Electrically programmable fuse unit and electrically programmable fuse memory unit

Abstract

The invention discloses an electrically programmable fuse unit. The electrically programmable fuse unit comprises a fuse pair and an NMOS (N-channel Metal Oxide Semiconductor) control tube, the fuse wire pair comprises a metal fuse wire and an AA fuse wire which are connected in parallel; one end of the fuse pair serves as a bit line end BL, and the other end of the fuse pair is connected with the drain end of the NMOS control tube; the grid end of the NMOS control tube is used as a word line end WL, and the source end of the NMOS control tube is used as a grounding end GND; two fuses, with different electromigration currents, of a fuse pair are programmed under two different programming voltages, equivalent resistance values of the two parallel fuses of the fuse pair are judged during reading operation, and corresponding logic values are output, so that the electrically programmable fuse unit has the capability of correcting the logic output values once, and the reliability of the electrically programmable fuse unit is improved. And secondary programming can be realized, and the reliability is improved.

Description

Technical Field

[0001] This invention relates to integrated circuit layout technology, specifically to an electrically programmable fuse (Efuse) unit and an electrically programmable fuse memory unit. Background Technology

[0002] Electrically programmable fuses (Efuse) are a type of one-time programmable memory (OTP). Their programming process utilizes electromigration (EM) to increase the fuse resistance value or even blow the fuse, then converts the resistance value into a corresponding logic value. However, due to special or unexpected reasons, Efuse units may experience issues during programming, such as the fuse blowing unexpectedly, not blowing completely, or having insufficient resistance after programming. This results in abnormal fuse resistance values, causing the read module to output incorrect logic values.

[0003] A typical Efuse cell consists of one fuse f1 and one NMOS control transistor Mn1, such as... Figure 1 As shown, the two ends of fuse f1 are connected to the Q terminal and the drain terminal of NMOS control transistor Mn1, respectively. The gate terminal of NMOS control transistor Mn1 is used to connect to the word line WL, and NMOS control transistor Mn1 is used to control the programming current flowing through fuse f1. During programming operations, the Q terminal of the fuse cell serves as the input terminal for the programming current; during read operations, its Q terminal is connected to the SA (Sense Amplifier) ​​module. The SA module generates a read current that flows from the Q terminal through fuse f1 and NMOS control transistor Mn1 to ground. The resistance value of fuse f1 after programming determines the logic output value of the SA module.

[0004] During programming of a conventional Efuse unit, fuse f1 undergoes electromigration or blows, increasing its resistance. The SA circuit in the read module compares the resistance of fuse f1 with a reference resistor to determine the programmed resistance value and outputs the corresponding logic value. However, if the Efuse unit experiences unexpected programming or abnormalities during the programming process (programming voltage, programming time, fuse characteristics, etc.), the resistance value of fuse f1 may change unexpectedly (e.g., become too low), causing the read module to output an incorrect logic value, ultimately significantly reducing the reliability of the Efuse unit.

[0005] To correct faulty bits, a common strategy is to store the address of the faulty bit and its correct value in a specific data area. When a read operation encounters these faulty addresses, the stored correct value replaces the faulty value at the actual address, effectively correcting the error from the output perspective. However, this method requires more bits in the storage area to define the relevant data for correcting even one faulty bit, making it inefficient in terms of area and incurring significant overhead. Therefore, it is only suitable for correcting a small number of faulty bits, such as 8 bits. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an electrically programmable fuse that has the ability to correct the logic output value once, can realize secondary programming, and has high reliability.

[0007] To solve the above-mentioned technical problems, the present invention provides an electrically programmable fuse unit, which includes a fuse pair and an NMOS control transistor Mn1;

[0008] The fuse pair includes a metal fuse f1 and an AA fuse f2 connected in parallel.

[0009] One end of the fuse pair serves as the bit line terminal BL, and the other end is connected to the drain terminal of the NMOS control transistor Mn1;

[0010] The gate terminal of the NMOS control transistor Mn1 is used as the word line terminal WL, and the source terminal is used as the ground terminal GND.

[0011] 100R1≤10R2≤5R3≤Rx;

[0012] R1 is the initial resistance of metal fuse f1, R2 is the initial resistance of AA fuse f2, R3 is the programmed resistance of AA fuse f2, and Rx is the programmed resistance of metal fuse f1.

[0013] Preferably, both ends of the AA fuse f2 are connected to the first metal layer M1 through contact holes;

[0014] The metal filament f1 is formed in the second metal layer M2;

[0015] The two ends of the metal fuse f1 are connected to the first metal layer M1 and the third metal layer M3 respectively through through holes;

[0016] The AA fuse f2, the first metal layer M1, the second metal layer M2, and the third metal layer M3 are stacked sequentially from bottom to top.

[0017] Preferably, the electrically programmable fuse unit can be programmed twice;

[0018] The first programming operation applies a low programming voltage VPL to the bit line BL, causing the metal fuse f1 to undergo electromigration. The resistance value of the metal fuse f1 increases from the initial resistance R1 to the programmed resistance Rx. This low programming voltage VPL does not cause the AA fuse f2 to undergo electromigration, and the resistance value of the AA fuse f2 remains unchanged at the initial resistance R2.

[0019] The second programming operation applies a high programming voltage VPH to the bit line BL, where the high programming voltage VPH is greater than the low programming voltage VPL.

[0020] During the second programming, the metal fuse f1, which had already undergone electromigration in the first programming, no longer undergoes electromigration. The metal fuse f1 maintains the same resistance Rx after programming. The high programming voltage VPH causes the AA fuse f2 to undergo electromigration, and the resistance value of the AA fuse f2 increases from the initial resistance R2 to the resistance R3 after programming.

[0021] Before the first programming operation, after the first programming operation, and after the second programming operation, the equivalent resistance value of the electrically programmable fuse unit exhibits three states.

[0022] Preferably, during the first programming operation, the low programming voltage VPL causes the current flowing through metal fuse f1 to exceed 20mA and the current flowing through AA fuse f2 to be less than 5mA.

[0023] During the second programming operation, the high programming voltage VPH caused the current flowing through fuse AA f2 to be greater than 5mA.

[0024] Preferably, the low programming voltage VPL is 450mV to 550mV;

[0025] The high programming voltage VPH is 900mV~1100mV;

[0026] The initial resistance R1 of the metal fuse f1 is 15-25Ω;

[0027] The initial resistance R2 of fuse f2 is 150~250Ω;

[0028] After programming AA fuse f2, the resistance R3 is 1500~3500 ohms;

[0029] After programming, the resistance Rx of the metal fuse f1 is greater than 20KΩ.

[0030] To solve the above-mentioned technical problems, the present invention provides an electrically programmable fuse memory unit including the aforementioned electrically programmable fuse unit, and further includes a read module;

[0031] The reading module includes a first sensitive amplifier SA1, a second sensitive amplifier SA2, a measurement path, a first reference path, and a second reference path;

[0032] The measurement path includes measuring the voltage divider resistor R00 and the NMOS measurement control transistor NR0;

[0033] The first reference path includes a first reference voltage divider resistor R01, a first reference resistor REF1, a first NMOS reference transistor ND1, and a first NMOS read control transistor NR1;

[0034] The second reference path includes a second reference voltage divider resistor R02, a second reference resistor REF2, a second NMOS reference transistor ND2, and a second NMOS read control transistor NR2;

[0035] The NMOS measurement control transistor NR0 has its drain terminal connected to one end of the measurement voltage divider resistor R00, the positive input terminal of the first sensitive amplifier SA1, and the positive input terminal of the second sensitive amplifier SA2, and its source terminal connected to the bit line terminal BL of an electrically programmable fuse unit.

[0036] The drain of the first NMOS read control transistor NR1 is connected to one end of the first reference voltage divider resistor R01 and the negative input terminal of the first sensitive amplifier SA1.

[0037] The drain of the second NMOS read control transistor NR2 is connected to one end of the second reference voltage divider resistor R02 and the negative input terminal of the second sensitive amplifier SA2;

[0038] The two ends of the first reference resistor REF1 are respectively connected to the source of the first NMOS read control transistor NR1 and the drain of the first NMOS reference transistor ND1;

[0039] The two ends of the second reference resistor REF2 are respectively connected to the source of the second NMOS read control transistor NR2 and the drain of the second NMOS reference transistor ND2;

[0040] The source terminals of the first NMOS reference transistor ND1 and the second NMOS reference transistor ND2 are grounded;

[0041] The gate terminals of the first NMOS reference transistor ND1, the second NMOS reference transistor ND2, the other end of the measuring voltage divider resistor R00, the other end of the first reference voltage divider resistor R01, and the other end of the second reference voltage divider resistor R02 are connected to the working voltage VDD.

[0042] The gate terminals of the NMOS measurement control transistor NR0, the first NMOS read control transistor NR1, and the second NMOS read control transistor NR2 are connected to the read control signal RD;

[0043] The output terminal DO1 of the first sensitive amplifier SA1 and the output terminal DO2 of the second sensitive amplifier SA2 are connected to the two input terminals of an XOR gate;

[0044] The output of the XOR gate serves as the read value Q output of the electrically programmable fuse unit.

[0045] Preferably, the first sensitive amplifier SA1 and the second sensitive amplifier SA2 have the same structure.

[0046] Preferably, the resistance values ​​of the first reference voltage divider resistor R01 and the second reference voltage divider resistor R02 are the same;

[0047] The resistance value of the first reference resistor REF1 is between the initial resistance R1 of the metal fuse f1 and the initial resistance R2 of the AA fuse f2;

[0048] The resistance value of the second reference resistor REF2 is between the initial resistance R2 of AA fuse f2 and the programmed resistance R3 of AA fuse f2.

[0049] Preferably, the resistance values ​​of the measuring voltage divider resistor R00, the first reference voltage divider resistor R01, and the second reference voltage divider resistor R02 are the same.

[0050] Preferably, the NMOS control transistor Mn1 in the electrically programmable fuse unit is the same as the first NMOS reference transistor ND1 and the second NMOS reference transistor ND2.

[0051] The electrically programmable fuse unit of the present invention is a 3-port (BL, WL, GND) device. Its fuse pair includes a metal fuse f1 and an AA fuse f2 connected in parallel. By programming the two fuses with different electromigration currents under two different programming voltages, and judging the equivalent resistance values ​​of the two parallel fuses during the read operation, the corresponding logic value is output. This enables the Efuse unit to correct the logic output value once, realizes the secondary programming of the Efuse unit, and improves the reliability of the Efuse unit. Attached Figure Description

[0052] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of a conventional electrically programmable fuse unit;

[0054] Figure 2 This is a circuit diagram of an embodiment of the electrically programmable fuse unit of the present invention;

[0055] Figure 3 This is a cross-sectional view of the fuse layout of an embodiment of the electrically programmable fuse unit of the present invention;

[0056] Figure 4 This is a schematic diagram of the first programming operation and resistance change of an embodiment of the electrically programmable fuse unit of the present invention;

[0057] Figure 5 This is a schematic diagram of the second programming operation and resistance change of an embodiment of the electrically programmable fuse unit of the present invention;

[0058] Figure 6 This is a circuit diagram of an embodiment of the electrically programmable fuse memory unit of the present invention. Detailed Implementation

[0059] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0060] Example 1

[0061] like Figure 2 As shown, an electrically programmable fuse unit includes a fuse pair and an NMOS control transistor Mn1;

[0062] The fuse pair includes a metal fuse f1 and an AA fuse f2 connected in parallel.

[0063] One end of the fuse pair serves as the bit line terminal BL, and the other end is connected to the drain terminal of the NMOS control transistor Mn1;

[0064] The gate terminal of the NMOS control transistor Mn1 is used as the word line terminal WL, and the source terminal is used as the ground terminal GND.

[0065] 100R1≤10R2≤5R3≤Rx;

[0066] R1 is the initial resistance of metal fuse f1, R2 is the initial resistance of AA fuse f2, R3 is the programmed resistance of AA fuse f2, and Rx is the programmed resistance of metal fuse f1.

[0067] Fuses can be made of metal, polysilicon, or AA (Active Area) materials. AA fuses are made of a diffusion layer structure within the active area. The physical properties and operating characteristics of the materials constituting these fuses differ. Metal and polysilicon fuses often experience thermal fracture during electromigration, while the materials constituting AA fuses only undergo electromigration. This unique characteristic results in a significantly different shape between AA and metal / polysilicon fuses, and AA fuses exhibit rapid heat dissipation and minimal heat accumulation during electromigration.

[0068] The electrically programmable fuse unit in Embodiment 1 is a 3-port (BL, WL, GND) device. Its fuse pair includes a metal fuse f1 and an AA fuse f2 connected in parallel. By programming the two fuses with different electromigration currents under two different programming voltages, and judging the equivalent resistance values ​​of the two parallel fuses during the read operation, the corresponding logic value is output. This enables the Efuse unit to correct the logic output value once, realizes the secondary programming of the Efuse unit, and improves the reliability of the Efuse unit.

[0069] Example 2

[0070] Based on the electrically programmable fuse unit of Embodiment 1, such as Figure 3 As shown, the two ends (anode and cathode) of the AA fuse f2 are connected to the first metal layer M1 through contact holes (CT);

[0071] The metal filament f1 is formed in the second metal layer M2;

[0072] The two ends (anode and cathode) of the metal fuse f1 are connected to the first metal layer M1 and the third metal layer M3 through through holes V1 and V2, respectively.

[0073] The AA fuse f2, the first metal layer M1, the second metal layer M2, and the third metal layer M3 are stacked sequentially from bottom to top.

[0074] Example 3

[0075] Based on Embodiment 1, the electrically programmable fuse unit can be programmed twice;

[0076] like Figure 4 As shown, in the first programming operation, a low programming voltage VPL is applied to the bit line BL and a high level (e.g., 1V to 5V) is applied to the word line WL. Since the initial resistance R1 of the metal fuse f1 is small (15 to 20 ohms), the low programming voltage VPL causes a large current (e.g., greater than 20mA) to flow through the metal fuse f1, causing electromigration in the metal fuse f1. The resistance value of the metal fuse f1 increases from the initial resistance R1 to the resistance Rx after programming. Since the initial resistance R2 of the AA fuse f2 is much larger than the initial resistance R1 of the metal fuse f1, and the low programming voltage VPL is small, the current flowing through the AA fuse f2 is very small (less than 5mA), and electromigration will not occur in the AA fuse f2. The resistance value of the AA fuse f2 remains unchanged at the initial resistance R2.

[0077] like Figure 5 As shown, the second programming operation applies a high programming voltage VPH to the bit line BL and a high level (e.g., 1V to 5V) to the word line WL. The high programming voltage VPH is greater than the low programming voltage VPL.

[0078] During the second programming, because the metal fuse f1, which had already undergone electromigration in the first programming, has a very large resistance Rx (tens of kilohms) after programming, the current flowing through the metal fuse f1 is extremely small. Since the metal fuse f1, which had already undergone electromigration in the first programming, does not undergo electromigration again, the metal fuse f1 maintains the same resistance Rx after programming. The high programming voltage VPH causes a large current (greater than 5mA) to flow through the AA fuse f2, causing the AA fuse f2 to undergo electromigration, and the resistance value of the AA fuse f2 increases from the initial resistance R2 to the resistance R3 after programming.

[0079] Before the first programming operation, after the first programming operation, and after the second programming operation, the equivalent resistance value of the electrically programmable fuse unit exhibits three states.

[0080] Preferably, during the first programming operation, the low programming voltage VPL causes the current flowing through metal fuse f1 to exceed 20mA and the current flowing through AA fuse f2 to be less than 5mA.

[0081] During the second programming operation, the high programming voltage VPH caused the current flowing through fuse AA f2 to be greater than 5mA.

[0082] Preferably, the low programming voltage VPL is 450mV to 550mV (e.g., 500mV);

[0083] The high programming voltage VPH is 900mV to 1100mV (e.g., 1000mV);

[0084] The initial resistance R1 of the metal fuse f1 is 15 to 25 Ω (e.g., 20 Ω);

[0085] The initial resistance R2 of fuse f2 is 150-250Ω (e.g., 200Ω);

[0086] After programming AA fuse f2, the resistance R3 is 400~3500 ohms (e.g., 3000Ω);

[0087] After programming the metal fuse f1, the resistance Rx is greater than 20KΩ (e.g., 30KΩ).

[0088] The electrically programmable fuse unit in Embodiment 3 is programmed twice under two different voltages, so that the equivalent resistance value of the electrically programmable fuse unit presents three states. The initial equivalent resistance Rt0 is the parallel resistance of the initial resistance R1 of the metal fuse f1 and the initial resistance R2 of the AA fuse f2. Since R1 is less than one-tenth of R2, Rt0 is approximately equal to R1. After the first programming operation, the equivalent resistance of the Efuse unit changes from the initial equivalent resistance Rt0 to the equivalent resistance Rt1 after one programming operation. Since the programming resistance Rx of the metal fuse f1 is much greater than the initial resistance R2 of the AA fuse f2, the equivalent resistance Rt1 after the first programming operation of the Efuse unit is approximately equal to R2. After the unit completes the second programming operation, the resistance value of the AA fuse f2 increases from the initial resistance R2 to the programming resistance R3. Since the programming resistance Rx of the metal fuse f1 is much greater than the programming resistance R3 of the AA fuse f2, the equivalent resistance Rt2 of the Efuse unit after the second programming operation is close to R3.

[0089] This electrically programmable fuse (Efuse) unit is first programmed and output at a low programming voltage VPL. If the output of the Efuse unit needs to be modified, it can be programmed a second time at a high programming voltage VPH to output the desired correct value. During the two programming processes, the equivalent resistance of the Efuse unit increases from Rt0 to Rt1, and then to Rt2. The equivalent resistance value of the Efuse unit can exhibit three states before, after, and after the first programming operation, respectively. The reading module can then output 0, 1, and the modified 0, respectively.

[0090] Example 4

[0091] An electrically programmable fuse memory cell, such as Figure 6 As shown, it includes the electrically programmable fuse unit and read module as in Embodiment 1;

[0092] The reading module includes a first sense amplifier SA1, a second sense amplifier SA2, a measurement path, a first reference path, and a second reference path;

[0093] The measurement path includes measuring the voltage divider resistor R00 and the NMOS measurement control transistor NR0;

[0094] The first reference path includes a first reference voltage divider resistor R01, a first reference resistor REF1, a first NMOS reference transistor ND1, and a first NMOS read control transistor NR1;

[0095] The second reference path includes a second reference voltage divider resistor R02, a second reference resistor REF2, a second NMOS reference transistor ND2, and a second NMOS read control transistor NR2;

[0096] The NMOS measurement control transistor NR0 has its drain terminal connected to one end of the measurement voltage divider resistor R00, the positive input terminal of the first sensitive amplifier SA1, and the positive input terminal of the second sensitive amplifier SA2, and its source terminal connected to the bit line terminal BL of an electrically programmable fuse unit.

[0097] The drain of the first NMOS read control transistor NR1 is connected to one end of the first reference voltage divider resistor R01 and the negative input terminal of the first sensitive amplifier SA1.

[0098] The drain of the second NMOS read control transistor NR2 is connected to one end of the second reference voltage divider resistor R02 and the negative input terminal of the second sensitive amplifier SA2;

[0099] The two ends of the first reference resistor REF1 are respectively connected to the source of the first NMOS read control transistor NR1 and the drain of the first NMOS reference transistor ND1;

[0100] The two ends of the second reference resistor REF2 are respectively connected to the source of the second NMOS read control transistor NR2 and the drain of the second NMOS reference transistor ND2;

[0101] The source terminals of the first NMOS reference transistor ND1 and the second NMOS reference transistor ND2 are grounded;

[0102] The gate terminals of the first NMOS reference transistor ND1, the second NMOS reference transistor ND2, the other end of the measuring voltage divider resistor R00, the other end of the first reference voltage divider resistor R01, and the other end of the second reference voltage divider resistor R02 are connected to the working voltage VDD.

[0103] The gate terminals of the NMOS measurement control transistor NR0, the first NMOS read control transistor NR1, and the second NMOS read control transistor NR2 are connected to the read control signal RD;

[0104] The output terminal DO1 of the first sensitive amplifier SA1 and the output terminal DO2 of the second sensitive amplifier SA2 are connected to the two input terminals of an XOR gate;

[0105] The output of the XOR gate serves as the output of the read value Q of the Efuse memory cell.

[0106] Preferably, the first sensitive amplifier SA1 and the second sensitive amplifier SA2 have the same structure.

[0107] Preferably, the resistance values ​​of the first reference voltage divider resistor R01 and the second reference voltage divider resistor R02 are the same;

[0108] The resistance value of the first reference resistor REF1 is between the initial resistance R1 of the metal fuse f1 and the initial resistance R2 of the AA fuse f2;

[0109] The resistance value of the second reference resistor REF2 is between the initial resistance R2 of AA fuse f2 and the programmed resistance R3 of AA fuse f2.

[0110] Preferably, the resistance values ​​of the measuring voltage divider resistor R00, the first reference voltage divider resistor R01, and the second reference voltage divider resistor R02 are the same.

[0111] Preferably, the NMOS control transistor Mn1 in the electrically programmable fuse unit is the same as the first NMOS reference transistor ND1 and the second NMOS reference transistor ND2.

[0112] In the electrically programmable fuse memory cell of Embodiment 4, the resistance value of the first reference resistor REF1 in the reference path of the first sensitive amplifier SA1 of the read module is greater than the resistance value of the second reference resistor REF2 in the reference path of the second sensitive amplifier SA2. The first sensitive amplifier SA1 and the second sensitive amplifier SA2 share a measurement path, which can realize the correct output of the three resistance states of the electrically programmable fuse cell.

[0113] Table 1 shows the truth table of the outputs of the electrically programmable fuse unit before and after the two programming operations. Q is the XOR logic output of DO1 and DO2. Before programming, the equivalent resistance of the electrically programmable fuse unit is approximately R1. Since it is smaller than the first reference resistor REF1 and the second reference resistor REF2, the outputs of the first sense amplifier SA1 (DO1) and the second sense amplifier SA2 (DO2) are both logic values ​​of 0. Therefore, the logic output Q after the XOR operation is 0. After the first programming, the equivalent resistance of the programmable fuse unit is approximately R2, which is between the first reference resistor REF1 and the second reference resistor REF. Therefore, the first sense amplifier SA1 outputs DO1 with a logic value of 1, and the second sense amplifier SA2 outputs DO2 with a logic value of 0. The logic output Q after XOR is 1. After the second programming, the equivalent resistance of the programmable fuse unit is R3, which is greater than the first reference resistor REF1 and the second reference resistor REF2. The outputs DO1 of the first sense amplifier SA1 and DO2 of the second sense amplifier SA2 are both logic values ​​of 1 (high level). Therefore, the logic output Q after XOR is 0, thus achieving the secondary programming result of the programmable fuse unit from 0 to 1 and then from 1 to 0.

[0114] Table 1: Truth Table of Programming Outputs for Efuse Memory Units

[0115] DO1 DO2 Q R1 before programming 0 0 0 R2 after the first programming 1 0 1 R3 after the second programming 1 1 0

[0116] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electrically programmable fuse cell, characterized by, It comprises one fuse pair and one NMOS control tube (Mn1); The fuse pair comprises one metal fuse (f1) and one AA fuse (f2) connected in parallel; One end of the fuse pair is connected to the bit line end BL, and the other end is connected to the drain end of the NMOS control tube (Mn1); The gate end of the NMOS control tube (Mn1) is connected to the word line end WL, and the source end is connected to the ground end GND; 100R1≤10R2≤5R3≤Rx; R1 is the initial resistance of the metal fuse (f1), R2 is the initial resistance of the AA fuse (f2), R3 is the resistance of the AA fuse (f2) after programming, and Rx is the resistance of the metal fuse (f1) after programming.

2. The electrically programmable fuse cell according to claim 1, wherein The two ends of the AA fuse (f2) are connected to the first metal layer (M1) through contact holes; The metal fuse (f1) is formed in the second metal layer (M2); The two ends of the metal fuse (f1) are connected to the first metal layer (M1) and the third metal layer (M3) through through holes, respectively; The AA fuse (f2), the first metal layer (M1), the second metal layer (M2), and the third metal layer (M3) are arranged in a stack from bottom to top.

3. The electrically programmable fuse cell according to claim 1, wherein The electrically programmable fuse cell can be programmed twice; In the first programming operation, a low programming voltage (VPL) is applied to the bit line end BL to cause electromigration of the metal fuse (f1), and the resistance of the metal fuse (f1) increases from the initial resistance R1 to the resistance Rx after programming; the low programming voltage (VPL) does not cause electromigration of the AA fuse (f2), and the resistance of the AA fuse (f2) remains unchanged at the initial resistance R2; In the second programming operation, a high programming voltage (VPH) is applied to the bit line end BL, and the high programming voltage (VPH) is greater than the low programming voltage (VPL); In the second programming, the metal fuse (f1) that has undergone electromigration in the first programming does not undergo electromigration again, and the metal fuse (f1) remains at the resistance Rx after programming; the high programming voltage (VPH) causes electromigration of the AA fuse (f2), and the resistance of the AA fuse (f2) increases from the initial resistance R2 to the resistance R3 after programming; Before the first programming operation, after the first programming operation, and after the second programming operation, the equivalent resistance of the electrically programmable fuse cell presents three states.

4. The electrically programmable fuse cell according to claim 3, wherein In the first programming operation, the low programming voltage (VPL) causes the current flowing through the metal fuse (f1) to exceed 20 mA, and the current flowing through the AA fuse (f2) is less than 5 mA; In the second programming operation, the high programming voltage (VPH) causes the current flowing through the AA fuse (f2) to be greater than 5 mA.

5. The electrically programmable fuse cell according to claim 3, wherein The low programming voltage (VPL) is 450 mV to 550 mV; The high programming voltage (VPH) is 900 mV to 1100 mV; The initial resistance R1 of the metal fuse (f1) is 15 to 25 Ω. The initial resistance R2 of the AA fuse (f2) is 150-250Ω; The programmed resistance R3 of the AA fuse (f2) is 1500-3500Ω; The programmed resistance Rx of the metal fuse (f1) is greater than 20KΩ.

6. An electrically programmable fuse memory cell comprising the electrically programmable fuse cell of claim 1, wherein, A reading module is further included; The reading module includes a first sensitive amplifier (SA1), a second sensitive amplifier (SA2), a measurement path, a first reference path and a second reference path; The measurement path includes a measurement voltage dividing resistor (R00) and an NMOS measurement control tube (NR0); The first reference path includes a first reference voltage dividing resistor (R01), a first reference resistor (REF1), a first NMOS reference tube (ND1) and a first NMOS reading control tube (NR1); The second reference path includes a second reference voltage dividing resistor (R02), a second reference resistor (REF2), a second NMOS reference tube (ND2) and a second NMOS reading control tube (NR2); The drain of the NMOS measurement control tube (NR0) is connected to one end of the measurement voltage dividing resistor (R00), the positive input of the first sensitive amplifier (SA1) and the positive input of the second sensitive amplifier (SA2), and the source is connected to the bit line BL of an electrically programmable fuse unit; The drain of the first NMOS reading control tube (NR1) is connected to one end of the first reference voltage dividing resistor (R01) and the negative input of the first sensitive amplifier (SA1); The drain of the second NMOS reading control tube (NR2) is connected to one end of the second reference voltage dividing resistor (R02) and the negative input of the second sensitive amplifier (SA2); The two ends of the first reference resistor (REF1) are respectively connected to the source of the first NMOS reading control tube (NR1) and the drain of the first NMOS reference tube (ND1); The two ends of the second reference resistor (REF2) are respectively connected to the source of the second NMOS reading control tube (NR2) and the drain of the second NMOS reference tube (ND2); The sources of the first NMOS reference tube (ND1) and the second NMOS reference tube (ND2) are connected to ground; The gate of the first NMOS reference tube (ND1), the gate of the second NMOS reference tube (ND2), the other end of the measurement voltage dividing resistor (R00), the other end of the first reference voltage dividing resistor (R01) and the other end of the second reference voltage dividing resistor (R02) are connected to the working voltage VDD; The gates of the NMOS measurement control tube (NR0), the first NMOS reading control tube (NR1) and the second NMOS reading control tube (NR2) are connected to the reading control signal RD; The output DO1 of the first sensitive amplifier (SA1) and the output DO2 of the second sensitive amplifier (SA2) are connected to the two input ends of an exclusive OR gate; The output of the exclusive OR gate is used as the reading value Q output end of the electrically programmable fuse unit.

7. The electrically programmable fuse memory unit according to claim 6, wherein The first sensitive amplifier (SA1) and the second sensitive amplifier (SA2) are of the same structure.

8. The electrically programmable fuse memory unit according to claim 6, wherein The resistance values of the first reference voltage dividing resistor (R01) and the second reference voltage dividing resistor (R02) are the same. The resistance value of the first reference resistor (REF1) is between the initial resistance R1 of the metal fuse (f1) and the initial resistance R2 of the AA fuse (f2). The resistance value of the second reference resistor (REF2) is between the initial resistance R2 of the AA fuse (f2) and the programmed resistance R3 of the AA fuse (f2).

9. The electrically programmable fuse memory cell according to claim 6, characterized in that The resistance values of the measurement voltage dividing resistor (R00), the first reference voltage dividing resistor (R01), and the second reference voltage dividing resistor (R02) are the same.

10. The electrically programmable fuse memory cell according to claim 6, characterized in that The NMOS control transistor (Mn1) in the electrically programmable fuse cell is the same as the first NMOS reference transistor (ND1) and the second NMOS reference transistor (ND2).

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