Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the device comprises the components of a substrate which is provided with a first source region and a first body region on a first surface; the at least one groove is formed on the first surface of the substrate; the fin-shaped grid electrode is located on the side wall of one side of the groove; the interlayer dielectric layer covers the fin-shaped grid electrode and partially fills the groove; the second source region is located at the bottom of the groove and connected with the fin-shaped grid electrode, the second body region surrounds the second source region, the second source region is provided with the first doping type, and the second body region is provided with the second doping type; the shielding region surrounds the bottom of the groove and has the second doping type, and the depth of the shielding region is larger than that of the second body region; and the source contact layer is in contact with the top of the first source region and the part, which is not covered by the interlayer dielectric layer, in the groove. The device can increase the channel density, reduce the contact resistance and improve the safety.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Silicon carbide (SiC) MOSFETs (metal-oxide-semiconductor field-effect transistors) are widely used in various fields of the power electronics industry due to their advantages such as high breakdown field strength and high thermal conductivity. Existing SiC MOSFETs are mainly divided into VDMOS structures using planar gates and TMOS structures using trench gates. Currently, traditional planar or trench SiC MOSFETs face a trade-off between on-resistance and breakdown voltage; limited by process complexity and cell pitch, it is difficult to further reduce on-resistance.

[0003] Among them, the TMOS structure has a vertical channel. Due to the anisotropy of the SiC crystal plane, it has higher channel mobility and larger cell density compared with the horizontal channel of VDMOS. However, the trench gate structure is prone to gate oxide breakdown under high stress due to electric field concentration, causing gate oxide reliability issues. The superjunction structure achieves charge balance through alternating doped P-type and N-type regions, optimizing the electric field distribution and improving the breakdown voltage, but it also requires more stringent process control. Existing trench and superjunction structures require multiple high-precision photolithography etching and high-energy ion implantation, resulting in high manufacturing costs and low yields. The VDMOS structure with a planar gate has excessively high gate-drain capacitance, leading to large switching losses and affecting performance in high-frequency applications. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this application provides a semiconductor device, which includes: A substrate having a first doping type, wherein a first source region of the first doping type and a first body region of the second doping type are formed on a first surface of the substrate; At least one trench is formed on the first surface of the substrate, the trench penetrating the first body region and the first source region and extending along a second direction; A fin-shaped gate is located on one sidewall of the trench, and a gate dielectric layer is formed between the fin-shaped gate and the substrate; An interlayer dielectric layer covers the finned gate and fills a portion of the trench; A second source region and a second body region, wherein the second source region is located at the bottom of the trench and connected to the fin gate, and the second body region surrounds the second source region, wherein the second source region has a first doping type and the second body region has a second doping type; A shielding region, at least surrounding the bottom of the trench, having a second doping type, wherein the depth of the shielding region is greater than the depth of the second body region; A source contact layer that contacts the top of the first source region and the portion of the trench not covered by the interlayer dielectric layer.

[0006] In one embodiment, at least one columnar doped region is further formed in the substrate, the columnar doped region having a second doping type.

[0007] In one embodiment, the trench includes a first trench and a second trench, the first trench and the second trench are spaced apart along a second direction, the first trench includes a first sidewall and a second sidewall, the second trench includes a third sidewall and a fourth sidewall, and the second sidewall is adjacent to the third sidewall. The fin gate includes a first fin gate located on the first sidewall of the first trench and a third fin gate located on the third sidewall of the second trench. The source contact layer contacts the second sidewall of the first trench and the portion of the bottom of the first trench not covered by the interlayer dielectric layer, and also contacts the fourth sidewall of the second trench and the portion of the bottom of the second trench not covered by the interlayer dielectric layer.

[0008] In one embodiment, the shielding area includes a first shielding area and a second shielding area, wherein the first shielding area at least surrounds the bottom of the first trench and the second sidewall, and the second shielding area at least surrounds the bottom of the second trench and the fourth sidewall.

[0009] In one embodiment, the second source region is alternately arranged with a spacer region of the second doping type in the second direction.

[0010] In one embodiment, the semiconductor device further includes: A source metal layer covers the source contact layer; A drain contact layer and a drain metal layer, wherein the drain contact layer is formed on the second surface of the substrate and the drain metal layer covers the drain contact layer.

[0011] In one embodiment, the source contact layer located at the bottom of the trench comprises alternating ohmic contact layers and Schottky contact layers.

[0012] Another aspect of this application provides a method for manufacturing a semiconductor device, the method comprising: A substrate of a first doped type is provided, wherein a first source region of the first doped type and a first body region of the second doped type are formed on a first surface of the substrate; The first surface of the substrate is etched to form at least one trench penetrating the first body region and the first source region, the trench extending along a second direction; A second source region and a second body region surrounding the second source region are formed at the bottom of the trench. The second source region has a first doping type, and the second body region has a second doping type. A second doped shielding region is formed that at least surrounds the bottom of the trench, the depth of which is greater than the depth of the second bulk region; A gate dielectric layer, a fin gate, and an interlayer dielectric layer are sequentially formed on one sidewall of the trench. The interlayer dielectric layer partially fills the trench, and the fin gate is connected to the second source region. A source contact layer is formed, which contacts the top of the first source region and the portion of the trench not covered by the interlayer dielectric layer.

[0013] In one embodiment, prior to forming the trench, the method further includes: At least one columnar doped region is formed in the substrate, the columnar doped region having a second doping type.

[0014] In one embodiment, the trench includes a first trench and a second trench spaced apart along the first direction, the first trench includes a first sidewall and a second sidewall, the second trench includes a third sidewall and a fourth sidewall, and the second sidewall is adjacent to the third sidewall. The fin gate includes a first fin gate located on the first sidewall of the first trench and a third fin gate located on the third sidewall of the second trench. The formation of a gate dielectric layer and a fin gate on one sidewall of the trench includes: A gate dielectric layer and a gate electrode layer are sequentially formed in the first trench and the second trench; The gate electrode layer is etched to form a first fin gate located on the first sidewall of the first trench, a second fin gate located on the second sidewall of the first trench, a third fin gate located on the third sidewall of the second trench, and a fourth fin gate located on the third sidewall of the second trench; the interlayer dielectric layer covers the first fin gate and the third fin gate. Remove the second fin gate, the fourth fin gate, and the gate dielectric layer below the second fin gate and the fourth fin gate that are not covered by the interlayer dielectric layer.

[0015] In one embodiment, the trench includes a first trench and a second trench spaced apart along the first direction, the first trench including a first sidewall and a second sidewall, the second trench including a third sidewall and a fourth sidewall, the second sidewall being adjacent to the third sidewall; the formation of a second doped type shielding region surrounding the bottom of the trench includes: Before forming the trench, the first surface of the substrate is subjected to ion implantation of a second doping type to form a first shielding region and a second shielding region; The etching of the first surface of the substrate to form at least one trench penetrating the first body region and the first source region includes: The first shielding area is etched to form the first trench in the first shielding area, and the second shielding area is etched to form the second trench in the second shielding area, wherein the first shielding area surrounds the bottom and second sidewall of the first trench, and the second shielding area surrounds the bottom and fourth sidewall of the second trench.

[0016] In one embodiment, forming the interlayer dielectric layer covering the first fin gate and the third fin gate includes: An interlayer dielectric layer is deposited to fill the first trench and the second trench and to cover the first surface of the substrate; The interlayer dielectric layer is planarized to remove the interlayer dielectric layer located above the first surface; A patterned photoresist layer is formed, which shields the first fin gate, the third fin gate, and the first source region located between the second fin gate and the third fin gate, and exposes the second fin gate and the fourth fin gate. Dry etching is performed on the interlayer dielectric layer to remove the portion of the interlayer dielectric layer not covered by the photoresist layer.

[0017] In one embodiment, removing the second fin gate, the fourth fin gate, and the gate dielectric layer located below the second fin gate and the fourth fin gate that are not covered by the interlayer dielectric layer includes: Perform a first wet etching process to remove the second fin gate and the fourth fin gate that are not covered by the interlayer dielectric layer, exposing the underlying gate dielectric layer; A second wet etching process is performed to remove the exposed gate dielectric layer.

[0018] In one embodiment, after the step of forming the source contact layer, the method further includes: Form a source metal layer covering the source contact layer; The second surface of the substrate is thinned; A drain contact layer and a drain metal layer covering the drain contact layer are formed on the thinned second surface.

[0019] In one embodiment, forming the second source region includes: A plurality of second source regions are formed at intervals in the second direction, and a second doping type spacer region is formed between adjacent second source regions.

[0020] According to the semiconductor device and manufacturing method provided in this application, a higher channel density is achieved by using parallel vertical and horizontal channels. This structure reconfigures the source contact layout, reduces the cell pitch, lowers the on-resistance, enhances short-circuit and avalanche tolerance, and proposes a corresponding process flow.

[0021] Furthermore, the effective grounding of the shielding region significantly alleviates the electric field at the bottom of the gate dielectric layer, improving the gate oxide reliability of the SiC MOSFET device. The effective shielding effect of the shielding region also reduces gate drain charge (Qgd), resulting in lower switching losses. When a short circuit occurs, the drain voltage is high, and the JFET region in the shielding region and body region is pinched off, thereby reducing the device's saturation current, improving its short-circuit capability, and enhancing its robustness.

[0022] Finally, the manufacturing method of this application embodiment has a simple process flow, does not require etching of small-sized trench widths and high-energy ion implantation, which can reduce costs and increase yield. Attached Figure Description

[0023] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0024] In the attached image: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figures 2A to 2T A schematic cross-sectional view is shown of a semiconductor device obtained by sequentially performing each step of a manufacturing method according to an embodiment of this application; Figure 2U A top view of a semiconductor device according to an embodiment of this application is shown; Figure 2V A top view of a semiconductor device according to another embodiment of this application is shown; Figure 2W A top view of a semiconductor device according to yet another embodiment of this application is shown. Detailed Implementation

[0025] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0026] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0028] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0031] Below, for reference Figures 1 to 2W The manufacturing method of the semiconductor device according to the embodiments of this application will be described in detail.

[0032] like Figure 1 As shown, the manufacturing method of this application embodiment includes the following steps: In step S101, a substrate of a first doped type is provided, and a first source region of the first doped type and a first body region of the second doped type located below the first source region are formed on the first surface of the substrate; In step S102, the first surface of the substrate is etched to form at least one trench penetrating the first body region and the first source region, the trench extending along a second direction; In step S103, a second source region and a second body region surrounding the second source region are formed at the bottom of the trench. The second source region has a first doping type, and the second body region has a second doping type. In step S104, a second doped shielding region is formed that at least surrounds the bottom of the trench, the depth of the shielding region being greater than the depth of the second body region; In step S105, a gate dielectric layer, a fin gate, and an interlayer dielectric layer are sequentially formed on one sidewall of the trench. The interlayer dielectric layer partially fills the trench, and the fin gate is connected to the second source region. In step S106, a source contact layer is formed, which contacts the top of the first source region and the portion of the trench not covered by the interlayer dielectric layer.

[0033] First, such as Figure 2A As shown, a substrate 200 of the first doping type is provided.

[0034] Exemplarily, the substrate 200 may include a silicon carbide substrate, specifically including a silicon carbide substrate and a silicon carbide epitaxial layer formed on the silicon carbide substrate, both the silicon carbide substrate and the silicon carbide epitaxial layer having a first doping type. The doping concentration of the silicon carbide epitaxial layer may be lower than the doping concentration of the silicon carbide substrate. Optionally, the silicon carbide epitaxial layer may serve as a drift region of the device. The presence of the drift region can provide the breakdown voltage of the device and act as a buffer, while reducing the parasitic capacitance between the source and drain. In one embodiment, the first doping type is N-type, that is, the silicon carbide substrate 200 is an N-type substrate, and correspondingly, the second doping type is P-type; in other embodiments, the first doping type may also be P-type, and correspondingly, the second doping type is N-type.

[0035] In a specific example, the silicon carbide substrate 200 is an N-type doped 4H-SiC substrate (i.e., the silicon and carbon lattice structures exhibit a periodic arrangement of four different layer sequences), and the epitaxial layer is an N-type doped SiC epitaxial layer. The doping concentration of the SiC substrate is 1e19cm⁻¹. -3 The doping concentration of the SiC epitaxial layer is 1e15cm. -3 -1e18cm -3 The thickness of the SiC epitaxial layer is 10μm-20μm. The substrate 200 may also include gallium nitride, gallium oxide, gallium nitride silicon, germanium or other suitable semiconductor materials.

[0036] In one embodiment, at least one columnar doped region 201 may also be formed in the substrate 200, such as Figure 2A As shown, the columnar doped region 201 can be formed by alternating ion implantation and epitaxial processes. For example, an epitaxial layer is first formed on the substrate surface, followed by ion implantation on the surface of the epitaxial layer to form the columnar doped region 201; then, an epitaxial layer is formed again on top of the columnar doped region 201.

[0037] For example, P-type columnar doped regions and N-type epitaxial layers are alternately arranged to form a superjunction structure. The doping concentration of the columnar doped regions 201 is substantially the same as the doping concentration of the epitaxial layers, at least on the same order of magnitude, so that the N-type and P-type doped regions achieve charge balance. When the doping concentration of the SiC epitaxial layer is 1e15cm⁻¹ -3 -1e18cm -3 At that time, the doping concentration of the columnar doped region was also 1e15cm. -3 -1e18cm -3 When the thickness of the SiC epitaxial layer is 10μm-20μm, the height of the columnar doped region can be 3μm-10μm.

[0038] After forming the columnar doped region 201, as Figure 2B As shown, ion implantation of the second doping type is performed on the substrate 200 to form the first bulk region 202. Then, as... Figure 2C As shown, ion implantation of a first doping type is performed on the surface of the first body region 202 to form a first source region 203. Exemplarily, the first body region 202 is lightly p-type doped, and the first source region 203 is heavily n-type doped.

[0039] Next, as Figure 2D As shown, a second type of ion implantation of the first surface of the substrate 200 is performed to form one or more second body regions 204. The second body regions 204 extend along a second direction. Then, as... Figure 2E As shown, ion implantation of a first doping type is performed on the first surface of substrate 200 to form one or more second source regions 205. The second source regions 205 are located within the second body region 204, and their depth and width are both smaller than those of the second body region 204. Exemplarily, the second body region 204 is lightly p-type doped, and the second source region 205 is heavily n-type doped. Optionally, ion implantation can also be performed on the bottom of the trench after trench formation to form the second body region 204 and the second source region 205.

[0040] In one embodiment, such as Figure 2U As shown, the second source region 205 extends continuously along the second direction. In another embodiment, as... Figure 2V As shown, the second source region 205 is alternately arranged with the second doped type spacer region 216 in the second direction. This design is mainly a trade-off between channel density and electric field shielding effect.

[0041] Next, as Figure 2FAs shown, a second type of ion implantation of the first surface of the substrate 200 is performed to form a shielding region 206. The shielding region 206 partially overlaps with and intersects with the second source region 205 and the second body region 204. The depth of the shielding region 206 is greater than the depth of the second body region 204. Exemplarily, the shielding region 206 is heavily p-type doped.

[0042] For example, the shielding region 206 includes at least two, specifically including a first shielding region and a second shielding region spaced apart. The shielding region 206 and the columnar doped region 201 are staggered in both the lateral and longitudinal directions. Each columnar doped region 201 is located below the shielding region 206 in the longitudinal direction and between adjacent shielding regions 206 in the lateral direction.

[0043] Next, as Figure 2G As shown, the first surface of the substrate 200 is etched to form at least one groove penetrating the first body region 202 and the first source region 203, such as... Figure 2U-Figure 2W As shown, at least one groove extends along the second direction.

[0044] Exemplarily, at least one groove includes a first trench ( Figure 2G Left side) and second trench ( Figure 2G (right side), such as Figure 2U-Figure 2W As shown, the first groove and the second groove are spaced apart from each other along the first direction (i.e., the x-direction) and extend along the second direction (i.e., the y-direction).

[0045] Exemplarily, the first trench includes a first sidewall and a second sidewall, and the second trench includes a third sidewall and a fourth sidewall, the second sidewall being adjacent to the third sidewall, i.e., the first sidewall, second sidewall, third sidewall, and fourth sidewall are arranged sequentially in the x-direction. The base 200 between the second sidewall and the third sidewall constitutes a mesa region. The channel is formed in the body region 202 near the trench sidewall.

[0046] Exemplarily, the first and second trenches can extend along the [11-20] crystal orientation and be arranged along the [-1100] crystal orientation; alternatively, they can extend along the [-1100] crystal orientation and be arranged along the [11-20] crystal orientation. Exemplarily, the trench aspect ratio is 0.5-2, and the width of the trench is greater than the width of the plateau region between the second and third sidewalls. Exemplarily, the angle of the trench sidewalls is 86°~90°. Exemplarily, a hard mask layer 207 is formed on a first surface of a substrate 200. Dry etching is performed on the first surface of the substrate 200 based on the hard mask layer 207 to form a plurality of trenches. The plurality of trenches extend along a second direction and are spaced apart along a first direction. The plurality of trenches may have the same depth and width. A first trench and a second trench refer to two adjacent trenches among the plurality of trenches. Exemplarily, the material of the hard mask layer 207 includes, but is not limited to, silicon oxide.

[0047] In this embodiment, the depth of the trench is less than the depth of the second source region 205, such that the second source region 205 is formed at the bottom of the trench. A first trench is formed in a first shielding region, and a second trench is formed in a second shielding region, such that the first shielding region surrounds the bottom and second sidewall of the first trench, and the second shielding region surrounds the bottom and fourth sidewall of the second trench. That is, the shielding region 206 is formed on the side of the trench where the finned gate is not formed, and terminates near the bottom corner of the trench on the other side. The second body region 204, used to form the horizontal channel, and the shielding region 205 simultaneously serve to alleviate the electric field at the bottom of the gate dielectric layer, protect the trench gate, and enhance the reliability of the gate dielectric layer. The depth of the shielding region 206 can be 1.5-2.5 times the trench depth. The columnar doped region 201 is located laterally between adjacent trenches.

[0048] In this embodiment, the epitaxial layer features alternating P-type and N-type doped regions. Under reverse breakdown voltage conditions, these regions deplete each other, achieving charge compensation. The introduction of the superjunction structure allows for increased doping concentration in the drift region at the same breakdown voltage, reducing the device's on-resistance. Furthermore, the shielding region 206 is effectively grounded, significantly mitigating the electric field at the bottom of the gate dielectric layer and improving the gate oxide reliability of the SiC MOSFET device. The effective shielding effect of the shielding region 206 also reduces Qgd (gate drain charge), resulting in lower switching losses.

[0049] In addition, when the device is short-circuited, the drain voltage is large, and the JFET region of the heavily P-type doped shielding region 206 and the lightly P-type doped body region will be pinched off, thereby reducing the saturation current of the device, improving the short-circuit capability of the device, and enhancing the robustness of the device.

[0050] Next, as Figure 2H As shown, a high-temperature oxidation process is performed, followed by annealing in a NO (nitric oxide) atmosphere, to form a gate dielectric layer 208 covering the bottom and sidewalls of the first and second trenches, as well as the first surface of the substrate. The material of the gate dielectric layer 208 includes, but is not limited to, silicon oxide. Exemplarily, the thickness of the gate dielectric layer 208 is 400 Å to 1000 Å.

[0051] Next, as Figure 2I As shown, a gate electrode layer 209 is deposited on the gate dielectric layer 208. The gate electrode layer 209 includes, but is not limited to, an in-situ doped polysilicon layer. The thickness of the gate electrode layer 209 is less than half the width of the trench, meaning that the gate electrode layer 209 does not completely fill the trench, and a void is formed in the middle region of the trench.

[0052] Next, as Figure 2JAs shown, the gate electrode layer 209 is etched to form a first finned gate 209A and a second finned gate 209B respectively disposed on the first and second sidewalls of the first trench, and a third finned gate 209C and a fourth finned gate 209D respectively disposed on the third and fourth sidewalls of the second trench. The second finned gate 209B and the third finned gate 209C are symmetrically disposed on opposite sides of the mesa region. A finned gate refers to a gate that only partially fills the trench, with its sidewall adjacent to the mesa region exhibiting a shape similar to a spacer wall—narrower at the top and wider at the bottom—rather than filling the entire trench as in a traditional trench gate.

[0053] For example, the gate electrode layer 209 can be etched using a dry etching process or a combination of dry and wet etching to form a fin-shaped gate. In this process, the gate electrode layer 209 is etched along a direction perpendicular to the surface of the substrate, thereby removing the thinner gate electrode layer 209 located on the substrate surface and in the middle of the trench, while retaining the gate electrode layer 209 located on the trench sidewalls, thus forming a fin-shaped gate that is narrower at the top and wider at the bottom.

[0054] Next, an interlayer dielectric layer 210 is formed in the first trench and the second trench, covering the fin gate.

[0055] Specifically, the interlayer dielectric layer 210 is formed in the first trench and the second trench, located on the side of the first trench near the first sidewall and the side of the second trench near the third sidewall, covering the first fin gate 209A and the third fin gate 209C, and exposing the second fin gate 209B and the fourth fin gate 209D.

[0056] Specifically, firstly, as Figure 2K As shown, an interlayer dielectric layer 210 is deposited to fill the first trench and the second trench and to cover the first surface of the substrate 200. Exemplarily, the material of the interlayer dielectric layer 210 includes one or more of USG (undoped silicon glass), PSG (phosphate glass), BPSG (borophosphosilicate glass), etc.

[0057] Next, as Figure 2L As shown, the interlayer dielectric layer 210 is planarized to remove the interlayer dielectric layer 210 located above the first surface, retaining only the interlayer dielectric layer 210 located in the first trench and the second trench. Furthermore, the planarization process may also remove the gate dielectric layer 208 located on the first surface. The planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0058] Next, as Figure 2MAs shown, a patterned photoresist layer 211 is formed above the substrate 200. The patterned photoresist layer 211 shields the first fin gate 209A, the third fin gate 209C, and the substrate 200 located between the second fin gate 209B and the third fin gate 209C, and exposes the second fin gate 209B and the fourth fin gate 209D.

[0059] Next, as Figure 2N As shown, the interlayer dielectric layer 210 is dry etched to remove the interlayer dielectric layer 210 that is not covered by the photoresist layer 211.

[0060] For example, the dry etching is selective dry etching. Since the interlayer dielectric layer 210 and the gate dielectric layer 208 have similar properties, the dry etching removes the unmasked portion of the interlayer dielectric layer 210 in the first trench, as well as the portion of the gate dielectric layer 208 located between the first fin gate 209A and the second fin gate 209B. It also removes the unmasked portion of the interlayer dielectric layer 210 in the second trench, as well as the portion of the gate dielectric layer 208 located between the third fin gate 209C and the fourth fin gate 209D. At this time, the interlayer dielectric layer 210 on the second fin gate 209B and the fourth fin gate 209D is removed and exposed.

[0061] Next, the second fin gate 209B, the fourth fin gate 209D, and the gate dielectric layer 208 located below the second fin gate 209B and the fourth fin gate 209D that are not covered by the interlayer dielectric layer 210 are removed to expose the substrate 200 below the gate dielectric layer 208.

[0062] Specifically, firstly, as Figure 2O As shown, a first wet etching process is performed to remove the second fin gate 209B and the fourth fin gate 209D that are not covered by the interlayer dielectric layer 210, exposing the underlying gate dielectric layer 208. At this time, the interlayer dielectric layer 210 is formed on the first fin gate 209A and the third fin gate 209C, which can serve as a mask layer for wet etching.

[0063] Next, as Figure 2P As shown, a second wet etching process is performed to remove the gate dielectric layer 208 exposed after the first wet etching process.

[0064] Specifically, an etchant with a high etching rate for silicon oxide and a low etching rate for silicon (such as hydrofluoric acid solution) can be used to remove the exposed gate dielectric layer 208. Since the gate dielectric layer 208 is relatively thin while the interlayer dielectric layer 210 is relatively thick, the second wet etching process can completely remove the gate dielectric layer 208, while only removing part of the interlayer dielectric layer 210. This allows the interlayer dielectric layer 210 covering the first fin gate 209A and the third fin gate 209C to also form a fin-like structure with inclined sidewalls, similar to a gate.

[0065] In this embodiment, a first body region 202 and a first source region 203 are formed on the substrate surface. A vertical channel is formed in the first body region 202 near the trench sidewall, forming a TMOS structure. A second body region 204 and a second source region 205 are formed at the bottom of the fin gate, thereby forming a horizontal channel and a VDMOS structure. The vertical and horizontal channels are connected in parallel, thereby increasing the channel density.

[0066] Next, a source contact layer 213 is formed, which contacts the top of the first source region 203 and the portion of the trench not covered by the interlayer dielectric layer 210.

[0067] In this embodiment, a portion of the source contact layer 213 is transferred to the bottom of the trench, which can shorten the width of the mesa region, reduce the cell pitch, and decrease the on-resistance; at the same time, it increases the area of ​​the source contact layer 213 and reduces the contact resistance.

[0068] Specifically, firstly, as Figure 2Q As shown, a metal material 212 is deposited in the first surface, the first trench, and the second trench of the substrate 200, and an annealing process is performed to react the deposited metal material 212 with the substrate 200 in contact with it to form a metal silicide, namely the source contact layer 213. The metal material includes, but is not limited to, nickel (Ni), and the annealing process includes, but is not limited to, rapid thermal annealing (RTA). The substrate 200 in contact with the metal material 212 includes portions of the first trench and the second trench located at the bottom and sidewalls that are not covered by the interlayer dielectric layer 210, as well as the first surface of the substrate 200. Specifically, the source contact layer 213 is formed on the second sidewall of the first trench, the portion of the first trench bottom not covered by the interlayer dielectric layer 210, the fourth sidewall of the second trench, and the portion of the second trench bottom not covered by the interlayer dielectric layer 210.

[0069] Next, as Figure 2R As shown, the unreacted metal material 212, i.e., the metal material 212 located on the interlayer dielectric layer 210, is removed. Exemplarily, a wet etching process can be used to remove the unreacted metal material 212.

[0070] In another embodiment, such as Figure 2W As shown, the source contact layer 213 located at the bottom of the trench may include alternating ohmic contact layers 213A and Schottky contact layers 213B. The ohmic contact layer 213A is a metal silicide layer, and the Schottky contact layer 213B can be a high-purity metal layer formed by sputtering or electron beam evaporation. Introducing the Schottky contact layer 213B at the bottom of the trench allows it to operate in reverse conduction mode, resulting in a lower on-state voltage and a lower reverse recovery current.

[0071] Next, as Figure 2S As shown, a source metal layer 214 is formed covering the source contact layer. Exemplarily, the source metal layer 214 includes Ti, TiN, and AlCu alloys, etc. The source metal layer 214 fills the first trench and the second trench, and covers the first surface of the substrate 200.

[0072] Next, as Figure 2T As shown, the second surface of the substrate 200 is thinned; a drain contact layer (not shown) and a drain metal layer 215 covering the drain contact layer are formed on the thinned second surface. In one example, a Ni metal layer may be deposited on the second surface of the thinned substrate 200 and laser annealed to form an ohmic contact layer, followed by sputtering TiNiAg to form the drain metal layer 215.

[0073] Thus, the process steps of the semiconductor device manufacturing method according to an embodiment of this application are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0074] According to the semiconductor device manufacturing method provided in the embodiments of this application, a substrate of the first doping type and a columnar doped region of the second doping type are alternately arranged. Under reverse breakdown voltage, the two different doping types of doped regions will deplete each other, achieving charge compensation. The introduction of the superjunction structure allows the device to increase the doping concentration of the drift region under the same breakdown voltage level, thereby reducing the on-resistance of the device. The fin gate design moves part of the source contact area to the bottom of the trench, which can shorten the width of the mesa region, reduce the cell pitch, and reduce the on-resistance. At the same time, it increases the area of ​​the contact region and reduces the contact resistance, providing more pathways for hole release during avalanche and reverse recovery of the body diode, thus optimizing the device's avalanche resistance and reverse recovery characteristics.

[0075] Furthermore, the effective grounding of the shielding region and the superjunction columnar doped region effectively alleviates the electric field at the bottom of the gate dielectric layer, improving the gate oxide reliability of the SiC MOSFET device. The effective shielding effect of the shielding region also reduces the gate drain charge (Qgd), resulting in lower switching losses. When a short circuit occurs, the drain voltage is large, and the JFET region in the shielding region and body region is pinched off, thereby reducing the saturation current of the device, improving its short-circuit capability, and enhancing its robustness.

[0076] Finally, the manufacturing method of this application embodiment has a simple process flow, does not require etching of small-sized trench widths and high-energy ion implantation, which can reduce costs and increase yield.

[0077] This application also provides a semiconductor device that can be prepared by the methods described in the foregoing embodiments, but is not limited thereto.

[0078] Below, for reference Figure 2T The semiconductor devices of this application are described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description is given for the same components and structures as in the foregoing embodiments. For specific explanations and descriptions, please refer to the descriptions in the foregoing embodiments.

[0079] Specifically, the semiconductor device in this application embodiment includes: The substrate 200 has a first doping type, and a first source region 203 of the first doping type and a first body region 202 of the second doping type are formed on the first surface of the substrate 200. At least one trench, formed on the first surface of the substrate 200, penetrates the first body region 202 and the first source region 203 and extends along the second direction; A fin-shaped gate is located on the sidewall of one side of the trench, and a gate dielectric layer 208 is formed between the fin-shaped gate and the substrate 200. An interlayer dielectric layer 210 covers the fin-shaped gate and partially fills the trench; Second source region 205 and second body region 204, the second source region is located at the bottom of the trench and connected to the fin gate, the second body region 205 surrounds the second body region 204 of the second source region 205, the second source region 205 has a first doping type, and the second body region 204 has a second doping type. The shielding region 206 surrounds the bottom of the trench and has a second doping type. The depth of the shielding region 206 is greater than the depth of the second bulk region 205. The source contact layer 214 is in contact with the top of the first source region and the portion of the trench not covered by the interlayer dielectric layer 210.

[0080] For example, the substrate 200 may be a silicon carbide substrate, specifically including a silicon carbide substrate and a silicon carbide epitaxial layer formed on the silicon carbide substrate, both the silicon carbide substrate and the silicon carbide epitaxial layer having a first doping type. In one embodiment, the first doping type is N-type, that is, the substrate 200 is an N-type substrate, and correspondingly, the second doping type is P-type; in other embodiments, the first doping type may also be P-type, and correspondingly, the second doping type is N-type.

[0081] In one embodiment, at least one columnar doped region 201 is further formed in the substrate 200. The columnar doped region 201 has a second doping type and is located below the shielding region. Exemplarily, the columnar doped region 201 is located between adjacent trenches in a horizontally reversed direction. P-type columnar doped regions and N-type epitaxial layers are alternately arranged in the epitaxial layer to form a superjunction structure.

[0082] A first surface of the substrate 200 has a first trench and a second trench extending through the first body region 202 and the first source region 203. The first trench and the second trench are spaced apart from each other along a first direction and extend along a second direction. The first trench includes a first sidewall and a second sidewall, and the second trench includes a third sidewall and a fourth sidewall. The second sidewall and the third sidewall are adjacent to each other. The substrate 200 between the second sidewall and the third sidewall constitutes a mesa region. For example, the aspect ratio of the trench is 0.5-2, and the width of the trench is greater than the width of the mesa region between the second sidewall and the third sidewall.

[0083] A first fin gate 209A is formed on the first sidewall of the first trench, and a third fin gate 209C is formed on the third sidewall of the second trench. A gate dielectric layer 208 is formed between the first fin gate 209A and the third fin gate 209C and the substrate 200.

[0084] An interlayer dielectric layer 210 is covered on the first fin gate 209A and the third fin gate 209C. The interlayer dielectric layer 210 covering the first fin gate 209A and the third fin gate 209C also forms a fin structure with inclined sidewalls similar to the gate.

[0085] A second source region 205 and a second body region 204 are formed below the first fin gate 209A and the third fin gate 209C. The second source region 205 has a first doping type, such as heavily N-type doping, and the second body region 204 has a second doping type, such as lightly P-type doping. A vertical channel is formed in the first body region 202, and a horizontal channel is formed in the second body region 204, thereby increasing the channel density.

[0086] Exemplarily, a second-doped shielding region 206 is also formed in the substrate 200. The shielding region 206 includes a first shielding region surrounding the bottom and second sidewall of the first trench, and a second shielding region surrounding the bottom and fourth sidewall of the second trench. Exemplarily, the shielding region 206 is heavily p-doped.

[0087] The source contact layer 213 contacts the top of the first source region 203 and the portion of the trench not covered by the interlayer dielectric layer 210. Specifically, the source contact layer 213 is formed on the second sidewall of the first trench, the portion of the bottom of the first trench not covered by the interlayer dielectric layer 210, the fourth sidewall of the second trench, and the portion of the bottom of the second trench not covered by the interlayer dielectric layer 210. In one embodiment, such as Figure 2W As shown, the source contact layer 213 located at the bottom of the trench may include alternating ohmic contact layers 213A and Schottky contact layers 213B.

[0088] The semiconductor device provided in this application also has the above-mentioned advantages.

[0089] In another embodiment of this application, an electronic device is provided, including the aforementioned semiconductor device, which can be prepared according to the aforementioned method.

[0090] The electronic device in this embodiment can be any electronic product or equipment, such as a new energy vehicle drive system and charging-related device, a high-performance industrial power supply, or a solar photovoltaic system, or any intermediate product including circuitry. The electronic device in this application embodiment has better performance because it uses the aforementioned semiconductor devices.

[0091] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate having a first doping type, a first surface of the substrate being formed with a first source region of the first doping type and a first body region of a second doping type located below the first source region; at least one trench formed in the first surface of the substrate, the trench extending through the first body region and the first source region and extending in a second direction; a fin-shaped gate located on a sidewall of the trench, a gate dielectric layer being formed between the fin-shaped gate and the substrate; an interlayer dielectric layer covering the fin-shaped gate and filling part of the trench; a second source region located at the bottom of the trench and connected to the fin-shaped gate, and a second body region surrounding the second source region, the second source region having the first doping type and the second body region having the second doping type; a shielding region surrounding at least the bottom of the trench and having the second doping type, the shielding region having a depth greater than that of the second body region; a source contact layer contacting a top of the first source region and a portion of the trench not covered by the interlayer dielectric layer.

2. The semiconductor device of claim 1, wherein, At least one columnar doped region having the second doping type is also formed in the substrate.

3. The semiconductor device of claim 1, wherein, The trench comprises a first trench and a second trench, the first trench and the second trench being spaced apart in the second direction, the first trench comprising a first sidewall and a second sidewall, and the second trench comprising a third sidewall and a fourth sidewall, the second sidewall being adjacent to the third sidewall; The fin-shaped gate comprises a first fin-shaped gate located on the first sidewall of the first trench and a third fin-shaped gate located on the third sidewall of the second trench; The source contact layer contacts the second sidewall of the first trench and a portion of the bottom of the first trench not covered by the interlayer dielectric layer, and contacts the fourth sidewall of the second trench and a portion of the bottom of the second trench not covered by the interlayer dielectric layer.

4. The semiconductor device of claim 3, wherein, The shielding region comprises a first shielding region surrounding at least the bottom of the first trench and the second sidewall, and a second shielding region surrounding at least the bottom of the second trench and the fourth sidewall.

5. The semiconductor device of claim 1, wherein, The source contact layer located at the bottom of the trench comprises alternating ohmic contact layers and Schottky contact layers.

6. A method of manufacturing a semiconductor device, characterized by The manufacturing method comprises: providing a substrate having a first doping type, a first surface of the substrate being formed with a first source region of the first doping type and a first body region of a second doping type located below the first source region; etching the first surface of the substrate to form at least one trench extending through the first body region and the first source region, the trench extending in a second direction; forming a second source region and a second body region surrounding the second source region at the bottom of the trench, the second source region having the first doping type and the second body region having the second doping type; forming a shielding region of the second doping type surrounding at least the bottom of the trench, the shielding region having a depth greater than that of the second body region; forming a gate dielectric layer, a fin-shaped gate and an interlayer dielectric layer on a side wall of the trench in sequence, the fin-shaped gate connecting the second source region; forming a source contact layer, the source contact layer being in contact with the top of the first source region and the part of the trench which is not covered by the interlayer dielectric layer.

7. The production method according to claim 6, wherein Before forming the trench, further comprising: forming at least one columnar doped region in the substrate, the columnar doped region having a second doped type.

8. The production method according to claim 6, wherein the trench comprises a first trench and a second trench which are spaced apart along the first direction, the first trench comprises a first side wall and a second side wall, the second trench comprises a third side wall and a fourth side wall, the second side wall is adjacent to the third side wall; the fin-shaped gate comprises a first fin-shaped gate located on the first side wall of the first trench and a third fin-shaped gate located on the third side wall of the second trench; the forming a gate dielectric layer and a fin-shaped gate on a side wall of the trench in sequence comprises: forming a gate dielectric layer and a gate electrode layer in the first trench and the second trench in sequence; etching the gate electrode layer to form a first fin-shaped gate located on the first side wall of the first trench, a second fin-shaped gate located on the second side wall of the first trench, a third fin-shaped gate located on the third side wall of the second trench and a fourth fin-shaped gate located on the third side wall of the second trench; the interlayer dielectric layer covers the first fin-shaped gate and the third fin-shaped gate; removing the second fin-shaped gate, the fourth fin-shaped gate and the gate dielectric layer under the second fin-shaped gate and the fourth fin-shaped gate which are not covered by the interlayer dielectric layer.

9. The production method according to claim 6, wherein the trench comprises a first trench and a second trench which are spaced apart along the first direction, the first trench comprises a first side wall and a second side wall, the second trench comprises a third side wall and a fourth side wall, the second side wall is adjacent to the third side wall; the forming a shielding region of a second doped type which surrounds the bottom of the trench comprises: before forming the trench, performing ion implantation of a second doped type on the first surface of the substrate to form a first shielding region and a second shielding region; the etching the first surface of the substrate to form at least one trench which penetrates through the first body region and the first source region comprises: etching the first shielding region to form the first trench in the first shielding region and etching the second shielding region to form the second trench in the second shielding region, wherein the first shielding region surrounds the bottom and the second side wall of the first trench, and the second shielding region surrounds the bottom and the fourth side wall of the second trench.

10. The production method according to claim 6, wherein the forming the interlayer dielectric layer which covers the first fin-shaped gate and the third fin-shaped gate comprises: depositing an interlayer dielectric layer which fills the first trench and the second trench and covers the first surface of the substrate; planarizing the interlayer dielectric layer to remove the interlayer dielectric layer which is located above the first surface; forming a patterned photoresist layer that masks the first fin gate, the third fin gate, and the first source region between the second fin gate and the third fin gate, and exposes the second fin gate and the fourth fin gate; dry etching the interlayer dielectric layer to remove the interlayer dielectric layer not covered by the photoresist layer.

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