Method of forming semiconductor device

Abstract

A method of forming a semiconductor device includes forming a self-aligned material (SAM) on a surface of a conductive feature of an interconnect structure, where the interconnect structure is formed on a first side of a device layer including a transistor, where the conductive feature is embedded in an outermost dielectric layer of the interconnect structure remote from the device layer, and a surface of the conductive feature is exposed by the outermost dielectric layer; after forming the SAM, selectively forming a dielectric layer on an outermost dielectric layer of the interconnect structure; after selectively forming the dielectric layer, the SAM is removed from the surface of the conductive feature, where after removing the SAM, the dielectric layer extends further from the device layer than the conductive feature.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum component size, thus allowing more components to be integrated into a given area. However, as the minimum component size decreases, other problems arise that need to be addressed.

[0004] Recently, vertically stacked transistor devices, such as complementary field-effect transistors (CFETs), have offered a promising new architecture, achieving higher integration density through vertically stacked nanostructured field-effect transistors on a substrate. Further research and refinement of various aspects of this new architecture are needed to achieve better device performance. Summary of the Invention

[0005] According to one aspect of the embodiments of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first device layer over a first substrate, wherein the first device layer includes a transistor, wherein the transistor includes a fin protruding over the first substrate, a channel region located above the fin, a gate structure surrounding the channel region, and a source / drain region located above the fin and on the opposite side of the gate structure; forming a first interconnect structure located at a first side of the first device layer and electrically coupled to the transistor, wherein the first interconnect structure includes a first metal pattern embedded in an outermost dielectric layer of the first interconnect structure remote from the first device layer, wherein a first surface of the first metal pattern is exposed by the outermost dielectric layer of the first interconnect structure; forming a first self-aligned material (SAM) on the first surface of the first metal pattern; selectively forming a first dielectric layer on the outermost dielectric layer of the first interconnect structure after forming the first SAM; and removing the first SAM from the first surface of the first metal pattern after selectively forming the first dielectric layer, wherein after removing the first SAM, the first metal pattern is recessed from the surface of the first dielectric layer remote from the first device layer.

[0006] According to another aspect of the embodiments of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first device layer over a first substrate, wherein the first device layer includes a first transistor; forming a first interconnect structure located at a first side of the first device layer and electrically coupled to the first transistor, wherein the first interconnect structure includes a first plurality of dielectric layers and a first plurality of conductive members embedded in the first plurality of dielectric layers, wherein the first conductive members of the first interconnect structure are exposed at a first surface of the outermost dielectric layer of the first interconnect structure away from the first device layer; covering the first conductive members with a self-aligned material (SAM), wherein after covering, the first surface of the outermost dielectric layer of the first interconnect structure is exposed by the SAM; selectively forming a first dielectric layer on the first surface of the outermost dielectric layer of the first interconnect structure after covering; and removing the SAM from the first conductive members after selectively forming the first dielectric layer, wherein after removing the SAM, the first dielectric layer extends further from the first device layer than the first conductive members.

[0007] According to another aspect of the present application, a method for forming a semiconductor device is provided, the method comprising: forming a self-aligned material (SAM) on the surface of a conductive component of an interconnect structure, wherein the interconnect structure is formed on a first side of a device layer including transistors, wherein the conductive component is embedded in an outermost dielectric layer of the interconnect structure away from the device layer, and the surface of the conductive component is exposed by the outermost dielectric layer; selectively forming a dielectric layer on the outermost dielectric layer of the interconnect structure after forming the SAM; and removing the SAM from the surface of the conductive component after selectively forming the dielectric layer, wherein after removing the SAM, the dielectric layer extends further from the device layer than the conductive component. Attached Figure Description

[0008] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 An example of a three-dimensional view of a nanostructured field-effect transistor (NSFET) device according to some embodiments is shown.

[0010] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A, Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B and Figure 15C Various views of a complementary field-effect transistor (CFET) device according to an embodiment are shown at different manufacturing stages.

[0011] Figure 16 , Figure 17A and Figure 17B Cross-sectional views of a CFET device according to another embodiment at different manufacturing stages are shown.

[0012] Figure 18 A flowchart of a method for forming a semiconductor device according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spacer terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacer terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacer descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar components formed using the same or similar materials and by the same or similar forming processes. Furthermore, figures with the same numerals but different letters (e.g., Figures 5A-5C (This shows different views of the same device at the same processing stage.)

[0015] An improved direct bonding between two semiconductor devices is achieved through the disclosed bonding method. The bonding interface of each semiconductor device is formed by the following steps: forming a self-aligned material (SAM) on the surface of a conductive component (e.g., a bonding pad) at the bonding interface of each semiconductor device; selectively forming a dielectric layer on the surface of a dielectric material surrounding the conductive component; and removing the SAM after selectively forming the dielectric layer. In the direct bonding process, the dielectric layers formed in each semiconductor device are first bonded together by direct dielectric-to-dielectric bonding, leaving gaps between the individual conductive components of the semiconductor devices. Next, an annealing process is performed to remove the gaps, causing the individual conductive components of the semiconductor devices to contact each other and form a direct metal-to-metal bond. The disclosed bonding method achieves reliable direct bonding and reduces resistance at the bonding interface, and allows for greater design and wiring flexibility.

[0016] Figure 1 An example three-dimensional view of a nanostructured field-effect transistor (NSFET) device 30 according to some embodiments is shown. The NSFET device 30 includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed above the fin, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed above the fin 90 and between the source / drain regions 112. An isolation region 96 is formed on opposite sides of the fin 90. A gate dielectric layer 120 is formed around the nanostructures 54. The gate electrode 122 is located above and around the gate dielectric layer 120.

[0017] Figure 1Reference sections used in subsequent figures are further illustrated. Section AA is along the longitudinal axis of fin 90 and, for example, along the current direction between the source / drain regions 112 of the NSFET device. Section BB is perpendicular to section AA and along the longitudinal axis of the gate electrode 122. Section CC is parallel to section BB and extends through the source / drain regions 112 of the NSFET device. These reference sections may be referenced in subsequent figures for clarity.

[0018] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B and Figure 15C Various views (e.g., cross-sectional views, top views) of a complementary field-effect transistor (CFET) device 300 according to an embodiment are shown at different manufacturing stages. Specifically, in the embodiment, Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B and Figure 13C Various views (e.g., cross-sectional views, top views) of the NSFET device 100 at different processing stages are shown. The NSFET device 100 is then bonded to another NSFET device 200 to form a CFET device 300, as shown. Figure 14A , Figure 14B , Figure 15A , Figure 15B and Figure 15C The cross-sectional view is shown.

[0019] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 includes: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0020] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. Figure 2 In the diagram, the layers formed by the first semiconductor material 52 are labeled as 52A, 52B and 52C, and the layers formed by the second semiconductor material 54 are labeled as 54A, 54B and 54C. Figure 2 The number of layers formed by the first and second semiconductor materials shown is merely a non-limiting example. Other numbers of layers are also possible and are fully intended to be included within the scope of this disclosure.

[0021] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming the channel region of a p-type FET, such as silicon germanium (Si). x Ge 1-x(where x can be in the range of 0 to 1), the second semiconductor material 54 is an epitaxial material suitable for forming the channel region of an n-type FET, such as silicon. In some embodiments, the second semiconductor material 54 (e.g., silicon) can be used to form an n-type or p-type FET, and the first semiconductor material 52 is used as a sacrificial material to be subsequently removed. The multilayer stack 64 (also referred to as an epitaxial material stack) will be patterned to form the channel region of the NSFET in subsequent processing. For example, the multilayer stack 64 can be patterned and etched to form nanostructures (e.g., nanosheets or nanowires) that comprise the channel region of the resulting NSFET, which includes nanostructures vertically stacked on the fins, with each nanostructure extending parallel to the main upper surface of the substrate.

[0022] The multilayer stack 64 can be formed by an epitaxial growth process that can be performed in a growth chamber. In some embodiments, in the epitaxial growth process, the growth chamber is cyclically exposed to a first set of precursors for selectively growing a first semiconductor material 52, and then exposed to a second set of precursors for selectively growing a second semiconductor material 54. The first set of precursors includes precursors for the first semiconductor material (e.g., silicon-germanium), and the second set of precursors includes precursors for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanane), and the second set of precursors includes a silicon precursor but omits the germanium precursor. Thus, the epitaxial growth process can include continuously flowing silicon precursors into the growth chamber, and then cyclically: (1) flowing germanium precursors into the growth chamber while growing the first semiconductor material 52; and (2) preventing the flow of germanium precursors into the growth chamber while growing the second semiconductor material 54. The cyclic exposure can be repeated until a target number of layers are formed.

[0023] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B and Figure 13CVarious views (e.g., cross-sectional views, top views) of the NSFET device 100 according to an embodiment during subsequent manufacturing stages are shown. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A It is along Figure 1 Cross-sectional view of section AA. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B and Figure 13B It is along Figure 1 Cross-sectional view of section BB in the middle. Figure 5C , Figure 6C and Figure 7C It is along Figure 1 Cross-sectional view of section C. Figure 13C It shows Figure 13A and Figure 13B Top view of the NSFET device 100. The number of fins and gate structures shown are merely non-limiting examples, and it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0024] exist Figure 3A and Figure 3B In the substrate 50, fin structures 91 are formed protruding above the substrate 50. Each fin structure 91 includes a semiconductor fin 90 (also referred to as a fin) and a layer stack 92 covering the semiconductor fin 90. The layer stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The layer stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0025] The fin structure 91 can be patterned using any suitable method. For example, the fin structure 91 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. In an embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are used to pattern, for example, the fin structure 91.

[0026] In some embodiments, the remaining spacers are used to pattern mask 94, which is then used to pattern fin structure 91. Mask 94 can be a single-layer mask or a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be formed of a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to a suitable technique. The first mask layer 94A and the second mask layer 94B are different materials with high etch selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. Mask 94 can be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etch process. Mask 94 can then be used as an etch mask to etch substrate 50 and multilayer stack 64. Etching can be any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. In some embodiments, etching is an anisotropic etching process. Following the etching process, patterned multilayer stack 64 forms layer stack 92, and patterned portions of the substrate 50 form fins 90, such as... Figure 3A and Figure 3B As shown. The unetched lower portion of substrate 50 is in Figure 3A and Figure 3B (And subsequently referred to as substrate 50). Thus, in the illustrated embodiment, the layer stack 92 also includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54, and the fin 90 is formed of the same material as substrate 50 (e.g., silicon).

[0027] Figure 3B The fins 90 and the stacked layers 92 are shown as having substantially vertical sidewalls (e.g., perpendicular to the main upper surface of the substrate 50). Figure 3B The shapes of the fin 90 and the stacked layer 92 shown are merely non-limiting examples. The fin 90 and the stacked layer 92 may have sloping sidewalls (e.g., trapezoidal cross-sections). Sloping sidewalls can be formed due to the characteristics of the anisotropic etching process used to form the fin 90 and the stacked layer 92. For example, the etching capability of the anisotropic etching process may be along... Figure 3B The downward vertical direction of the fin 90 and the stacked parts 92 may tilt.

[0028] Next, in Figure 4A and Figure 4BIn this embodiment, a shallow trench isolation (STI) region 96 is formed above the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material can be formed above the substrate 50. The insulating material can be an oxide (such as silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process can be performed after the formation of the insulating material.

[0029] In some embodiments, an insulating material is formed such that an excess of the insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surface of the substrate 50 and the fin structure 91, and a filler material (such as those discussed above) is formed over the liner. In some embodiments, the liner is omitted.

[0030] Next, a removal process is performed on the insulating material to remove excess insulating material above the fin structure 91. In the illustrated embodiment, the removal process also removes the mask 94. In some embodiments, planarization processes such as chemical mechanical planarization (CMP), etch-back processes, or combinations thereof can be utilized. The planarization process exposes the layer stack 92 such that the top surface of the layer stack 92 and the insulating material are flat after the planarization process. Next, the insulating material is recessed to form STI regions 96. The insulating material is recessed such that the layer stack 92 protrudes between adjacent STI regions 96. The top of the semiconductor fin 90 may also protrude between adjacent STI regions 96. Furthermore, the top surface of the STI region 96 may have the flat surface, convex surface, concave surface (e.g., dish-shaped), or combination thereof shown. The top surface of the STI region 96 may be formed as flat, raised, and / or recessed by appropriate etching. The STI region 96 can be recessed using an acceptable etching process, such as an etching process selective for the insulating material (e.g., etching the insulating material at a faster rate than other materials, such as the materials of fin 90 and the stacked layer 92). For example, chemical oxide removal can be performed using a suitable etchant (e.g., dilute hydrofluoric acid (dHF)).

[0031] Next, in Figures 5A-5C In this process, a pseudo dielectric layer 97 is formed over the stacked layer 92 and the STI region 96. The pseudo dielectric layer 97 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and can be deposited or thermally grown according to acceptable techniques.

[0032] Next, a dummy gate 102 is formed over the fin structure 91. To form the dummy gate 102, a dummy gate layer can be formed over the dummy dielectric layer 97. The dummy gate layer can be deposited over the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be a conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials that have high etch selectivity with the STI region 96.

[0033] A mask 104 is then formed over the dummy gate layer. The mask 104 can be formed of silicon nitride, silicon oxynitride, combinations thereof, etc., and can be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer using an acceptable etching technique to form a dummy gate 102, and then transferred to the dummy dielectric layer using an acceptable etching technique to form a dummy gate dielectric 97. The dummy gate 102 covers the corresponding channel region of the stack 92. The pattern of the mask 104 can be used to physically separate each dummy gate 102 from adjacent dummy gates. The dummy gate 102 may also have a length direction substantially perpendicular to the length direction of the fin structure 91. The dummy gate 102 and the dummy gate dielectric 97 are collectively referred to as the dummy gate structure 101.

[0034] Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stack 92, the STI region 96, and the dummy gate 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, etc. In some embodiments, the gate spacer layer 108 includes a plurality of sublayers. For example, a first sublayer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, and a second sublayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sublayer.

[0035] Figure 5B and Figure 5C They are shown respectively Figure 5A NSFET device 100 edge Figure 5A Cross-sectional views of sections EE and FF. Sections EE and FF correspond to... Figure 1 Sections BB and CC are shown in the diagram. Unless otherwise specified, subsequent figures with the letters A, B, and C (e.g., Figure 6A , Figure 6B and Figure 6C The figures along and Figure 5A , Figure 5B and Figure 5CCross-sectional views of the same section.

[0036] Next, in Figures 6A-6C In this process, the gate spacer layer 108 is etched using an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove the horizontal portion of the gate spacer layer 108 (e.g., the portion above the STI region 96 and the dummy gate structure 101), and the remaining vertical portion of the gate spacer layer 108 (e.g., the portion along the sidewall of the dummy gate structure) forms the gate spacer 108.

[0037] After forming the gate spacer 108, lightly doped source / drain (LDD) regions (not shown) can be implanted. Appropriate types of impurities (e.g., p-type or n-type) can be implanted into the exposed layer stack 92 and / or fins 90. The n-type impurity can be any suitable n-type impurity, such as phosphorus, arsenic, antimony, etc., and the p-type impurity can be any suitable p-type impurity, such as boron, BF2, indium, etc. The lightly doped source / drain regions can have a density of approximately 1E15 / cm². 3 And approximately 1E16 / cm 3 The concentration of impurities can be adjusted. Annealing can be used to activate the injected impurities.

[0038] Next, an opening 110 (which may also be referred to as a recess or source / drain opening) is formed in the layer stack 92. The opening 110 may extend through the layer stack 92 and into the fin 90. The opening 110 may be formed by an anisotropic etching process using, for example, a dummy gate structure 101 and a gate spacer 108 as an etching mask.

[0039] After forming the opening 110, a selective etching process is performed to recess the end of the first semiconductor material 52 exposed by the opening 110, without substantially attacking the second semiconductor material 54. After the selective etching process, a recess (also known as a sidewall recess) is formed at the location of the end that has been removed from the first semiconductor material 52.

[0040] Next, an internal spacer layer is formed in the opening 110 (e.g., conformally) to line the sidewalls and bottom of the opening 110. The internal spacer layer also fills the sidewall recesses of the first semiconductor material 52 formed by a previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon carbonitride oxycarbonyl (SiOCN), etc., and can be formed by a suitable deposition method, such as PVD, CVD, atomic layer deposition (ALD), etc. Next, an etching process, such as anisotropic etching, is performed to remove portions of the internal spacer layer disposed outside the sidewall recesses of the first semiconductor material 52. The remaining portion of the internal spacer layer (e.g., the portion disposed within the sidewall recesses of the first semiconductor material 52) forms the internal spacer 55. Figure 6A As shown, the opening 110 exposes the sidewall of the second semiconductor material 54 and the upper surface 90U of the fin 90 at the bottom of the opening 110.

[0041] exist Figure 6C In the example, a portion of the gate spacer layer 108 on the upper surface of the STI region 96 between adjacent fins 90 is completely removed by an anisotropic etching process used to form the gate spacer 108. The remaining portion of the gate spacer layer 108 along the sidewalls of the fins 90 forms the fin spacer 108F. Figure 6C In this example, as a non-limiting example, the upper surface of the STI region 96 between adjacent fins 90 is shown as a flat surface. The upper surface of the STI region 96 between adjacent fins 90 may be curved (e.g., concave), for example, due to an anisotropic etching process that removes the upper portion of the STI region 96.

[0042] Next, in Figures 7A-7C In the diagram, a source / drain region 112 is formed in the opening 110. In the discussion herein, the term "source / drain region" may refer individually or collectively to either the source or the drain, depending on the context. In the illustrated embodiment, the source / drain region 112 is formed of an epitaxial material and may therefore also be referred to as an epitaxial source / drain region 112. In some embodiments, the epitaxial source / drain region 112 is formed in the opening 110 to apply stress to the respective channel regions of the formed NSFET device, thereby improving performance. In some embodiments, the epitaxial source / drain region 112 is formed such that a dummy gate 102 is disposed between correspondingly adjacent pairs of epitaxial source / drain regions 112. In some embodiments, a gate spacer 108 is used to space the epitaxial source / drain region 112 from the dummy gate 102 by an appropriate lateral distance such that the epitaxial source / drain region 112 does not short-circuit the replacement gate structure of the subsequently formed NSFET device.

[0043] In some embodiments, the epitaxial source / drain region 112 is epitaxially grown in the opening 110. The epitaxial source / drain region 112 may include any acceptable material, such as materials suitable for n-type or p-type devices. For example, when forming an n-type device, the epitaxial source / drain region 112 may include a material that applies tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type device, the epitaxial source / drain region 112 may include a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain region 112 may have a surface protruding from the corresponding surface of the fin 90 and may have facets.

[0044] The epitaxial source / drain regions 112 and / or fins 90 can be implanted with dopants (e.g., n-type or p-type impurities), similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have a density of approximately 1E19 / cm². 3 And about 1E21 / cm 3 The impurity concentration (also referred to as dopant concentration) between these parameters. The n-type and / or p-type impurities used in the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 112 can be doped in situ during the growth process.

[0045] As a result of the epitaxial process used to form the epitaxial source / drain regions 112, the upper surface of the epitaxial source / drain regions 122 has facets that extend laterally outward beyond the fins 90. In the illustrated embodiment, after the epitaxial process is completed, adjacent epitaxial source / drain regions 112 remain separated (see...). Figure 7C In other embodiments, these facets cause adjacent epitaxial source / drain regions 112 to merge together.

[0046] Next, a contact etch stop layer (CESL) 116 is formed over the source / drain region 112 and the dummy gate structure 101 (e.g., conformally), and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and can be formed from silicon nitride using PECVD, although other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, etc., and alternative techniques for forming the CESL 116, such as low-pressure CVD (LPCVD), PVD, etc., can also be used.

[0047] The first ILD 114 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, PECVD, or FCVD. The dielectric material used for the first ILD 114 can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used.

[0048] Next, in Figure 8A and Figure 8B In the middle, remove the dummy gate 102 and the dummy gate dielectric 97. Note that, for simplicity, Figure 5A The cross-sectional view along section FF shown is not presented in the following machining steps because these cross-sectional views are related to... Figure 7C Same or similar, or can be easily obtained from Figure 7C Modifications (e.g., by adding an additional layer formed on the first ILD 114).

[0049] To remove the dummy gate 102, a planarization process such as CMP is performed to make the top surfaces of the first ILD 114 and CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer 108. The planarization process also removes the mask 104 on the dummy gate 102 (see...). Figure 7A The dummy gate 102, gate spacer 108, CESL 116, and first ILD 114 are flush after the planarization process. Therefore, the top surface of the dummy gate 102 is exposed through the first ILD 114.

[0050] Next, the dummy gate 102 is removed in an etching step, thereby forming a recess 103 (also referred to as a gate trench). In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 102 without etching the first ILD 114 or the gate spacer 108. During the removal of the dummy gate 102, the dummy gate dielectric 97 may be used as an etch stop layer while the dummy gate 102 is being etched. The dummy gate dielectric 97 may then be removed after the removal of the dummy gate 102. An etching process, such as an isotropic etching process, may be performed to remove the dummy gate dielectric 97. Figure 8A and Figure 8B As shown, the recess 103 exposes the channel region of the NSFET device 100. The channel region is disposed between adjacent pairs of epitaxial source / drain regions 112.

[0051] Next, the first semiconductor material 52 (e.g., the portion exposed by the recess 103) is removed to release the second semiconductor material 54. After the removal of the first semiconductor material 52, the second semiconductor material 54 (e.g., the portion located below the dummy gate 102 before removal of the dummy gate 102) forms a plurality of nanostructures 54. The nanostructures 54 may be collectively referred to as the channel region 93 or channel layer 93 of the formed NSFET device 100. Figure 8A and Figure 8B As shown, gaps 53 (e.g., voids) are formed between nanostructures 54 by removing the first semiconductor material 52. In some embodiments, the nanostructures 54 are nanosheets or nanowires, depending on, for example, the size (e.g., size and / or aspect ratio) of the nanostructures 54.

[0052] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to the first semiconductor material 52 (e.g., has a higher etching rate), such that the first semiconductor material 52 is removed without substantially damaging the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process is performed using an etching gas and optionally a carrier gas. In some embodiments, the etching gas includes F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, or combinations thereof.

[0053] Next, in Figure 9A and Figure 9B In this process, a gate dielectric material 120 and a gate electrode material 122 are formed in a recess 103 to form an alternative gate structure 123. The gate dielectric material 120 is conformally deposited in the recess 103, for example, on the top surface and sidewalls of the semiconductor fin 90, and on the sidewalls of the gate spacer 108. The gate dielectric material 120 may also be formed on the top surface of the first ILD 114. Notably, the gate dielectric material 120 is formed to encapsulate the nanostructure 54. According to some embodiments, the gate dielectric material 120 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric material 120 is formed of a high-k dielectric material, in which the gate dielectric material 120 may have a dielectric constant (also referred to as a K value) greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof. Methods for forming the gate dielectric material 120 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0054] Next, gate electrode material 122 is deposited over and around gate dielectric material 120, filling the remaining portion of recess 103. Gate electrode material 122 may include a metallic material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode material 122 is shown, gate electrode material 112 may include any number of pad layers (e.g., barrier layers), any number of work function tuning layers, and filler material (e.g., filler metal, conductive material). After forming gate electrode material 122, a planarization process, such as CMP, may be performed to remove excess portions of gate dielectric material 120 and gate electrode material 112 located above the top surface of first ILD 114. Thus, the gate electrode material 122 and the remaining portion of gate dielectric material 120 form the gate electrode 122 and gate dielectric layer 120 of the replacement gate structure 123 of the resulting NSFET device 100, respectively. Each gate electrode 122 and the corresponding gate dielectric layer 120 may be collectively referred to as a gate stack, an alternative gate structure, a metal gate structure, or a gate structure. Each gate structure 123 extends around a corresponding nanostructure 54.

[0055] Next, in Figure 10A and Figure 10B In this process, a gate mask 138 is formed over the replacement gate structure 123. The formation process of the gate mask 138 may include: recessing the replacement gate structure 123; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbonitride; and performing a planarization process to remove excess dielectric material over the first ILD 114. The remaining portion of the dielectric material forms the gate mask 138.

[0056] Next, source / drain contact plugs 119 and gate contact plugs 118 are formed to electrically couple to source / drain region 112 and replacement gate structure 123, respectively. In the illustrated embodiment, source / drain contact plugs 119 and gate contact plugs 118 are formed in a self-aligned manner and fill the space between opposite sidewalls of CESL 116 and the space between opposite sidewalls of gate spacer 108, respectively.

[0057] In some embodiments, one or more anisotropic etching processes are performed to remove portions of the first ILD 114 and CESL 116 disposed above the source / drain regions 112 to form source / source contact openings and expose the source / drain regions 112. Similarly, one or more anisotropic etching processes may be performed to remove the gate mask 138 to form gate contact openings that expose the replacement gate structure 123.

[0058] The source / drain contact plugs 119 and gate contact plugs 118 can be formed by filling the source / drain contact openings and gate contact openings with a conductive material (such as tungsten), but other suitable materials such as aluminum, copper, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys of these materials, combinations thereof, etc., can also be used. Planarization processes, such as CMP, can be performed to remove excess portions of conductive material disposed outside the source / drain contact openings and gate contact openings. As will be readily understood by those skilled in the art, the number and location of the source / drain contact plugs 119 and gate contact plugs 118 shown are illustrative and not limiting.

[0059] In the illustrated embodiment, a silicide region 99 is formed on the source / drain region 112 before the source / drain contact opening is filled to form the source / drain contact plug 119. In some embodiments, the silicide region 99 is formed by depositing a metal (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with a semiconductor material (e.g., silicon, germanium) to form a silicide or germanide region on the source / drain region 112, followed by a thermal annealing process to form the silicide region 99. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although region 99 is referred to as a silicide region, region 99 can also be a germanide region or a silicon germanide region (e.g., a region comprising both silicide and germanide).

[0060] Next, an etch stop layer (ESL) 134 and a second ILD 135 are sequentially formed over, for example, the first ILD 114, the replacement gate structure 123, and the gate spacer 108. In some embodiments, the ESL 134 may include a dielectric material with high etch selectivity for etching the second ILD 135, such as aluminum oxide, aluminum nitride, silicon carbide, etc. The second ILD 135 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0061] Next, a via 131 is formed to extend through the second ILD 135 and ESL 134 and electrically couple to the source / drain contact plug 119 and the gate contact plug 118. The via 131 can be formed by forming a via opening extending through the second ILD 135 and ESL 134 and filling the via opening with a conductive material. The conductive material can be the same as or similar to the conductive material used for the source / drain contact plug 119 or the gate contact plug 118, and therefore details will not be repeated. In some embodiments, a liner layer (e.g., a diffusion barrier layer) can be formed along the sidewalls of the via opening before the conductive material fills the via opening. The liner layer can be titanium, tantalum, titanium nitride, tantalum nitride, etc., and can be formed using any suitable formation method, such as CVD, ALD, etc.

[0062] exist Figure 10A and Figure 10B In the middle, the layer of the NSFET device 100 disposed between the upper part of the fin 90 and the second ILD 135 is collectively referred to as the device layer 142 of the NSFET device.

[0063] Still referencing Figure 10A and Figure 10B Next, a front interconnect structure 130 is formed on device layer 142. The front interconnect structure 130 includes a dielectric layer 136 and conductive components 132 within the dielectric layer 136. The dielectric layer 136 may include suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectric materials, combinations thereof, etc., and can be formed by any suitable formation method, such as CVD, PECVD, ALD, combinations thereof, etc. The conductive components 132 (e.g., conductive elements) may include metal lines and vias, which may be formed using, for example, a damascene process. The conductive components 132 may include a diffusion barrier layer and a metal-containing material (e.g., copper) above the diffusion barrier layer. The diffusion barrier layer (also referred to as a pad layer) may be, for example, TiN, TaN, TiSiN, TiO, Mn-doped Ru, Mn-doped Co, RuCo, etc. The metal-containing material may be, for example, Cu, Co, Ru, Mo, etc. In some embodiments, the topmost conductive component 132 (e.g., the conductive component in the topmost dielectric layer 136T away from device layer 142) may include a conductive component 132P for bonding with another semiconductor device (e.g., a bonding pad or a metal pattern for bonding). Therefore, the conductive component 132P may also be referred to as a bonding component or bonding structure.

[0064] In the illustrated embodiment, the conductive component 132P is exposed at the outermost surface of the front interconnect structure 130, away from the device layer 142. For example, the top surface 132PU of the conductive component 132P is level (e.g., flush) with the upper surface of the topmost dielectric layer 136T of the front interconnect structure 130.

[0065] Next, in Figure 11A and Figure 11B In this embodiment, a self-aligned material (SAM) 137 is formed on the top surface of the conductive component 132P. In the illustrated embodiment, the SAM 137 is selectively formed on the top surface of the conductive component 132P. In other words, the SAM 137 covers the top surface of the conductive component 132P and exposes the upper surface of the topmost dielectric layer 136T of the front interconnect structure 130. In some embodiments, the SAM 137 passivates the top surface of the conductive component 132P such that, in a subsequent process, a dielectric layer 139 is selectively formed on the upper surface of the topmost dielectric layer 136T.

[0066] In some embodiments, SAM 137 is formed by applying an alkylthiol to the top surface of the conductive component 132P. The alkylthiol may be, for example, octadecylthiol (CH3(CH2)17SH) or hexadecylthiol (CH3(CH2)15SH). In some embodiments, SAM 137 is formed by applying a dithiol to the top surface of the conductive component 132P. The dithiol may be, for example, 1,6-hexanedithiol (HS(CH2)6SH). Other suitable materials may be used to form SAM 137 in addition to those listed.

[0067] In some embodiments, to form SAM 137, the top surface of conductive component 132P is immersed in a solution containing a solute (e.g., an alkylthiol or a dithiol) and a solvent (e.g., ethanol) for a predetermined period of time. Alkylthiols and dithiols are organic compounds that can form self-assembled monolayers on metal surfaces. Therefore, SAM 137 is formed (e.g., selectively formed) on the top surface of conductive component 132P. In the illustrated embodiment, SAM 137 is an organic material monolayer that covers (e.g., passivates) the top surface of conductive component 132P and prevents another material (e.g., SiO, SiN) from depositing on the SAM passivated top surface of conductive component 132P. In some embodiments, after forming SAM 137 by the solution deposition process described above, conductive component 132P (or NSFET device 100) can be rinsed with a solvent (e.g., ethanol) and then dried using nitrogen. In addition to solution deposition, SAM 137 can also be formed by vapor deposition, in which the top surface of the conductive component 132P is exposed to dithiol vapor or alkathiol vapor for a predetermined period of time.

[0068] Next, in Figure 12A and Figure 12BIn this embodiment, a dielectric layer 139 is selectively formed on the upper surface of the topmost dielectric layer 136T of the front interconnect structure 130. The dielectric layer 139 can be formed from a suitable dielectric material using appropriate formation methods such as CVD, PECVD, or ALD, for example, silicon oxide, silicon nitride, carbon-doped dielectric materials (e.g., carbon-doped silicon oxide), or high-k dielectric materials. It should be noted that in the illustrated embodiment, since the top surface of the conductive component 132P is passivated by SAM 137, the dielectric layer 139 is selectively formed on the upper surface of the topmost dielectric layer 136T, and not on the SAM-passivated top surface of the conductive component 132P.

[0069] In one embodiment, dielectric layers 139 and 136 of the front interconnect structure 130 are formed of different dielectric materials. For example, dielectric layer 136 may be formed of silicon oxide, while dielectric layer 139 may be formed of silicon nitride, carbon-doped dielectric material, or high-k dielectric material. In other embodiments, dielectric layers 139 and 136 of the front interconnect structure 130 are formed of the same dielectric material.

[0070] Next, in Figure 13A and Figure 13B In this process, SAM 137 is removed from the top surface 132PU of the conductive component 132P using a suitable removal process. For example, UV / ozone treatment can be used to remove SAM 137, in which ultraviolet (UV) light is irradiated onto SAM 137 while ozone gas is applied to SAM 137. The UV light decomposes organic materials (e.g., SAM 137), and the ozone gas oxidizes the organic compounds and reacts with the decomposition products. As another example, oxygen plasma treatment is performed, in which oxygen plasma is supplied to react with SAM 137 to remove SAM 137.

[0071] like Figure 13A and Figure 13B As shown, after removing SAM 137, the top surface 132PU of the conductive component 132P is a flat surface and is recessed from the upper surface 139U of the dielectric layer 139, which is farther from the device layer 142. In other words, the upper surface 139U of the dielectric layer 139 extends further from the device layer 142 than the top surface 132PU of the conductive component 132P. In some embodiments, the upper surface 132PU of the conductive component 132P lies on the same horizontal plane (e.g., a plane parallel to the main upper surface of the substrate 50) and has the same vertical offset as the upper surface 139U of the dielectric layer 139.

[0072] Figure 13C It shows Figure 13A and Figure 13B A top view of the NSFET device 100. Figure 13CThe diagram shows multiple conductive components 132P. These conductive components 132P are used in subsequent processing with another NSFET device 200 (see [link to diagram]). Figure 14A They are joined together to form a CFET device 300. In Figure 13C In the example, multiple conductive components 132P have different dimensions. For example, some conductive components 132P may have a width W1, while other conductive components 132P may have a width W2 that is larger than that width W1. The width W2 may be larger than the width W1 by, for example, 20%, 30%, 40%, 50%, 100%, or even more. The different widths of the conductive components 132P allow for increased freedom in the design and wiring of the NSFET device 100. Figure 13C The number and location of the conductive patterns 132P shown are illustrative and not limiting.

[0073] Next, in Figure 14A and Figure 14B In this configuration, NSFET device 100 is bonded to NSFET device 200 to form CFET device 300. NSFET device 200 is similar to NSFET device 100 and can be formed using the same or similar formation methods. In some embodiments, the source / drain region 124 of NSFET device 200 has a different conductivity type (e.g., N-type or P-type) than the source / drain region 112 of NSFET device 100. For example, the source / drain region 112 of NSFET device 100 may have a first doping type (e.g., doped with a dopant of a first conductivity type, such as N-type), while the source / drain region 124 of NSFET device 200 may have a second doping type (e.g., doped with a dopant of a second conductivity type, such as P-type). In other words, one of NSFET devices 100 and 200 can be formed using an N-type NSFET, and the other of NSFET devices 100 and 200 can be formed using a P-type NSFET. In other embodiments, the source / drain region 112 of NSFET device 100 and the source / drain region 124 of NSFET device 200 have the same doping type (e.g., both are doped with N-type or P-type dopants).

[0074] exist Figure 14A and Figure 14B In the middle, the layers of the NSFET device 200 disposed between the upper part of the fin 90 and the second ILD 135 are collectively referred to as the device layer 142A of the NSFET device 100. Figure 14A and Figure 14B The front interconnect structure 130A of the NSFET device 200 formed above the device layer 142A is further shown.

[0075] exist Figure 14A and Figure 14B In this configuration, the front interconnect structure 130A of the NSFET device 200 is bonded to the front interconnect structure 130 of the NSFET device 100 to form the CFET device 300. This bonding scheme is also known as front-to-front bonding.

[0076] exist Figure 14A and Figure 14B In this configuration, the dielectric layer 139 of NSFET device 100 and the dielectric layer 139 of NSFET device 200 are bonded via dielectric-to-dielectric bonding (also known as direct dielectric-to-dielectric bonding), while the conductive portion 132P of NSFET device 100 is spaced apart from the corresponding conductive portion 132P of NSFET device 200, as shown by the gap 141 (e.g., a void) between the conductive portions 132P of NSFET devices 100 and 200. In other words, the dielectric layer 139 of NSFET devices 100 and 200 is bonded together before the conductive portions 132P of NSFET devices 100 and 200 are bonded together. Figure 13A and Figure 13B As shown, the gap 141 exists because the conductive part 132P of the NSFET device 100 (or 200) is recessed from the upper surface 139U of the dielectric layer 139 of the NSFET device 100 (or 200).

[0077] Next, in Figure 15A and Figure 15B In this process, an annealing process is performed by heating the CFET device 300 to a predetermined temperature and maintaining it for a predetermined time. Because the conductive component 132P (e.g., a metal pattern) has a larger coefficient of thermal expansion (CTE) than the dielectric layer 139, the annealing process increases the thickness of the conductive component 132P by a greater margin than the dielectric layer 139. After the annealing process is completed, the conductive component 132P of the NSFET device 100 contacts the conductive component 132P of the NSFET device 200, and a metal-to-metal bond is formed between the respective conductive components 132P.

[0078] Dielectric-to-dielectric bonding and metal-to-metal bonding (also known as direct metal-to-metal bonding) are bonding techniques available for direct bonding processes that join two semiconductor devices together without the use of an intermediate layer (such as solder). Direct bonding processes use dielectric-to-dielectric bonding and / or metal-to-metal bonding to achieve a robust and reliable connection at the interface of two devices. Metal-to-metal bonding involves aligning and applying sufficient pressure on a metal surface (such as a copper or aluminum surface), often accompanied by heat treatment to promote atomic diffusion and interfacial adhesion, without requiring an intermediate layer (such as solder). Dielectric-to-dielectric bonding uses surfaces such as silicon dioxide or other insulating materials, where, when aligned under appropriate conditions (e.g., at high temperatures and / or under pressure applied to the surface), a bond is formed through forces such as van der Waals forces or covalent interactions. Direct bonding processes help create high-density, low-resistance connections while reducing or minimizing the thermal budget.

[0079] In some embodiments, Figure 14A and Figure 14B In the dielectric-to-dielectric bonding process, NSFET devices 100 and 200 are heated to a first temperature to promote dielectric-to-dielectric bonding. The first temperature is below... Figure 15A and Figure 15B The second temperature of the annealing process performed on the metal-to-metal bonding is insufficient to achieve physical contact between the conductive parts 132P of the NSFET devices 100 and 200 due to the expansion of the conductive parts 132P caused by the lower first temperature, thus forming... Figure 14A and Figure 14B The gap 141 is in the middle. At the higher second temperature of the annealing process, the conductive parts 132P of NSFET devices 100 and 200 contact and form a metal-to-metal bond. In some embodiments, Figure 14A and Figure 14B The dielectric-to-dielectric bonding process in this process is performed by applying pressure at the bonding interface without a heating process.

[0080] exist Figure 15A and Figure 15B In the example, there is no misalignment between the conductive parts 132P of NSFET devices 100 and 200. Figure 15C An example of misalignment between conductive parts 132P of NSFET devices 100 and 200 is shown. Figure 15C cross-sectional view and Figure 15A The corresponding cross-sectional view. For example... Figure 15CAs shown, there is a lateral offset between the corresponding conductive portions 132P of NSFET devices 100 and 200. This lateral offset may be caused by misalignment, for example, introduced during the formation of the conductive portions 132P of NSFET devices 100 and 200. Due to this misalignment, the conductive portion 132P of NSFET device 100 (or 200) is in direct contact not only with the corresponding bonding conductive portion 132P of NSFET device 200 (or 100), but also with the dielectric layer 139. In the embodiments disclosed subsequently (e.g., Figure 17A The CFET device 300A in the diagram does not show misalignment between conductive parts 132P of NSFET devices 100A and 200A, but it is understood that misalignment may exist between conductive parts 132P of NSFET devices 100A and 200A. These and other variations are intended to be included within the scope of this disclosure.

[0081] Additional processing can be performed to complete the fabrication of the CFET device 300. For example, a back-side interconnect structure can be formed on the side of the device layer 142 of the NSFET device 100 opposite to the front-side interconnect structure 130 (see [link to documentation]). Figure 16 (See 151 in the original text). Similarly, a back-side interconnect structure can be formed on the side of device layer 142A of NSFET device 200 opposite to the front-side interconnect structure 130A (e.g., see 151 in the original text). Figure 17A (Referring to 151A in the original text). Before NSFET devices 100 and 200 are bonded together, a back-side interconnect structure can be formed for each NSFET device. More details about the back-side interconnect structure will be discussed below.

[0082] In some embodiments, a plurality of NSFET devices 100 are formed on a first wafer (e.g., substrate 50), and a plurality of NSSET devices 200 are formed on a second wafer (e.g., another substrate 50). After the front-side interconnect structures 130 and 130A are bonded together, a wafer-on-wafer structure including a plurality of CFET devices 300 is formed. Next, along Figure 15A The dicing region shown by the dashed line 150 undergoes a dicing process to separate the wafer-on-wafer structure into single (e.g., individual) CFET devices 300, each CFET device 300 comprising vertically stacked (e.g., bonded together) NSFET devices 100 and 200. In some embodiments, the NSFET devices 100 and 200 in the CFET device 300 have different conductivity types. In other embodiments, the NSFET devices 100 and 200 in the CFET device 300 have the same conductivity type.

[0083] Figure 16 , Figure 17A and Figure 17BCross-sectional views of a CFET device 300A according to another embodiment are shown at different manufacturing stages. Figure 16 A cross-sectional view of NSFET device 100A is shown. NSFET device 100A is bonded to another NSFET device 200A using a front-to-back bonding scheme to form CFET device 300A, as shown. Figure 17A and Figure 17B As shown.

[0084] Figure 16 A cross-sectional view of an NSFET device 100A in one embodiment is shown. The NSFET device 100A is similar to... Figures 13A-13C The NSFET device 100 has a back-side interconnect structure 151 and a dielectric layer 139 on the back-side interconnect structure 151.

[0085] In some embodiments, Figures 13A-13C Following the initial processing, a thinning process is performed from the back side of substrate 50 to thin the substrate. The thinning process can be a polishing process, a CMP process, an etching process, or a combination thereof. The thinning process can remove the substrate 50, the STI region 96, and the lower portion of the fin 90. In some embodiments, the thinning process stops when the source / drain region 112 is exposed. Next, the remaining portion of the fin 90 (e.g., the portion that contacts the gate structure 123) is removed (e.g., by a selective etching process) and replaced with a dielectric layer 143 (e.g., SiO, SiN, or a low-k dielectric material). Figure 16 In this context, the layer of the NSFET device 100 disposed between the second ILD 135 and the lower surface of the source / drain region 112 is collectively referred to as the device layer 142 of the NSFET device 100A.

[0086] Next, a backside interconnect structure 151, including a dielectric layer 136 and conductive components 132, is formed on the backside of device layer 142. The backside interconnect structure 151 may include source / drain contact plugs 119 formed in the dielectric layer 136 that contacts the dielectric layer 143. In the illustrated embodiment, a silicide region 99 is formed at the lower surface of the source / drain region 112 before the source / drain contact plugs 119 are formed. The backside interconnect structure 151 also includes conductive components 132P (e.g., bonding pads) embedded in the outermost dielectric layer 136T remote from device layer 142. Next, in Figures 11A-13C Following the same or similar processing, a SAM 137 is formed on the exposed surface of the conductive component 132P of the back-side interconnect structure 151. Next, a dielectric layer 139 is selectively formed on the outermost dielectric layer 136T of the back-side interconnect structure 151, and then the SAM 137 is removed. Note that the conductive component 132P of the back-side interconnect structure 151 is recessed from the upper surface 139U of the dielectric layer 139 formed on the back-side interconnect structure 151.

[0087] Next, in Figure 17A and Figure 17B In this process, the front-side interconnect structure 130 of the NSFET device 100A is bonded to the back-side interconnect structure 151A of the NSFET device 200A to form the CFET device 300A. This bonding scheme is also referred to as front-side to back-side bonding. The NSFET device 200A is similar to the NSFET device 100A and can be formed using the same or similar formation methods. In some embodiments, the source / drain region 124 of the NSFET device 200A has a different conductivity type (e.g., N-type or P-type) than the source / drain region 112 of the NSFET device 100A. In other embodiments, the source / drain region 112 of the NSFET device 100A and the source / drain region 124 of the NSFET device 200A have the same conductivity type (e.g., both are doped with N-type or P-type dopants). Figure 17A and Figure 17B In the diagram, the device layer, front interconnect structure, and back interconnect structure of the NSFET device 200A are labeled as device layer 142A, front interconnect structure 130A, and back interconnect structure 151A.

[0088] The bonding between NSFET devices 100A and 200A is performed after a bonding process similar to that used to form CFET device 300. For example, the dielectric layer 139 on the front interconnect structure 130 of NSFET device 100A is first bonded to the dielectric layer 139 on the back interconnect structure 151A of NSFET device 200A via dielectric-to-dielectric bonding. After dielectric-to-dielectric bonding, the conductive portion 132P of the front interconnect structure 130 of NSFET device 100A is aligned with the corresponding conductive portion 132P of the back interconnect structure 151A of NSFET device 200A, but a gap exists between the conductive portions 132P of NSFET devices 100A and 200A (e.g., see...). Figure 14A and Figure 14B (141 in the text). Next, an annealing process is performed to remove the gaps, causing the conductive part 132P of the NSFET device 100A to contact the corresponding conductive part 132P of the NSFET device 200A to form a metal-to-metal bond. The details are the same as or similar to those described above, and therefore will not be repeated.

[0089] Figure 17A and Figure 17B The diagram illustrates the formation of a metal-to-metal bond between the corresponding conductive components 132P of the CFET device 300A and NSFET devices 100A and 200A after the annealing process. In some embodiments, the following can be done along... Figure 17AThe dicing region shown by the dashed line 150 is subjected to a dicing process in order to separate the multiple CFET devices 300A formed in the wafer-to-wafer structure into multiple individual (e.g., separate) CFET devices 300.

[0090] The disclosed embodiments achieve advantages. For example, the disclosed embodiments achieve a flat upper surface 132PU for the conductive component 132P (e.g., see...). Figure 13A During the annealing process, each conductive component 132P expands in volume (e.g., in the thickness direction) while still maintaining a flat upper surface 132PU, which allows for reliable metal-to-metal bonding with the corresponding conductive component 132P.

[0091] To understand the advantages of the disclosed embodiments, consider a reference bonding process that does not use SAM137, does not form dielectric layer 139, and bonds NSFET devices 100 and 200 on the outermost surfaces of the interconnect structure. In the reference bonding process, after forming the front-side interconnect structure 130 (or the back-side interconnect structure 151), an etching process (e.g., a wet etching process) is performed to recess the upper surface 132PU of the conductive component 132P. The upper surface 132PU recess is required to accommodate the expansion of the conductive component 132P during the annealing process. However, due to the characteristics of the etching process, the upper surface 132PU of the conductive component 132P is not flat after the etching process. In contrast, the typical upper surface 132PU of the reference bonding method after the etching process is a curved upper surface, such as a concave upper surface. Furthermore, the vertical offset between the middle and edge portions of the resulting concave upper surface 132PU may increase with the size (e.g., width) of the conductive component 132P. Therefore, if the conductive components 132P of the semiconductor device have different widths, the upper surface 132PU obtained after the etching process is a concave upper surface with different depths in the middle. In the annealing process, the concave upper surfaces with different depths result in non-flat bonding surfaces with different heights, which makes it difficult to form a reliable metal-to-metal bond between the conductive components 132P of the two semiconductor devices, and may lead to a large resistance at the metal bonding interface due to poor metal-to-metal bonding.

[0092] In contrast, the disclosed embodiments not only achieve a flat upper surface 132PU of the conductive component 132P, but also exhibit a uniform vertical offset between the upper surface 132PU of the conductive component 132P and the upper surface 139U of the dielectric layer 139, regardless of the size (e.g., width) of the conductive component 132P. These features allow for reliable metal-to-metal bonding, reduced resistance, thereby improving device reliability, increasing production yield, and reducing power consumption. Another advantage of the disclosed embodiments is that the conductive components 132P used for bonding can have different sizes (e.g., widths), which allows for greater flexibility in device design and provides greater wiring freedom.

[0093] Figure 18 A flowchart of a method 1000 for forming a semiconductor device according to some embodiments is shown. It should be understood that... Figure 18 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, deletions, substitutions, rearrangements, or repetitions may be made. Figure 18 The various steps are shown.

[0094] refer to Figure 18 At block 1010, a self-aligned material (SAM) is formed on the surface of a conductive component of an interconnect structure, wherein the interconnect structure is formed on a first side of a device layer including transistors, wherein the conductive component is embedded in the outermost dielectric layer of the interconnect structure away from the device layer, and the surface of the conductive component is exposed by the outermost dielectric layer. At block 1020, after forming the SAM, a dielectric layer is selectively formed on the outermost dielectric layer of the interconnect structure. At block 1030, after selectively forming the dielectric layer, the SAM is removed from the surface of the conductive component, wherein after removing the SAM, the dielectric layer extends further from the device layer than the conductive component.

[0095] In an embodiment, a method of forming a semiconductor device includes: forming a first device layer over a first substrate, wherein the first device layer includes a transistor, wherein the transistor includes a fin protruding over the first substrate, a channel region located above the fin, a gate structure surrounding the channel region, and a source / drain region located above the fin and on the opposite side of the gate structure; forming a first interconnect structure located at a first side of the first device layer and electrically coupled to the transistor, wherein the first interconnect structure includes a first metal pattern embedded in an outermost dielectric layer of the first interconnect structure remote from the first device layer, wherein a first surface of the first metal pattern is exposed by the outermost dielectric layer of the first interconnect structure; forming a first self-aligned material (SAM) on the first surface of the first metal pattern; selectively forming a first dielectric layer on the outermost dielectric layer of the first interconnect structure after forming the first SAM; and removing the first SAM from the first surface of the first metal pattern after selectively forming the first dielectric layer, wherein after removing the first SAM, the first metal pattern is recessed from the surface of the first dielectric layer remote from the first device layer. In an embodiment, forming the first SAM includes applying an alkylthiol to the first surface of the first metal pattern. In one embodiment, the alkylthiol includes octadecylthiol or hexadecylthiol. In an embodiment, forming the first SAM includes applying a dithiol to a first surface of the first metal pattern. In an embodiment, the dithiol includes 1,6-hexanedithiol. In an embodiment, the method further includes: after removing the first SAM, bonding the first dielectric layer to the second dielectric layer, wherein, prior to bonding, the second dielectric layer is pre-formed over the second interconnect structure, wherein, prior to bonding, the second interconnect structure is formed over a second device layer disposed over the second substrate, wherein, during bonding, the second metal pattern embedded in the outermost dielectric layer of the second interconnect structure is aligned with the first metal pattern, wherein, after bonding, a gap exists between the first metal pattern and the second metal pattern. In an embodiment, bonding the first dielectric layer includes bonding the first dielectric layer to the second dielectric layer by dielectric-to-dielectric bonding. In an embodiment, the method further includes: performing an annealing process after bonding, wherein the annealing process removes the gap between the first metal pattern and the second metal pattern, wherein, after performing the annealing process, the first metal pattern is bonded to the second metal pattern. In one embodiment, the first metal pattern is bonded to the second metal pattern by metal-to-metal bonding. In another embodiment, prior to bonding, the second metal pattern is recessed from the surface of the second dielectric layer away from the first device layer. In yet another embodiment, the first device layer is interposed between the first substrate and the first interconnect structure.In one embodiment, a first device layer is formed on a first side of a first substrate, and the first side of the first device layer faces the first substrate. The method further includes performing a thinning process from a second opposite side of the first substrate before forming the first device layer and before forming the first interconnect structure. The thinning process removes the substrate. The first interconnect structure is formed on the first side of the first device layer after the thinning process is performed.

[0096] In an embodiment, a method of forming a semiconductor device includes: forming a first device layer over a first substrate, wherein the first device layer includes a first transistor; forming a first interconnect structure located at a first side of the first device layer and electrically coupled to the first transistor, wherein the first interconnect structure includes a first plurality of dielectric layers and a first plurality of conductive members embedded in the first plurality of dielectric layers, wherein the first conductive members of the first interconnect structure are exposed at a first surface of the outermost dielectric layer of the first interconnect structure away from the first device layer; covering the first conductive members with a self-aligned material (SAM), wherein after covering, the first surface of the outermost dielectric layer of the first interconnect structure is exposed by the SAM; selectively forming a first dielectric layer on the first surface of the outermost dielectric layer of the first interconnect structure after covering; and removing the SAM from the first conductive members after selectively forming the first dielectric layer, wherein after removing the SAM, the first dielectric layer extends further from the first device layer than the first conductive members. In an embodiment, covering the first conductive members includes selectively forming the SAM on the first conductive members using alkylthiols or dithiols. In an embodiment, the method further includes, after removing the SAM, bonding the first dielectric layer to the second dielectric layer by dielectric-to-dielectric bonding, wherein the second dielectric layer is pre-formed on the second interconnect structure prior to bonding, and the second interconnect structure is formed over the second device layer prior to bonding, wherein second conductive components of the second interconnect structure are exposed at a second surface of the second interconnect structure remote from the second device, wherein the second conductive components are aligned with the first conductive components during bonding, and wherein a gap exists between the first conductive components and the second conductive components after bonding. In an embodiment, the method further includes, after bonding, performing an annealing process to bond the first conductive components and the second conductive components by metal-to-metal bonding.

[0097] In an embodiment, a method of forming a semiconductor device includes: forming a self-aligned material (SAM) on the surface of a conductive component of an interconnect structure, wherein the interconnect structure is formed on a first side of a device layer including transistors, wherein the conductive component is embedded in an outermost dielectric layer of the interconnect structure remote from the device layer, and the surface of the conductive component is exposed by the outermost dielectric layer; after forming the SAM, selectively forming a dielectric layer on the outermost dielectric layer of the interconnect structure; and after selectively forming the dielectric layer, removing the SAM from the surface of the conductive component, wherein after removing the SAM, the dielectric layer extends further from the device layer than the conductive component. In an embodiment, before forming the SAM, the surface of the conductive component is flush with the surface of the outermost dielectric layer remote from the device layer. In an embodiment, forming the SAM includes applying an alkylthiol or dithiol to the surface of the conductive component, wherein after forming the SAM, the surface of the outermost dielectric layer is exposed by the SAM. In an embodiment, the dielectric layer and the outermost dielectric layer of the interconnect structure are formed of different materials.

[0098] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A method of forming a semiconductor device, the method comprising: forming a first device layer over a first substrate, wherein the first device layer comprises a transistor, wherein the transistor comprises a fin protruding above the first substrate, a channel region located above the fin, a gate structure surrounding the channel region, and a source / drain region located above the fin and on an opposite side of the gate structure; forming a first interconnect structure located at a first side of the first device layer and electrically coupled to the transistor, wherein the first interconnect structure comprises a first metal pattern embedded in an outermost dielectric layer of the first interconnect structure distal to the first device layer, wherein a first surface of the first metal pattern is exposed by the outermost dielectric layer of the first interconnect structure; forming a first self-aligned material on the first surface of the first metal pattern; after forming the first self-aligned material, selectively forming a first dielectric layer on the outermost dielectric layer of the first interconnect structure; and after selectively forming the first dielectric layer, removing the first self-aligned material from the first surface of the first metal pattern, wherein, after removing the first self-aligned material, the first metal pattern is recessed from a surface of the first dielectric layer distal to the first device layer.

2. The method of claim 1, wherein, forming the first self-aligned material comprises applying an alkanethiol on the first surface of the first metal pattern.

3. The method of claim 1, wherein, forming the first self-aligned material comprises applying a dithiol on the first surface of the first metal pattern.

4. The method of claim 1, further comprising: after removing the first self-aligned material, bonding the first dielectric layer to a second dielectric layer, wherein, prior to the bonding, the second dielectric layer is preformed over a second interconnect structure, wherein, prior to the bonding, the second interconnect structure is formed over a second device layer disposed over a second substrate, wherein, during the bonding, a second metal pattern embedded in an outermost dielectric layer of the second interconnect structure is aligned with the first metal pattern, wherein, after the bonding, a gap exists between the first metal pattern and the second metal pattern.

5. The method of claim 4, wherein, bonding the first dielectric layer comprises bonding the first dielectric layer to the second dielectric layer by dielectric-to-dielectric bonding.

6. The method of claim 5, further comprising: performing an anneal process after the bonding, wherein the anneal process removes the gap between the first metal pattern and the second metal pattern, wherein, after performing the anneal process, the first metal pattern is bonded to the second metal pattern.

7. The method of claim 1, wherein, the first device layer is formed at a first side of the first substrate and the first side of the first device layer faces the first substrate, wherein, prior to forming the first device layer and prior to forming the first interconnect structure, the method further comprises: performing a thinning process from an opposite second side of the first substrate, wherein the thinning process removes the substrate, wherein, after performing the thinning process, the first interconnect structure is formed at the first side of the first device layer.

8. A method of forming a semiconductor device, the method comprising: forming a first device layer over a first substrate, wherein the first device layer includes a first transistor; forming a first interconnect structure at a first side of the first device layer and electrically coupled to the first transistor, wherein the first interconnect structure includes a first plurality of dielectric layers and a first plurality of conductive features embedded in the first plurality of dielectric layers, wherein a first conductive feature of the first interconnect structure is exposed at a first surface of the first interconnect structure distal to an outermost dielectric layer of the first interconnect structure from the first device layer; capping the first conductive feature with a self-aligned material, wherein after capping, the first surface of the outermost dielectric layer of the first interconnect structure is exposed by the self-aligned material; after capping, selectively forming a first dielectric layer on the first surface of the outermost dielectric layer of the first interconnect structure; and after selectively forming the first dielectric layer, removing the self-aligned material from the first conductive feature, wherein after removing the self-aligned material, the first dielectric layer extends further from the first device layer than the first conductive feature.

9. The method of claim 8, further comprising after removing the self-aligned material: bonding the first dielectric layer to a second dielectric layer by dielectric-to-dielectric bonding, wherein the second dielectric layer is pre-formed on a second interconnect structure prior to bonding, and a second interconnect structure is formed over a second device layer prior to bonding, wherein a second conductive feature of the second interconnect structure is exposed at a second surface of the second interconnect structure distal to the second device, wherein during bonding, the second conductive feature is aligned with the first conductive feature, wherein after bonding, a gap exists between the first conductive feature and the second conductive feature.

10. A method of forming a semiconductor device, the method comprising: forming a self-aligned material on a surface of a conductive feature of an interconnect structure, wherein the interconnect structure is formed at a first side of a device layer including a transistor, wherein the conductive feature is embedded in an outermost dielectric layer of the interconnect structure distal to the device layer, and the surface of the conductive feature is exposed by the outermost dielectric layer; after forming the self-aligned material, selectively forming a dielectric layer on the outermost dielectric layer of the interconnect structure; and after selectively forming the dielectric layer, removing the self-aligned material from the surface of the conductive feature, wherein after removing the self-aligned material, the dielectric layer extends further from the device layer than the conductive feature.

Images