Semiconductor structure and forming method thereof

Abstract

The semiconductor structure disclosed by the invention comprises a semiconductor structure, the semiconductor structure includes a backside dielectric layer, a backside etch stop layer (ESL) over the backside dielectric layer, a first source / drain feature and a second source / drain feature over the backside ESL and spaced apart from each other along a first direction, a front side source / drain contact disposed over the first source / drain feature and the second source / drain feature, a backside contact feature through the backside dielectric layer and the backside ESL to couple to the first source / drain feature, a through-via extending through the backside dielectric layer and the backside ESL, a base fin between the backside ESL and the second source / drain feature; and an isolation feature including a portion extending along a sidewall of the base fin. The backside contact feature is in contact with the through-via in the backside dielectric layer, and the isolation feature includes an oxide-based material. The embodiment of the invention also relates to a method for forming the semiconductor structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller, faster electronic devices capable of supporting increasingly complex and sophisticated functions. Consequently, there is a persistent trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down the size of semiconductor ICs (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this scaling also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] As IC devices become smaller, it becomes increasingly challenging to compactly package front-side metal wiring without excessively increasing undesirable parasitic resistance (R) and capacitance (C). Back-side metal wiring has been introduced to alleviate the density problem of metal wiring above the front side of IC devices. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure including: a back-side dielectric layer; a back-side etch stop layer (ESL) located above the back-side dielectric layer; a first source / drain component and a second source / drain component located above the back-side etch stop layer and spaced apart from each other along a first direction; a front-side source / drain contact disposed above the first source / drain component and the second source / drain component; a back-side contact component extending through the back-side dielectric layer and the back-side etch stop layer to couple to the first source / drain component; a via extending through the back-side dielectric layer and the back-side etch stop layer to couple to the front-side source / drain contact component; a base fin located between the back-side etch stop layer and the second source / drain component; and an isolation component including a portion extending along the sidewall of the base fin, wherein the back-side contact component is in contact with the via in the back-side dielectric layer, and wherein the isolation component comprises an oxide-based material.

[0005] Another embodiment of this disclosure provides a semiconductor structure, including: a back-side dielectric layer; a back-side etch stop layer (ESL) located above the back-side dielectric layer; a first gate structure located above the back-side etch stop layer; a second gate structure located above the back-side etch stop layer and aligned with the first gate structure along a first direction; a third gate structure located above the back-side etch stop layer; a fourth gate structure located above the back-side etch stop layer and aligned with the third gate structure along the first direction; a first source / drain component located above the back-side etch stop layer and disposed between the first gate structure and the third gate structure along a second direction perpendicular to the first direction; and a second source / drain component located above the back-side etch stop layer and disposed between the first gate structure and the third gate structure along a second direction perpendicular to the first direction. The following components are disposed above the etch stop layer and along the second direction between the second gate structure and the fourth gate structure: a front source / drain contact disposed above the first source / drain component and the second source / drain component; a back contact extending through the back dielectric layer and the back etch stop layer to couple to the first source / drain component; and a via extending through the back dielectric layer and the back etch stop layer to couple to the front source / drain contact, wherein the back contact is connected to the via in the back dielectric layer, wherein the first gate structure includes a gate dielectric layer and a gate electrode layer located above the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation component.

[0006] Another embodiment of this disclosure provides a method for forming a semiconductor structure, comprising: providing a precursor structure, the precursor structure including: a first source / drain component and a second source / drain component located above a front source / drain contact; a first base fin located above the first source / drain component; a second base fin located above the second source / drain component; an isolation component disposed between the first base fin and the second base fin and extending along the sidewalls of the first base fin and the second base fin; and a gate isolation component disposed between the first base fin and the second base fin, a portion of the gate isolation component extending into the isolation component; the method The method further includes: depositing a back-side etch stop layer (ESL) over the first base fin, the second base fin, the isolation member, and the gate isolation member; depositing a back-side dielectric layer over the back-side etch stop layer; forming a via opening through the back-side dielectric layer, the back-side etch stop layer, and the gate isolation member to expose the front-side source / drain contacts; forming a via in the via opening; forming a back-side opening through the first base fin to expose the first source / drain member, such that a portion of the via is exposed in the back-side opening; and forming a back-side contact member in the back-side opening, such that the back-side contact member is in contact with the via. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be emphasized that, in accordance with standard industry practice, the individual components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0008] Figure 1 A flowchart of a method 100A for forming a back-side contact member and a through hole according to one or more aspects of this disclosure.

[0009] Figures 2 to 8 This demonstrates the experience under various aspects of this disclosure. Figure 1 Partial cross-sectional views of the precursor structure for each step of method 100A.

[0010] Figure 9 The various aspects of this disclosure are shown. Figure 8 A schematic top view of the precursor structure.

[0011] Figure 10 A flowchart of a method 100B for forming a back-side contact member and a through hole, according to one or more aspects of this disclosure.

[0012] Figures 11 to 13 This demonstrates the experience under various aspects of this disclosure. Figure 10 Partial cross-sectional views of the precursor structure for each step of method 100B.

[0013] Figure 14 The various aspects of this disclosure are shown. Figure 13 A schematic top view of the precursor structure.

[0014] Figure 15 A partial cross-sectional view of a semiconductor structure according to various aspects of the present disclosure is shown, the semiconductor structure including through holes located on both sides of a back-side contact.

[0015] Figure 16 The various aspects of this disclosure are shown. Figure 15 A schematic top view of the semiconductor structure. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or component to another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] Additionally, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with that value, the value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer with a thickness of "about 5 nm" can encompass a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. When describing aspects of a transistor, depending on the context, the source / drain region may refer individually or collectively to the source or drain.

[0019] As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. Fin field-effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, and they have become popular and promising candidates for high-performance and low-leakage applications. A FinFET has a raised channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of a “fin” of semiconductor material extending from the substrate). A GAA transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor can also be called a gate-around transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also provides alternative names for GAA transistors, such as nanosheet transistors or nanowire transistors. As the semiconductor industry further advances to sub-10 nanometer (nm) technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to stacked device structure configurations, such as complementary field-effect transistors (CFETs), in which n-type multi-gate transistors and p-type multi-gate transistors are stacked vertically on top of each other.

[0020] Smaller device sizes and stacking configurations have placed significant pressure on front-side-only circuitry, prompting the development of device structures with routing structures both above and below the device structure. For example, back-side power rails (BPRs) or super-power rails (SPRs) have been proposed, where back-side source / drain contacts are formed through the substrate to contact source / drain components, and power rails are formed on the back side of the substrate to contact the back-side source / drain contacts. The industry continues to seek methods to reduce the resistance in routing structures, including the resistance between front-side and back-side routing structures.

[0021] This disclosure provides a method for forming a back-side contact component and a through-hole adjacent to the back-side contact component. The through-hole extends between source / drain components to connect to a front-side source / drain contact. This connection provides a low-resistance conductive path between the back-side contact component and the front-side source / drain contact. In the method of this disclosure, openings for the through-hole and openings for the back-side contact component are formed separately. Metal fillers for the through-hole and the back-side contact component can be deposited separately or simultaneously.

[0022] Figure 1 and Figure 10This is a flowchart illustrating methods 100A and 100B for forming a back-side contact member and a through hole adjacent to the back-side contact member. Methods 100A and 100B are merely examples and are not intended to limit this disclosure to what is explicitly shown in methods 100A and 100B. Additional steps may be provided before, during, and after methods 100A or 100B, and for additional embodiments of the methods, some of the described steps may be replaced, eliminated, or rearranged. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 8 Description method 100A, Figures 2 to 8 These are partial cross-sectional views of the precursor structure 200 at different manufacturing stages according to various embodiments of method 100A. The following is in conjunction with... Figures 2 to 4 and Figures 11 to 13 Description method 100B, Figures 2 to 4 and Figures 11 to 13 This is a partial cross-sectional view of the precursor structure 200 at different manufacturing stages according to various embodiments of method 100B. Since the precursor structure 100 will be manufactured as a semiconductor structure, the precursor structure 400 may be referred to herein as semiconductor structure 200, depending on the context. For the avoidance of doubt, the X, Y, and Z directions in the figures of this disclosure are perpendicular to each other. In this disclosure, unless otherwise explicitly stated, the same reference numerals denote the same parts.

[0023] refer to Figure 1 , Figure 2 and Figure 3 Method 100A includes block 102, in which a precursor structure 200 is formed. For example... Figure 2 and Figure 3 As shown, the precursor structure 200 includes a front-end process (FEOL) structure, a middle-end process (MEOL) structure, and a front-side back-end process (BEOL) structure formed over a substrate 201 (shown by dashed lines). In one embodiment, the substrate 201 may include silicon (Si). Optionally or additionally, the substrate 201 may include another elemental semiconductor, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Optionally, the substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0024] At frame 102, an epitaxial stack with alternating semiconductor layers is formed over substrate 201. In some cases, the epitaxial stack may include multiple first semiconductor layers interleaved with multiple second semiconductor layers. The first semiconductor layers may include silicon (Si), and the second semiconductor layers may include silicon germanium (SiGe). Figure 3 As shown, the precursor structure 200 includes a channel member 2080 released from the first semiconductor layer when a second semiconductor layer in the channel region is selectively removed. This forms a gate structure (such as...). Figure 3 The first gate structure 268 and the second gate structure 270 shown enclose each channel member 2080. The gate structure includes a gate dielectric layer 282 and a gate electrode 284 located above the gate dielectric layer 282. The gate dielectric layer 282 includes a high-k dielectric material, such as hafnium oxide (HfO), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), or hafnium lanthanum oxide (HfLaO). In one embodiment, the gate dielectric layer 282 includes hafnium oxide. The gate electrode 284 may include a multilayer structure, such as various combinations of metal layers (work function metal layers) having selective work functions to enhance device performance, padding layers, wetting layers, adhesive layers, metal alloys, or metal silicides. For example, the gate electrode 284 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials or combinations thereof.

[0025] In an embodiment where the depicted transistor is a GAA transistor, portions of the epitaxial stack and substrate 201 are patterned to form fin-shaped active regions. Each fin-shaped active region may include a base fin 202B formed by the substrate 201 and a top portion formed by the epitaxial stack. An isolation member 204 is deposited over the substrate 201, and portions of the isolation member 204 extend along the sidewalls of the base fin 202B. The isolation member 204 may include an oxide-based material, such as silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), or a low-k dielectric material. The isolation member 204 has a much smaller dielectric constant than the gate dielectric layer 282. In some cases, the dielectric constant of the gate dielectric layer 282 is at least three times that of the isolation member 204. A gate spacer 210 is formed along the sidewalls of a dummy gate stack, which is later replaced by a gate structure. Figure 2 As shown, Figure 2This is a cross-sectional view spanning the first source / drain component 226 and the second source / drain component 227, with a portion of the gate spacer 210 disposed above the isolation component 204. Still referring to... Figure 2 A buffer epitaxial layer 222 is disposed above the top surface of the substrate fin 202B, and a bottom nitride layer 224 is disposed above the buffer epitaxial layer 222. In some embodiments, the buffer epitaxial layer 222 comprises undoped silicon, undoped germanium, or undoped silicon-germanium, and serves to prevent leakage into the substrate 201. The bottom nitride layer 224 comprises silicon nitride and serves to control the growth and stress of the first source / drain component 226 and the second source / drain component 227. A portion of the gate spacer 210 is disposed along the sidewalls of the buffer epitaxial layer 222 and the bottom nitride layer 224. In some embodiments, the gate spacer 210 may comprise a nitride-based material, such as silicon nitride, silicon carbonitride, or silicon carbonitride oxide.

[0026] The first source / drain component 226 and the second source / drain component 227 can be obtained from the channel component 2080 (e.g. Figure 3 Epitaxial growth of the exposed endwalls (shown). In some embodiments, the first source / drain component 226 and the second source / drain component 227 may comprise silicon germanium (SiGe) doped with a p-type dopant (such as boron (B)). In some alternative embodiments, the first source / drain component 226 and the second source / drain component 227 may comprise silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). After forming the first source / drain component 226 and the second source / drain component 227, a contact etch stop layer (CESL) 206 is deposited over the isolation component 204, the gate spacer 210, the first source / drain component 226, and the second source / drain component 227. A first interlayer dielectric (ILD) layer 208 is then formed over the CESL 206. Following the planarization step, a first etch stop layer (ESL) 212 is formed over the planar top surface of the first ILD layer 208, and a second ILD layer 214 is formed over the first ESL 212. Because the first ILD layer 208 needs to accommodate the height of the source / drain components, it is thicker along the Z-direction than the second ILD layer 214. The first ILD layer 208 and the second ILD layer 214 may comprise oxide-based materials, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (BSG). CESL 206 and the first ESL 212 may comprise nitride-based materials, such as silicon nitride or aluminum nitride.

[0027] The precursor structure 200 includes a front contact 230 extending through the second ILD layer 214, the first ESL 212, and the first ILD layer 208 to be electrically coupled to the first source / drain component 226 and the second source / drain component 227 via a silicide component 228. The front contact 230 includes a lower portion disposed between the first source / drain component 226 and the second source / drain component 227, and an upper portion spanning the first source / drain component 226 and the second source / drain component 227. The front contact 230 may include cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), or combinations thereof. The front contact 230 is spaced apart from the first ILD layer 208, the first ESL 212, and the second ILD layer 214 by a barrier layer. The barrier layer may include titanium nitride or tantalum nitride. The silicide component 228 may include titanium silicide or cobalt silicide.

[0028] like Figure 3 As shown, a gate isolation component 220 is formed to separate the first gate structure 268 and the second gate structure 270. Figure 2 and Figure 3 As shown, the gate isolation member 220 also extends along the X direction between the base fins 202B and insulates the first gate structure 268 from the second gate structure 270. A portion of the gate isolation member 220 extends into the isolation member 204. Although not explicitly shown in the figures, the gate isolation member 220 may include a pad for contact with the gate structure and a low-k filler spaced apart from the gate structure by the pad. In some embodiments, the pad may include an oxygen-free dielectric material, such as silicon nitride, and the low-k filler may include an oxide-based material.

[0029] Still referencing Figure 2The precursor structure 200 represents a structure in which a front-side interconnect structure has been formed above the front side 200F of the precursor structure 200. For example, the precursor structure 200 includes a first inter-metal dielectric (IMD) layer 232, a second IMD layer 234, a third IMD layer 238, a second ESL 242, and a fourth IMD layer 244 located above the second ILD layer 214. In some embodiments, the second ESL 242 may have a composition similar to the first ESL 212. The first IMD layer 232, the second IMD layer 234, the third IMD layer 238, and the fourth IMD layer 244 may include oxide-based materials, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (BSG). A first front-side metal line 236 is disposed in the first IMD layer 232. A first front-side contact via 240 is disposed in a third IMD layer 238. Contact components 246 are disposed in a second ESL 242 and a fourth IMD layer 244. The first front-side metal line 236, the first front-side contact via 240, and the contact components 246 may comprise titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), or combinations thereof. Metal nitrides are components of the barrier layer used for these conductive components.

[0030] After forming the front-side interconnect structure, the precursor structure 200 is flipped and the substrate 201 is thinned. A combination of polishing and planarization processes is then performed to thin the substrate 201 to expose the isolation component 204 and the base fin 202B. In some embodiments, the thinning also exposes the gate isolation component 220 and the first ILD layer 208.

[0031] refer to Figure 1 and Figure 4 Method 100A includes block 104, wherein a back-side etch stop layer (ESL) 247 and a back-side dielectric layer 248 are deposited above the back-side surface of the precursor structure 200. In some embodiments, the back-side ESL 247 may comprise silicon nitride, silicon carbonitride, aluminum nitride, or aluminum oxide, and may be deposited using chemical vapor deposition (CVD). In one embodiment, the back-side ESL 247 comprises silicon nitride. The back-side dielectric layer 248 may be deposited using CVD, flowable CVD (FCVD), or spin coating, and may comprise an oxide-based dielectric material, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (BSG). In one embodiment, the back-side dielectric layer 248 comprises silicon oxide.

[0032] refer to Figure 1 and Figure 5 Method 100A includes a frame 106, wherein a through-hole opening 250 is formed through the back-side ESL 247 and the back-side dielectric layer 248. For example... Figure 5 As shown, the via opening 250 is designed to penetrate the back-side dielectric layer 248, the back-side ESL 247, the gate isolation member 220, and the first ILD layer 208 to expose the lower portion of the front-side contact 230. As described above, the low-k filler layers in the back-side dielectric layer 248 and the gate isolation member 220 are formed of oxide-based dielectric materials, and the pads of the back-side ESL 247 and the gate isolation member 200 are formed of nitride-based materials. Because the back-side ESL 247 and the pads are thinner than the back-side dielectric layer 248 and the low-k filler, the formation of the via opening 250 primarily involves etching the oxide-based material. Photolithography and etching processes can be used to form the via opening 250. In the example process, a patterned mask is formed over the back-side dielectric layer 248. Figure 5 (Not explicitly shown), and then a first etching process 300 is performed using a patterned mask as an etching mask to etch the precursor structure 200. The first etching process 300 is configured to etch silicon oxide faster than etching silicon or silicon nitride. In some embodiments, the first etching process 300 may include a dry etching process using a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), or sulfur hexafluoride (SF6)), a chlorine-containing gas (e.g., chlorine (Cl2)), oxygen (O2), or hydrogen (H2). Because the via opening 250 has a larger size and does not need to be aligned with the source / drain components, the photolithography process required to form the via opening 250 may include immersion lithography, which employs a deep ultraviolet (DUV) radiation source with wavelengths between about 100 nm and about 300 nm (such as 193 nm). In other words, the photolithography process used to form the through-hole opening 250 does not require the use of extreme ultraviolet (EUV) lithography.

[0033] refer to Figure 1 and Figure 6 Method 100A includes a frame 108, wherein a through-hole 252 is formed in a through-hole opening 250. In some embodiments, the through-hole 252 may include cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), copper (Cu), or a combination thereof. In some embodiments, the through-hole 252 may be formed by depositing the aforementioned metal to fill the through-hole opening 250 by physical vapor deposition (PVD), metal-organic CVD (MOCVD), electroplating, or electroless plating. After depositing the metal filler, a planarization process (such as chemical mechanical polishing (CMP)) is performed to remove excess metal above the back-side dielectric layer 248 to form the through-hole 252.

[0034] refer to Figure 1 and Figure 7 Method 100A includes a frame 110, wherein a back-side contact opening 254 is formed adjacent to the through hole 252. For example... Figure 7 As shown, the back-side contact opening 254 exposes the first source / drain component 226 and is designed to penetrate the back-side dielectric layer 248, the back-side ESL 247, the base fin 202B, the buffer epitaxial layer 222, and the bottom nitride layer 224 to expose the bottom surface of the first source / drain component 226. As described above, the base fin 202B and the buffer epitaxial layer 222 are formed of a semiconductor material, such as silicon or germanium. As a result, the formation of the back-side contact opening 254 primarily involves etching the semiconductor material. Photolithography and etching processes can be used to form the back-side contact opening 254. In the example process, a patterned mask is formed over the back-side dielectric layer 248. Figure 7 (Not explicitly shown), and then a second etching process 400 is performed using a patterned mask as an etching mask to etch the precursor structure 200. The second etching process 400 is configured to etch silicon faster than etching silicon oxide or silicon nitride. It should be noted that the openings in the patterned mask partially overlap with the through-hole 252 to ensure that the back-side contact 260 to be formed is adjacent to and physically connected to the through-hole 252. In some embodiments, the second etching process 400 may include a dry etching process using a fluorinated gas (e.g., carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), or sulfur hexafluoride (SF6)), oxygen (O2), or hydrogen (H2). Because the back contact opening 254 has a small size and needs to be satisfactorily aligned with the first source / drain component 226, the photolithography process required to form the back contact opening 254 may include extreme ultraviolet (EUV) lithography, which employs a radiation source with wavelengths between about 10 nm and about 100 nm (such as about 13.5 nm). Because the lower portion of the front contact 230 extends below the bottom surface of the first source / drain component 226, the back contact opening 254 extends to a level below the bottom surface of the through-hole 252.

[0035] refer to Figure 1 and Figure 8 Method 100A includes a frame 112, wherein a back-side contact 260 is formed in a back-side contact opening 254 such that the back-side contact 260 abuts a through-hole 252. In some embodiments, the back-side contact 260 may include cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), copper (Cu), or combinations thereof. In some embodiments, the back-side contact 260 may be formed by depositing the aforementioned metals to fill the back-side contact opening 254 via PVD, MOCVD, electroplating, or electroless plating. After depositing the metal filler, a planarization process (such as chemical mechanical polishing (CMP)) is performed to remove excess metal above the back-side dielectric layer 248 to form the back-side contact 260. Figure 8 As shown, due to the planarization process, the top surfaces (inverted for the precursor structure 200) of the back dielectric layer 248, the back contact 260, and the through hole 252 are coplanar.

[0036] Figure 9 It shows Figure 8 The dorsal side 200B of the precursor structure 200 in the middle (e.g. Figure 8 A schematic top view (as shown). Figure 9 As shown, Figure 8 Indicates crossing Figure 9 A partial cross-section of line AA in the diagram. (Reference) Figure 9 The base fin 202B extends longitudinally along the Y direction and is parallel to each other. A first gate structure 268 and a second gate structure 270 extend longitudinally along the X direction. A third gate structure 272 and a fourth gate structure 274 also extend longitudinally along the X direction. A gate isolation member 220 extends longitudinally along the Y direction between the first gate structure 268 and the second gate structure 270, and between the third gate structure 272 and the fourth gate structure 274. The gate isolation member 220 isolates the first gate structure 268 from the second gate structure 270, such that the first gate structure 268 and the second gate structure 270 are aligned longitudinally along the X direction. Similarly, the gate isolation member 220 isolates the third gate structure 272 from the fourth gate structure 274, such that the third gate structure 272 and the fourth gate structure 274 are aligned longitudinally along the X direction. Each of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274 encloses each channel member 2080 disposed above the base fin 202B (e.g., Figure 3 (As shown). Gate spacers 210 are disposed along the sidewalls of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274. Figure 9 As shown, the gate isolation member 220 is in contact with the sidewall of the gate spacer 210 along the sidewalls of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274. In some embodiments, the first etching process 300 for forming the through-hole opening 250 etches the gate spacer 210 at a slower rate, such that the gate spacer 210 defines the boundary of the through-hole 252 along the Y direction. Figure 9 In some embodiments shown, the through-hole 252 is adjacent to and connected to the gate spacer 210. Still referring to... Figure 9 Each of the first source / drain component 226 and the second source / drain component 227 is disposed above the base fin 202B. With the back side 200B facing upwards, the front contact 230 is disposed below the first source / drain component 226 and the second source / drain component 227 to allow passage through the silicide component 228 ( Figure 9(Not shown) Coupled to the first source / drain component 226 and the second source / drain component 227.

[0037] In the depicted embodiment, the through-hole 252 includes a first width W1 along the X direction and a first length L1 along the Y direction. The first width W1 is different from the first length L1. In some embodiments, the first length L1 is greater than the first width W1. In one embodiment, the ratio of the first length L1 to the first width W1 is between about 1.5 and about 2.5. In some cases, the first length L1 is between about 24 nm and about 72 nm, and the first width W1 is between about 12 nm and about 36 nm. The back contact 260 includes a second width W2 along the X direction and a second length L2 along the Y direction. The second width W2 is different from the second length L2. In some embodiments, the second width W2 is greater than the second length L2 because the width of the back contact 260 is intentionally increased to overlap and connect with the through-hole 252. In one embodiment, the ratio of the second width W2 to the second length is between about 1.1 and about 1.5. Due to the different forming methods, the through-hole 252 has a larger occupied area than the back contact 260. That is, the first length L1 is greater than the second length L2, and the first width W1 is greater than the second width W2.

[0038] In method 100A described above, openings for the back-side contact 260 and the through hole 252 are formed separately, and the back-side contact 260 and the through hole 252 are formed separately in the respective openings. In method 100B, openings for the back-side contact 260 and the through hole 252 are formed separately, but the back-side contact 260 and the through hole 252 are formed simultaneously.

[0039] refer to Figure 10 , Figure 2 and Figure 3 Method 100B includes box 102, in which a precursor structure 200 is formed. The operation at box 102 has been described in detail above in conjunction with method 100A. For the sake of brevity, a detailed description of box 102 is omitted here.

[0040] refer to Figure 10 and Figure 4 Method 100B includes block 104, in which a back-side etch stop layer (ESL) 247 and a back-side dielectric layer 248 are deposited above the back-side surface of the precursor structure 200. The operation at block 104 has been described in detail above in conjunction with method 100A. For the sake of brevity, a detailed description of block 104 is omitted here.

[0041] refer to Figure 10 and Figure 11 Method 100B includes a frame 106, wherein a through-hole opening 250 is formed through the back-side ESL 247 and the back-side dielectric layer 248. (As...) Figure 11 As shown, the via opening 250 is designed to penetrate the back-side dielectric layer 248, the back-side ESL 247, the gate isolation member 220, and the first ILD layer 208 to expose the lower portion of the front-side contact 230. As described above, the low-k filler layers in the back-side dielectric layer 248 and the gate isolation member 220 are formed of oxide-based dielectric materials, and the pads of the back-side ESL 247 and the gate isolation member 200 are formed of nitride-based materials. Because the back-side ESL 247 and the pads are thinner than the back-side dielectric layer 248 and the low-k filler, the formation of the via opening 250 primarily involves etching the oxide-based material. Photolithography and etching processes can be used to form the via opening 250. In the example process, a patterned mask is formed over the back-side dielectric layer 248. Figure 11 (Not explicitly shown), and then a patterned mask is used as an etching mask to perform a first etching process 300 to etch the precursor structure 200. In some embodiments, the first etching process 300 may include a dry etching process using a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), or sulfur hexafluoride (SF6)), a chlorine-containing gas (e.g., chlorine (Cl2)), oxygen (O2), or hydrogen (H2). Because the via opening 250 has a larger size and does not need to be aligned with the source / drain components, the photolithography process required to form the via opening 250 may include immersion lithography, which uses a deep ultraviolet (DUV) radiation source with wavelengths between about 100 nm and about 300 nm (such as 193 nm). That is, the photolithography process used to form the via opening 250 may not involve the use of extreme ultraviolet (EUV) lithography.

[0042] refer to Figure 10 and Figure 12 Method 100B includes a frame 109 in which a back-side contact opening 254 is formed in conjunction with a via opening 250. The back-side contact opening 254 exposes a first source / drain component 226 and is designed to penetrate a back-side dielectric layer 248, a back-side ESL 247, a base fin 202B, a buffer epitaxial layer 222, and a bottom nitride layer 224 to expose the bottom surface of the first source / drain component 226. The base fin 202B and the buffer epitaxial layer 222 are formed of a semiconductor material such as silicon or germanium. As a result, the formation of the back-side contact opening 254 primarily involves etching the semiconductor material. Photolithography and etching processes can be used to form the back-side contact opening 254. Because the back-side contact opening 254 is formed without any metal filler in the via opening 250, a bottom anti-reflective coating (BARC) layer can be deposited to temporarily fill the via opening 250. A patterned mask is then formed over the back-side dielectric layer 248. Figure 12(Not explicitly shown), and then a second etching process 400 is performed using a patterned mask as an etching mask to etch the precursor structure 200. It should be noted that the openings in the patterned mask partially overlap with the through-hole opening 250 to ensure fluid communication between the back-side contact opening 254 and the through-hole opening 250. In some embodiments, the dielectric separation structure between the through-hole opening 250 and the back-side contact opening 254 is below the top surface of the back-side dielectric layer 248. For ease of reference, Figure 12 The merged back-side contact opening 254 and through-hole opening 250 shown may be referred to as merged opening 258. In some embodiments, the second etching process 400 may include a dry etching process using a fluorinated gas (e.g., carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), or sulfur hexafluoride (SF6)), oxygen (O2), or hydrogen (H2). Because the back-side contact opening 254 has a small size and needs to be satisfactorily aligned with the first source / drain component 226, the photolithography process required to form the back-side contact opening 254 may include extreme ultraviolet (EUV) lithography, which employs a radiation source with wavelengths between about 10 nm and about 100 nm (such as about 13.5 nm). Because the lower portion of the front contact 230 extends below the bottom surface of the first source / drain component 226, the back-side contact opening 254 extends to a level below the bottom surface of the through-hole 252.

[0043] refer to Figure 10 and Figure 13 Method 100B includes block 111, wherein a merged conductive component 266 is formed in a merged opening 258. In some embodiments, the merged conductive component 266 may include cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), copper (Cu), or combinations thereof. In some embodiments, the aforementioned metal may be deposited by PVD, MOCVD, electroplating, or electroless plating to fill the merged opening 258 to form the back-side contact 260. After depositing the metal filler, a planarization process (such as chemical mechanical polishing (CMP)) is performed to remove excess metal above the back-side dielectric layer 248 to form the merged conductive component 266. Figure 13 As shown, due to the planarization process, the top surfaces (inverted form of the precursor structure 200) of the back-side dielectric layer 248 and the merged conductive component 266 are coplanar. Since the merged opening 258 includes a back-side contact opening 254 and a through-hole opening 250, the merged conductive component 266 includes a through-hole leg 256 located in the through-hole opening 25 and a back-side contact leg 264 located in the back-side contact opening 254. The through-hole leg 256 and the back-side contact leg 264 are partially merged in the back-side dielectric layer 248 and branch as they extend toward the first source / drain component 226 and the front contact 230.

[0044] Figure 14 It shows Figure 13 The dorsal side 200B of the precursor structure 200 in the middle (e.g. Figure 13 A schematic top view (as shown). Reference Figure 14 The base fin 202B extends longitudinally along the Y direction and is parallel to each other. A first gate structure 268 and a second gate structure 270 extend longitudinally along the X direction. A third gate structure 272 and a fourth gate structure 274 also extend longitudinally along the X direction. A gate isolation member 220 extends longitudinally along the Y direction between the first gate structure 268 and the second gate structure 270, and between the third gate structure 272 and the fourth gate structure 274. The gate isolation member 220 isolates the first gate structure 268 from the second gate structure 270, such that the first gate structure 268 and the second gate structure 270 are aligned longitudinally along the X direction. Similarly, the gate isolation member 220 isolates the third gate structure 272 from the fourth gate structure 274, such that the third gate structure 272 and the fourth gate structure 274 are aligned longitudinally along the X direction. Each of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274 encloses each channel member 2080 disposed above the base fin 202B (e.g., Figure 3 (As shown). Gate spacers 210 are disposed along the sidewalls of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274. Figure 14 As shown, the gate isolation member 220 is in contact with the sidewall of the gate spacer 210 along the sidewalls of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274. In some embodiments, the first etching process 300 for forming the through-hole opening 250 etches the gate spacer 210 at a slower rate, such that the gate spacer 210 defines the boundary of the through-hole leg 256 along the Y direction. Figure 14 In some embodiments shown, the through-hole leg 256 of the merged conductive member 266 is adjacent to and connected to the gate spacer 210. Still referring to... Figure 14 The first source / drain component 226 and the second source / drain component 227 are each disposed above the base fin 202B. On the back side 200B (e.g.) Figure 13 When the front contact 230 is facing upwards, it is positioned below the first source / drain component 226 and the second source / drain component 227, so as to allow the silicide component 228 (shown) to pass through. Figure 13 (Not shown) Coupled to the first source / drain component 226 and the second source / drain component 227.

[0045] In the depicted embodiment, the through-hole leg 256 and the back contact leg 264 of the merged conductive component 266 form a shape resembling the letter "T" or a T-shape in a top view. The through-hole leg 256 includes a first width W1 along the X direction and a first length L1 along the Y direction. The first width W1 differs from the first length L1. In some embodiments, the first length L1 is greater than the first width W1. In one embodiment, the ratio of the first length L1 to the first width W1 is between about 1.5 and about 2.5. In some cases, the first length L1 is between about 24 nm and about 72 nm, and the first width W1 is between about 12 nm and about 36 nm. The back contact leg 264 includes a third width W3 along the X direction and a second length L2 along the Y direction. The second length L2 may be similar to the third width W3. In one embodiment, the ratio of the second width W2 to the second length is between about 0.9 and about 1.1. Due to the different formation methods, the through-hole leg 256 has a larger footprint than the back contact leg 264. That is, the first length L1 is greater than the second length L2, and the first width W1 is greater than the third width W3. The through-hole leg 256 and the back contact leg 264 are continuous without any interface because they are formed simultaneously. This is not the case for the back contact 260 and the through-hole 252. Because the back contact 260 and the through-hole 252 are formed separately, there is an observable interface between the back contact 260 and the through-hole 252.

[0046] exist Figure 2 In the illustrated precursor structure 200, the front contact 230 does not extend above the third source / drain component 229. Figure 15 In some of the alternative embodiments shown, the long front contact 2300 extends continuously over the first source / drain component 226, the second source / drain component 227, and the third source / drain component 229, and is contacted by the silicide component 228. This arrangement allows for the possibility of forming another through-hole 2520 to contact the long front contact 2300. In some embodiments, the composition and formation method of through-holes 252 and 2520 are similar. In the depicted alternative embodiments, through-holes 252 and 2520 sandwich the back contact 260 in the middle and partially overlap with the back contact 260. Adding through-hole 2520 can further reduce contact resistance. Figure 16 schematically shown Figure 15 A top view of the semiconductor structure 200 in the image. (See image for reference.) Figure 16 As shown, Figure 15 Indicates crossing Figure 16 A partial cross-section of line AA in the diagram. Through holes 252 and 2520 can appear symmetrical with respect to the back contact 260. Both through holes 252 and 2520 are connected to the gate spacer 210 along the longitudinal direction (i.e., the Y direction).

[0047] In one example aspect, this disclosure provides a semiconductor structure. The semiconductor structure includes: a back-side dielectric layer; a back-side etch stop layer (ESL) located above the back-side dielectric layer; a first source / drain component and a second source / drain component located above the back-side ESL and spaced apart from each other along a first direction; a front-side source / drain contact disposed above the first source / drain component and the second source / drain component; a back-side contact component extending through the back-side dielectric layer and the back-side ESL to couple to the first source / drain component; a via extending through the back-side dielectric layer and the back-side ESL to couple to the front-side source / drain contact; a base fin located between the back-side ESL and the second source / drain component; and an isolation component including a portion extending along the sidewall of the base fin. The back-side contact component is in contact with the via in the back-side dielectric layer, and the isolation component comprises an oxide-based material.

[0048] In some embodiments, the front-side source / drain contact includes a portion extending along a first direction between the first source / drain component and the second source / drain component. In some embodiments, the first source / drain component is disposed along a second direction perpendicular to the first direction between the first gate structure and the second gate structure, and the second source / drain component is disposed along the second direction between the third gate structure and the fourth gate structure. In some embodiments, the back-side contact includes a first width along the second direction, and the via includes a second width along the second direction, and the second width is greater than the first width. In some cases, the via is adjacent to the first gate structure and the second gate structure. In some embodiments, the semiconductor structure further includes a plurality of nanostructures in contact with the sidewalls of the first source / drain component. The gate structure encloses each of the plurality of nanostructures. In some embodiments, the semiconductor structure further includes: a buffer semiconductor layer located above the substrate fin; and a bottom isolation layer located above the buffer semiconductor layer. In some embodiments, the buffer semiconductor layer includes undoped silicon, undoped germanium, or undoped silicon-germanium, and the bottom isolation layer includes silicon nitride.

[0049] Another aspect of this disclosure relates to a semiconductor structure. The semiconductor structure includes: a back-side dielectric layer; a back-side etch stop layer (ESL) located above the back-side dielectric layer; a first gate structure located above the back-side ESL; a second gate structure located above the back-side ESL and aligned with the first gate structure along a first direction; a third gate structure located above the back-side ESL; a fourth gate structure located above the back-side ESL and aligned with the third gate structure along the first direction; a first source / drain component located above the back-side ESL and disposed between the first and third gate structures along a second direction perpendicular to the first direction; a second source / drain component located above the back-side ESL and disposed between the second and fourth gate structures along a second direction; a front-side source / drain contact disposed above the first and second source / drain components; a back-side contact extending through the back-side dielectric layer and the back-side ESL to couple to the first source / drain component; and a via extending through the back-side dielectric layer and the back-side ESL to couple to the front-side source / drain contact. The back-side contact component is connected to the via in the back-side dielectric layer. The first gate structure includes a gate dielectric layer and a gate electrode layer located above the gate dielectric layer. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation component.

[0050] In some embodiments, the back-side contact member includes a first width along a second direction. The via includes a second width along the second direction, and the second width is greater than the first width. In some embodiments, the via is adjacent to the first gate structure and the third gate structure. In some embodiments, the semiconductor structure further includes a plurality of nanostructures in contact with the sidewalls of the first source / drain member. The first gate structure encloses each of the plurality of nanostructures. In some embodiments, the semiconductor structure further includes: a base fin located between the back-side ESL and the second source / drain member; and an isolation member including a portion extending along the sidewall of the base fin. In some embodiments, portions of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are disposed above and in contact with the isolation member. In some embodiments, the front-side source / drain contact includes a portion extending along a first direction between the first source / drain member and the second source / drain member. In some embodiments, the back-side contact member and the via are continuous structures.

[0051] Another aspect of this disclosure pertains to a method. The method includes: providing a precursor structure comprising: a first source / drain component and a second source / drain component located above a front source / drain contact; a first base fin located above the first source / drain component; a second base fin located above the second source / drain component; an isolation component disposed between the first base fin and the second base fin and extending along the sidewalls of the first base fin and the second base fin; and a gate isolation component disposed between the first base fin and the second base fin, a portion of the gate isolation component extending into the isolation component; and in the first base... A back-side etch stop layer (ESL) is deposited over a fin, a second base fin, an isolation component, and a gate isolation component; the method includes depositing a back-side dielectric layer over the back-side ESL; forming a via opening through the back-side dielectric layer, the back-side ESL, and the gate isolation component to expose front-side source / drain contacts; forming a via in the via opening; forming a back-side opening through the first base fin to expose a first source / drain component, such that a portion of the via is exposed in the back-side opening; and forming a back-side contact in the back-side opening, such that the back-side contact is in contact with the via.

[0052] In some embodiments, the bottom surface of the back-side contact member is lower than the bottom surface of the through-hole. In some embodiments, the formation of the through-hole includes using a first etching process, and the formation of the back-side opening includes using a second etching process different from the first etching process. In some embodiments, the first etching process etches silicon oxide faster than it etches silicon and silicon nitride, and the second etching process etches silicon faster than it etches silicon oxide and silicon nitride.

[0053] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: a backside dielectric layer; a backside etch stop layer (ESL) located above the backside dielectric layer; a first source / drain component and a second source / drain component located above the backside etch stop layer and spaced apart from one another along a first direction; a frontside source / drain contact disposed above the first source / drain component and the second source / drain component; a backside contact component extending through the backside dielectric layer and the backside etch stop layer to couple to the first source / drain component; a via extending through the backside dielectric layer and the backside etch stop layer to couple to the frontside source / drain contact; a base fin located between the backside etch stop layer and the second source / drain component; and an isolation component comprising a portion extending along a sidewall of the base fin, wherein the backside contact component meets the via in the backside dielectric layer, wherein the isolation component comprises an oxide-based material. The frontside source / drain contact comprises a portion extending between the first source / drain component and the second source / drain component along the first direction.

2. The semiconductor structure of claim 1, wherein, 3. The semiconductor structure of claim 1, the first source / drain component is disposed between a first gate structure and a second gate structure along a second direction perpendicular to the first direction, wherein wherein the second source / drain component is disposed between a third gate structure and a fourth gate structure along the second direction.

4. The semiconductor structure of claim 3, the backside contact component comprises a first width along the second direction, wherein wherein the via comprises a second width along the second direction, wherein the second width is greater than the first width. The via abuts the first gate structure and the second gate structure.

5. The semiconductor structure of claim 3, wherein, 6. The semiconductor structure of claim 3, further comprising: a plurality of nanostructures meeting a sidewall of the first source / drain component, wherein the first gate structure encloses each of the plurality of nanostructures.

7. The semiconductor structure of claim 1, further comprising: a buffer semiconductor layer located above the base fin; and a bottom isolation layer located above the buffer semiconductor layer.

8. The semiconductor structure of claim 7, the buffer semiconductor layer comprises undoped silicon, undoped germanium, or undoped silicon germanium, wherein the bottom isolation layer comprises silicon nitride. wherein 9. A semiconductor structure, comprising: a backside dielectric layer; a backside etch stop layer (ESL) located above the backside dielectric layer; a first gate structure located above the backside etch stop layer; a second gate structure located above the backside etch stop layer and aligned with the first gate structure along a first direction; a third gate structure located above the backside etch stop layer; a fourth gate structure located above the backside etch stop layer and aligned with the third gate structure along the first direction; ​ ​ a first source / drain component located above the backside etch stop layer and disposed between the first gate structure and the third gate structure along a second direction perpendicular to the first direction; a second source / drain component located above the backside etch stop layer and disposed between the second gate structure and the fourth gate structure along the second direction; a frontside source / drain contact disposed above the first source / drain component and the second source / drain component; a backside contact component extending through the backside dielectric layer and the backside etch stop layer to couple to the first source / drain component; and a through-hole extending through the backside dielectric layer and the backside etch stop layer to couple to the frontside source / drain contact, wherein the backside contact component meets the through-hole in the backside dielectric layer, wherein the first gate structure includes a gate dielectric layer and a gate electrode layer located above the gate dielectric layer, wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the isolation component.

10. A method of forming a semiconductor structure, comprising: providing a precursor structure, the precursor structure including: a first source / drain component and a second source / drain component located above a frontside source / drain contact, a first base fin located above the first source / drain component, a second base fin located above the second source / drain component, an isolation component disposed between the first base fin and the second base fin and extending along sidewalls of the first base fin and the second base fin, and a gate isolation component disposed between the first base fin and the second base fin, a portion of the gate isolation component extending into the isolation component; depositing a backside etch stop layer (ESL) above the first base fin, the second base fin, the isolation component, and the gate isolation component; depositing a backside dielectric layer above the backside etch stop layer; forming a through-hole opening through the backside dielectric layer, the backside etch stop layer, and the gate isolation component to expose the frontside source / drain contact; forming a through-hole in the through-hole opening; forming a backside opening through the first base fin to expose the first source / drain component such that a portion of the through-hole is exposed in the backside opening; and forming a backside contact component in the backside opening such that the backside contact component meets the through-hole. ​

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