Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming the same are provided. The semiconductor device may include: a first source / drain region; a first nanostructure on a first sidewall of the first source / drain region; a first gate structure around the first nanostructure; a first internal spacer on a first sidewall of the first source / drain region; a second internal spacer on a second sidewall of the first source / drain region; a first dielectric pad on a sidewall of the second internal spacer; and a first isolation feature on a sidewall of the first dielectric pad. The first internal spacer may be between the first gate structure and the first source / drain region. A second internal spacer may be between the first dielectric liner and the first source / drain region. A first dielectric liner may be between the first isolation feature and the second internal spacer.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum part size, allowing more components to be integrated into a given area. As the semiconductor industry further moves towards increasing device density, higher performance, and lower cost, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). While the minimum part size decreases, additional components are introduced. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device, including: a first source / drain region; a first nanostructure located on a first sidewall of the first source / drain region; a first gate structure located around the first nanostructure; a first internal spacer located on the first sidewall of the first source / drain region, wherein the first internal spacer is located between the first gate structure and the first source / drain region; a second internal spacer located on a second sidewall of the first source / drain region, wherein the second sidewall is opposite to the first sidewall; a first dielectric pad located on the sidewall of the second internal spacer, wherein the second internal spacer is located between the first dielectric pad and the first source / drain region; and a first isolation member located on the sidewall of the first dielectric pad, wherein the first dielectric pad is located between the first isolation member and the second internal spacer.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first nanostructure and forming a second nanostructure over the first nanostructure; growing a first source / drain region and a second source / drain region, wherein the first nanostructure is located on a sidewall of the first source / drain region, and wherein the second nanostructure is located on a sidewall of the second source / drain region; forming a first opening by removing a first portion of the second nanostructure, wherein a second portion of the second nanostructure remains on the sidewall of the second source / drain region; depositing a dielectric pad in the first opening, wherein... A dielectric pad is located on the sidewall of the second portion of the second nanostructure; the first opening is extended by removing a first portion of the dielectric pad and a first portion of the first nanostructure, wherein a second portion of the dielectric pad remains on the sidewall of the second portion of the second nanostructure, and wherein a second portion of the first nanostructure remains on the sidewall of the first source / drain region; and a first isolation member is deposited in the first opening, wherein the first isolation member is located on the sidewall of the second portion of the dielectric pad, and wherein the first isolation member is located on the sidewall of the second portion of the first nanostructure.

[0006] Some embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first nanostructure; forming a first internal spacer, wherein the first internal spacer is located on the top surface of the first nanostructure; forming a first isolation member below the first nanostructure; forming a first dielectric member, wherein the first isolation member is located on the sidewall of the first dielectric member; growing a first source / drain region above the first dielectric member, wherein the first nanostructure and the first internal spacer are located on the sidewall of the first source / drain region; forming a first opening by removing a first portion of the first nanostructure and a first portion of the first internal spacer, wherein a second portion of the first nanostructure and a second portion of the first internal spacer remain on the sidewall of the first source / drain region, and wherein the top surface of the first isolation member is formed by the first internal spacer. A first opening is exposed; a dielectric pad is deposited in the first opening, wherein the dielectric pad is located on the sidewall of the second portion of the first nanostructure, the sidewall of the second portion of the first internal spacer, and the top surface of the first isolation member; the first opening is extended by removing the first portion of the dielectric pad and the first portion of the first isolation member, wherein a second portion of the dielectric pad remains on the sidewall of the second portion of the first nanostructure and the sidewall of the second portion of the first internal spacer, and wherein a second portion of the first isolation member remains on the sidewall of the first dielectric member; and a second isolation member is deposited in the first opening, wherein the second isolation member is located on the sidewall of the second portion of the dielectric pad, and wherein the second isolation member is located on the sidewall of the second portion of the first isolation member. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of an exemplary stacked transistor according to some embodiments is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12 and Figure 13 These are various views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] Various embodiments provide semiconductor devices and methods for forming the same. The semiconductor device can be a stacked transistor comprising a vertically stacked upper transistor and a lower transistor. Each of the upper and lower transistors may include a gate structure enclosing a corresponding semiconductor nanostructure and source / drain regions located on the sidewalls of the corresponding semiconductor nanostructure. In certain regions of the semiconductor device, isolation components may extend through the upper and lower transistors. Prior to forming the isolation components, a dielectric pad may be formed in the upper transistor to protect the source / drain regions in the upper transistor during various etching processes, which can create openings for forming the isolation components. Therefore, the performance and reliability of the stacked transistor can be improved.

[0013] Figure 1An example of a stacked transistor 10 according to some embodiments is shown. Figure 1 This is a three-dimensional diagram, and for clarity, some components of the stacked transistor are omitted. The stacked transistor comprises multiple vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type or p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type or n-type). When the stacked transistor is a complementary field-effect transistor (CFET), the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The upper nanostructure FET 10U and the lower nanostructure FET 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, stacked transistors can be applied to other types of transistors, nanofield-effect transistors (nanoFETs), fin field-effect transistors (finFETs), etc.

[0014] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each of the source / drain regions 62 may refer to either a source or a drain, individually or collectively, depending on the context. Isolation components (not shown) may be formed to separate selected source / drain regions 62 and / or selected gate electrodes 80.

[0015] Figure 1 Reference sections A-A' and B-B' are also shown. Reference section A-A' may be a vertical section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor 10 and, for example, in the direction of current between the source / drain regions 62 of the stacked transistor 10. Reference section B-B' may be a vertical section perpendicular to reference section A-A' and extending through the gate electrode 80. Figure 1 The reference sections A-A' and B-B' in the figure may correspond to some of the reference sections A-A' and B-B' shown in the subsequent top-down view figures.

[0016] Figures 2 to 13 It is a stacked transistor according to some embodiments, including a lower nanostructure FET and an upper nanostructure FET (which may be similar to...). Figure 1Various views of intermediate stages in the fabrication of the stacked transistor 10 shown. Figure 2 It is a 3D image, and Figures 3 to 13 yes Figure 2 The diagram shows a cross-sectional view and a top-down view of a portion of the structure. Figure 2 The wafer is provided, and the wafer includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, or combinations thereof.

[0017] Semiconductor strips 28 are formed extending upward from substrate 20. Each of the semiconductor strips 28 includes a semiconductor fin 20' (a patterned portion of substrate 20) and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to below as nanostructures. Specifically, the multilayer stack 22 includes pseudo-nanostructures 24A and 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Pseudo-nanostructures 24A and 24B can be further collectively referred to as pseudo-nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0018] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, the pseudo-nanostructure 24B can be removed in a subsequent process at a faster rate than the pseudo-nanostructure 24A.

[0019] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the pseudo-nanostructure 24 exhibit high etch selectivity towards the third semiconductor material of the semiconductor nanostructure 26. Therefore, the pseudo-nanostructure 24 can be selectively removed in subsequent processes without significantly removing the semiconductor nanostructure 26. In some embodiments, the semiconductor nanostructure 26 is formed of silicon, the pseudo-nanostructure 24A is formed of silicon-germanium, and the pseudo-nanostructure 24B is formed of germanium or silicon-germanium having a higher percentage of germanium atoms than the pseudo-nanostructure 24A.

[0020] The lower semiconductor nanostructure 26L can be used as a channel region for a lower nanostructure FET used in stacked transistors. The upper semiconductor nanostructure 26U can be used as a channel region for an upper nanostructure FET used in stacked transistors. The semiconductor nanostructure 26 directly above / below (e.g., in contact with) the pseudo-nanostructure 24B can be used for isolation and may or may not be used as a channel region for stacked transistors. The pseudo-nanostructure 24B can then be replaced with an isolation structure defining the boundary between the lower and upper nanostructure FETs.

[0021] To form the semiconductor strip 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (arranged as shown and described above) can be deposited over the substrate 20. These layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the substrate 20 to define the semiconductor strip 28, which includes semiconductor fins 20', pseudo-nanostructures 24, and semiconductor nanostructures 26.

[0022] For example, the patterning process may include one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller pitch than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, and the substrate 20. Etching can be performed using any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0023] An STI region 34 is formed over the substrate 20 and between adjacent semiconductor strips 28. The STI region 34 may include dielectric pads and dielectric material above the dielectric pads. Each of the dielectric pads and dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof. Forming the STI region 34 may include: depositing a dielectric layer; and performing a planarization process such as chemical mechanical polishing (CMP), mechanical polishing, etc., to remove excess portions of the dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, the STI region 34 comprises silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric pads and dielectric material are then recessed to define the STI region 34, such that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 34.

[0024] After forming the STI region 34, a dummy gate stack 42 can be formed above the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 34) and along the sidewalls of the upper portion of the semiconductor strip 28. Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28 and forming a dummy gate layer 38 above the dummy dielectric layer 36. The dummy dielectric layer 36 can be formed from, for example, silicon oxide, silicon nitride, combinations thereof, and can be deposited or thermally grown according to acceptable techniques. The dummy gate layer 38 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 can be selected from the group including amorphous silicon, polycrystalline silicon, polysilicon germanium (poly-SiGe), etc.

[0025] A mask layer 40' is formed over the planarized dummy gate layer 38. The mask layer 40' may include silicon nitride, silicon oxynitride, etc. The mask layer 40' can then be patterned using suitable photolithography and etching processes to form the mask 40. Figure 3 (as shown in the diagram), and then mask 40 can be used to pattern the dummy gate layer 38 and the dummy dielectric layer 36. Mask 40, the remainder of the dummy gate layer 38 and the dummy dielectric layer 36 can be referred to as dummy gate stack 42.

[0026] exist Figure 3In this process, a gate spacer 44 and a source / drain recess 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc. The mask 40 and the gate spacer 44 can be used to protect the dummy gate layer 38 during the subsequent etching process.

[0027] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into the semiconductor fin 20'. The bottom surface of the source / drain recesses 46 can be located above, below, or flush with the top surface of the STI region 34 (not shown). During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. When the source / drain recesses 46 reach a selected depth, a timing etching process can be used to stop the etching of the source / drain recesses 46.

[0028] exist Figure 4 In the process, pseudo-nanostructure 24A is partially removed, and pseudo-nanostructure 24B is completely removed. Then, internal spacers 54 and dielectric isolation layers 56 are formed. After the partial removal of pseudo-nanostructure 24A, the sidewalls of pseudo-nanostructure 24A can be recessed. Pseudo-nanostructures 24A and 24B can be removed by a suitable etching process. The etching process can selectively remove material from pseudo-nanostructures 24A and 24B without significantly removing material from the upper semiconductor nanostructure 26U, the lower semiconductor nanostructure 26L, or the semiconductor fin 20'. The etching process can remove pseudo-nanostructure 24A at a slower rate than that removing pseudo-nanostructure 24B.

[0029] In embodiments where pseudo-nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, pseudo-nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process can be a dry etching process using an etchant such as chlorine. Because the pseudo-gate stack 42 surrounds the sidewalls of semiconductor nanostructure 26 (see...), the etching process can be a dry etching process using an etchant such as chlorine. Figure 2 Therefore, the pseudo-gate stack 42 can support the upper semiconductor nanostructure 26U, so that the upper semiconductor nanostructure 26U will not collapse when the pseudo-nanostructure 24B is completely removed.

[0030] Internal spacers 54 can be formed on the recessed sidewalls of the pseudo-nanostructure 24A. A dielectric isolation layer 56 can be formed in the spacers occupied by the pseudo-nanostructure 24B before its removal. Source / drain regions can then be formed in the source / drain recesses 46, and the pseudo-nanostructure 24A can be replaced with a corresponding gate structure. Internal spacers 54 can be used to isolate the subsequently formed source / drain regions from the subsequently formed gate structure. The dielectric isolation layer 56 can be used to isolate the upper semiconductor nanostructure 26U from the lower semiconductor nanostructure 26L.

[0031] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing a suitable dielectric material in the source / drain trench 46, on the sidewalls of the pseudo-nanostructure 24A, and between the upper semiconductor nanostructure 26U at the bottom and the lower semiconductor nanostructure 26L at the top. The dielectric material can then be etched to remove excess portions. The dielectric material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon oxycarbonate, silicon carbonitride, etc. Other low dielectric constant (low-k) materials with a k value less than about 3.5 can be utilized. The dielectric material can be formed by a suitable deposition process, such as ALD, CVD, etc. The etching of the dielectric material can be anisotropic or isotropic etching processes.

[0032] exist Figure 5A , Figure 5B and Figure 5C In the source / drain groove 46, a lower source / drain region 62L, an upper epitaxial source / drain region 62U, a first contact etch stop layer (CESL) 66, a first interlayer dielectric (ILD) 68, a second CESL 70, and a second ILD 72 are formed. Figure 5C This is a top-down view, in which some parts are omitted for illustrative purposes, and some parts are shown with dashed lines. Figure 5C The reference sections A-A' and B-B' shown can correspond to Figure 1 The reference sections A-A' and B-B' are shown in the figure. Figure 5A Is along as Figure 5C The cross-sectional view of reference section A-A' shown in the figure. Figure 5B Is along as Figure 5C The cross-sectional view of reference section B-B' shown in the figure.

[0033] A lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26L but not the upper semiconductor nanostructure 26U. The upper epitaxial source / drain region 62U contacts the upper semiconductor nanostructure 26U but not the lower semiconductor nanostructure 26L. The lower epitaxial source / drain region 62L contacts the internal spacer 54, which electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A. The upper epitaxial source / drain region 62U contacts the internal spacer 54, which electrically insulates the upper epitaxial source / drain region 62U from the pseudo-nanostructure 24A. In subsequent processes, the pseudo-nanostructure 24A will be replaced with a replacement gate.

[0034] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0035] Due to the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has small facets that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these small facets cause adjacent lower epitaxial source / drain regions 62L to merge.

[0036] The first CESL 66 and the first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0037] The formation process may include: depositing a conformal CESL; depositing material for the first ILD 68; and a subsequent planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the conformal CESL unetched. An anisotropic etching process is then performed to remove the portion of the conformal CESL above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0038] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower epitaxial source / drain region 62L, depending on the selected conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U can be in situ doped with n-type or p-type dopants and / or implanted with n-type or p-type dopants.

[0039] Due to the epitaxial process used to form the upper epitaxial source / drain regions 62U, the upper surface of the upper epitaxial source / drain regions 62U has small facets that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent upper epitaxial source / drain regions 62U remain separated after the epitaxial process is completed. In other embodiments, these small facets cause adjacent upper epitaxial source / drain regions 62U to merge.

[0040] After forming the upper epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively. The formation process may include: depositing a conformal CESL and the second ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 40 are substantially coplanar (within process variations). In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, thereby exposing the top surface of the dummy gate layer 38.

[0041] exist Figure 6A , Figure 6B and Figure 6C In the process, a mask 100 is formed, and an opening 101 is formed using the mask 100 to expose the top surface of a selected portion of the selected upper semiconductor nanostructure 26U and STI region 34. Figure 6C This is a top-down view, in which some parts are shown in dashed lines for illustrative purposes. Figure 6C The reference sections A-A' and B-B' shown can correspond to Figure 5C The reference sections A-A' and B-B' are shown in the figure. Figure 6A Is along as Figure 6C The cross-sectional view of reference section A-A' shown in the figure. Figure 6B Is along as Figure 6C The cross-sectional view of reference section B-B' shown in the figure.

[0042] Mask 100 can be formed from a suitable dielectric material and through a suitable deposition and patterning method. Openings in mask 100 can expose selected portions of mask 40. Opening 101 can be formed by one or more etching processes by removing the exposed portions of mask 40 and the portions of dummy gate layer 38 and dummy dielectric layer 36 located below the exposed portions of mask 40. The exposed portions of mask 40 can be removed by a dry etching process using fluorine-based plasma as the etchant. The exposed portions of dummy gate layer 38 can then be removed by one or more dry etching processes using chlorine or bromine-based plasma as the etchant. The exposed portions of dummy dielectric layer 36 can then be removed by a wet etching process using hydrofluoric acid, ammonium hydroxide, etc., as the etchant. After forming opening 101, the top surfaces of selected portions of the selected upper semiconductor nanostructure 26U and STI region 34, as well as the sidewalls of the corresponding gate spacer 44 and multilayer stack 22, are exposed.

[0043] exist Figure 7A and Figure 7BIn this process, the opening 101 is extended by removing a portion of the upper semiconductor nanostructure 26U, a portion of the internal spacer 54, and the pseudo nanostructure 24A to expose the underlying dielectric isolation layer 56. Figure 7A It corresponds to Figure 6A The cross-sectional view shown is a cross-sectional view of the diagram shown. Figure 7B It corresponds to Figure 6B The cross-sectional view shown is shown. A portion of the upper semiconductor nanostructure 26U and the portion of the internal spacer 54, as well as the pseudo-nanostructure 24A, located directly below the opening 101, can be removed by one or more dry etching processes using chlorine or bromine-based plasma as the etchant. After one or more dry etching processes, a portion of the upper semiconductor nanostructure 26U and the portion of the internal spacer 54 located directly below the gate spacer 44 can remain on the sidewalls of the adjacent upper epitaxial source / drain region 62U and the first CESL 66. After extending the opening 101, the sidewalls of the remaining portions of the upper semiconductor nanostructure 26U and the internal spacer 54, as well as the top surface of the dielectric isolation layer 56, are exposed.

[0044] exist Figure 8A and Figure 8B In the middle, a dielectric pad 102 is formed in the opening 101. Figure 8A It corresponds to Figure 7A The cross-sectional view shown is a cross-sectional view of the diagram shown. Figure 8B It corresponds to Figure 7B The cross-sectional view shown is a cross-sectional view. The dielectric pad 102 may be a conformal layer covering the top surface of the mask 100 and the surface exposed by the opening 101. This surface may include the top surface of the dielectric isolation layer 56 and the STI region 34, as well as the mask 100, the gate spacer 44, the upper semiconductor nanostructure 26U and the remainder of the inner spacer 54, the dielectric isolation layer 56, the lower semiconductor nanostructure 26L, the pseudo-nanostructure 24A, and the sidewalls of the semiconductor fin 20'. As described in more detail below, the dielectric pad 102 may provide protection for the mask 100 and the remainder of the inner spacer 54 during subsequent etching processes. The dielectric pad 102 may be formed of silicon nitride, silicon carbide, silicon carbonitride, aluminum oxide, titanium nitride, etc. The dielectric pad 102 may be formed by a suitable deposition process, such as CVD, ALD, etc.

[0045] exist Figure 9A and Figure 9B In the process, a portion of dielectric pad 102 is removed to partially expose the top surface of dielectric isolation layer 56 and STI region 34. After removal, dielectric pad 102 can be divided into an upper portion of dielectric pad 102U and a lower portion of dielectric pad 102L. Figure 9A It corresponds to Figure 8A The cross-sectional view shown is a cross-sectional view of the diagram shown. Figure 9B It corresponds to Figure 8BThe cross-sectional view shown is shown. A portion of the dielectric pad 102 can be removed by a dry etching process using fluorine-based plasma as the etchant. The etching process can be an anisotropic etching process, which can remove the horizontal portion of the dielectric pad 102 at a higher rate than the vertical portion. During the etching process, carbon-based byproducts generated by the plasma may concentrate at the upper portion of the opening 101, which can protect portions of the dielectric pad 102 adjacent to the mask 100 from the etchant. The vertical portion of the dielectric pad 102 adjacent to the STI region 34 can also be partially removed.

[0046] After the etching process, such as Figure 9A As shown, a portion of the top surface of the dielectric isolation layer 56 can be exposed, and the upper portion of the dielectric pad 102U can remain on the top surface of the mask 100 and the dielectric isolation layer 56, as well as on the remaining portions of the mask 100, the gate spacer 44, the upper semiconductor nanostructure 26U, and the sidewalls of the internal spacer 54. After the etching process, as... Figure 9B As shown, a portion of the top surface of the STI region 34 can be exposed, and a portion of the lower dielectric pad 102L can be retained on the top surface of the STI region 34, as well as on the sidewalls of the lower semiconductor nanostructure 26L, pseudo-nanostructure 24A, and semiconductor fin 20'.

[0047] exist Figure 10A and Figure 10B In this process, the opening 101 is further extended by removing a portion of the dielectric isolation layer 56, a portion of the lower semiconductor nanostructure 26L, the pseudo nanostructure 24A, and the semiconductor fin 20' to expose the underlying substrate 20. The portion of the internal spacer 54 located below the dielectric isolation layer 56 may also be removed. After further extending the opening 101, the opening 101 may have a curved bottom surface. Figure 10A It corresponds to Figure 9A The cross-sectional view shown is a cross-sectional view of the diagram shown. Figure 10B It corresponds to Figure 9B The cross-sectional view shown is shown. A portion of the dielectric isolation layer 56, a portion of the lower semiconductor nanostructure 26L, and the portion of the internal spacer 54 located directly below the opening 101, as well as the pseudo nanostructure 24A and the semiconductor fin 20', can be removed by one or more dry etching processes using chlorine or bromine-based plasma as the etchant.

[0048] Because the upper portion of the dielectric pad 102U on the sidewalls of mask 100 and the remaining portion of the internal spacer 54 are adequately protected during the etching process, the risk of damage to adjacent upper epitaxial source / drain regions 62U, the first CESL 66, and the second CESL 70 during the etching process can be improved. Therefore, the performance and reliability of the subsequently formed stacked transistors can be enhanced.

[0049] Following one or more dry etching processes, portions of the dielectric isolation layer 56, portions of the lower semiconductor nanostructure 26L, and portions of the internal spacer 54 located directly below the upper portions of the gate spacer 44 and the dielectric pad 102U may remain on the sidewalls of the adjacent lower epitaxial source / drain region 62L and the first CESL 66. After further extending the opening 101, the remaining sidewalls of the dielectric isolation layer 56, the lower semiconductor nanostructure 26L, and the internal spacer 54, the lower portion of the dielectric pad 102L, the STI region 34, the sidewalls of the substrate 20, and the upper surface of the substrate 20 are exposed.

[0050] The upper portion of dielectric pad 102U and the lower portion of dielectric pad 102L may have a thickness T1 ranging from about 1 nm to about 2 nm. The remaining portion of the internal spacer 54, which contacts the remaining portion of the upper semiconductor nanostructure 26U, may have a thickness T2 ranging from about 1.6 nm to about 2.4 nm. The remaining portion of the upper semiconductor nanostructure 26U may have a thickness T3 ranging from about 1.6 nm to about 2.4 nm. The remaining portion of the dielectric isolation layer 56 may have a thickness T4 ranging from about 2.4 nm to about 3.6 nm. Thickness T4 may be greater than thickness T2. The remaining portion of the internal spacer 54, which contacts the remaining portion of the lower semiconductor nanostructure 26L, may have a thickness T5 ranging from about 2.4 nm to about 3.6 nm. The remaining portion of the lower semiconductor nanostructure 26L may have a thickness T6 ranging from about 2.4 nm to about 3.6 nm. Thickness T5 may be greater than thickness T2. Thickness T6 can be greater than thickness T3. The complete internal spacer 54 in other multi-layer stacked components 22 can have a thickness T7, which can be greater than thickness T5 and thickness T2.

[0051] exist Figure 11A , Figure 11B and Figure 11C In the middle, an isolation member 103 is formed in the opening 101, and a portion of the upper part of the mask 100 and the dielectric pad 102U is removed. Figure 11C This is a top-down view, in which some parts are omitted for illustrative purposes, and some parts are shown with dashed lines. Figure 11CThe reference sections A-A' and B-B' shown can correspond to Figure 6C The reference sections A-A' and B-B' are shown in the figure. Figure 11A Is along as Figure 11C The cross-sectional view of reference section A-A' shown in the figure. Figure 11B Is along as Figure 11C The cross-sectional view of reference section B-B' shown. The isolation member 103 can fill the opening 101 and contact the surface previously exposed by the opening 101. The sidewalls of the upper portion of the dielectric pad 102U can be covered by the isolation member 103. The top surface and sidewalls of the lower portion of the dielectric pad 102L can be covered by the isolation member 103.

[0052] The isolation component 103 may be formed of one or more dielectric materials, such as silicon nitride, silicon oxide, etc. In some embodiments, the isolation component 103 and the dielectric pad 102 comprise different materials. In some embodiments, the isolation component 103 and the dielectric pad 102 comprise the same material. In some embodiments, the isolation component 103 comprises multiple layers of different dielectric materials. The isolation component 103 may be formed by one or more suitable deposition processes, such as CVD, ALD, etc. After the deposition process, a planarization process, such as CMP, etch-back, or combinations thereof, may be performed to remove excess deposited material and the portion of the upper portion of the mask 100 and the dielectric pad 102U located on the mask 100. After the planarization process, the mask 40, gate spacer 44, second CESL 70, second ILD 72, the upper portion of the dielectric pad 102U, and the top surface of the isolation component 103 may be substantially coplanar (within process variations).

[0053] exist Figure 12 In this embodiment, a gate replacement process is implemented to replace the dummy gate stack 42 and the dummy nanostructure 24A with the gate structure 90. The gate replacement process may include first removing the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 can be removed by one or more suitable etching processes. Then, the dummy nanostructure 24A can be removed by an additional suitable etching process. The etching process for removing the dummy nanostructure 24A can selectively remove material from the dummy nanostructure 24A without significantly removing material from the semiconductor nanostructure 26. In embodiments where the dummy nanostructure 24A comprises silicon germanium and the semiconductor nanostructure 26 comprises silicon, the etching process may be a wet isotropic etching process, and etchants such as tetramethylammonium hydroxide, ammonium hydroxide, etc., may be used.

[0054] Then, a gate dielectric 78 can be deposited in the grooves between the gate spacers 44 and on the exposed semiconductor nanostructure 26. The gate dielectric 78 can be conformally formed on the exposed surface of the grooves (removed dummy gate stack 42 and dummy nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 encloses all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 can be formed on the top surface of the semiconductor fin 20'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 26; and the sidewalls of the internal spacers 54.

[0055] Gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. Gate dielectric 78 may include high-k materials having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove portions of gate dielectric 78 above the second ILD 72. While a single-layer gate dielectric 78 may be shown, gate dielectric 78 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0056] A lower gate electrode 80L can be formed on the gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. The lower gate electrode 80L can encapsulate the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L can include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials. The lower gate electrode 80L can be formed by: conformally depositing one or more gate electrode layers; or recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0057] The lower gate electrode 80L can be formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0058] In some embodiments, an isolation layer (not shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0059] An upper gate electrode 80U may be formed on the isolation layer (if present) or the lower gate electrode 80L described above. The upper gate electrode 80U may be disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U encapsulates the upper semiconductor nanostructure 26U. The upper gate electrode 80U may be formed of the same or similar material as the lower gate electrode 80L and by the same or similar process as the lower gate electrode 80L. The upper gate electrode 80U may be formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more power function adjustment layers (e.g., n-type power function adjustment layers and / or p-type power function adjustment layers) formed of a material suitable for the device type of the upper nanostructure FET. Although a single-layer upper gate electrode 80U is shown, the upper gate electrode 80U may include any number of power function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0060] A gate mask 92 can be formed on the upper gate structure 90U. The formation process may include: recessing the upper gate structure 90U; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.; and performing a planarization process to remove excess dielectric material above the second ILD 72, and to make the top surfaces of the gate mask 92 and the second ILD 72 flush. The planarization process may be a CMP process, an etch-back process, a combination thereof, etc. After the planarization process, the top surfaces of the gate mask 92, the gate dielectric 78, the second ILD 72, and the gate spacer 44 may be substantially coplanar (within process variations). Each corresponding pair of gate dielectric 78 and gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) may be collectively referred to as a “gate structure” 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 is along the semiconductor nanostructure 26 (see...). Figure 1 The channel region of the semiconductor fin 20' extends along three sides (e.g., top, sidewall, and bottom). The lower gate structure 90L may also extend along the sidewall and / or top surface of the semiconductor fin 20'.

[0061] exist Figure 13 In the second ILD 72, a metal-semiconductor alloy region 94 and a source / drain contact 96 are formed to electrically couple to an upper epitaxial source / drain region 62U and / or a lower epitaxial source / drain region 62L. As an example of forming the source / drain contact 96, an opening is formed through the second ILD 72 and the second CESL 70 using acceptable photolithography and etching techniques. A pad (not shown separately), such as a diffusion barrier layer or an adhesive layer, and a conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process may be performed to remove excess material from the gate spacer 44 and the top surface of the second ILD 72. The remaining pad and conductive material form the source / drain contact 96 in the opening. In some embodiments, a planarization process, such as CMP, etch-back process, or a combination thereof, is utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contact 96 are substantially coplanar (within process variations).

[0062] Optionally, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 94 can be formed prior to the material of the source / drain contact 96 by depositing metal in the opening for the source / drain contact 96 and then performing a thermal annealing process. The metal can be any metal capable of reacting with semiconductor materials (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings used for the source / drain contacts 96 (such as from the surface of the metal-semiconductor alloy region 94). The material for the source / drain contacts 96 can then be formed on the metal-semiconductor alloy region 94.

[0063] Then, a third CESL 104 and a third ILD 106 are formed. In some embodiments, the third CESL 104 may include a dielectric material with high etch selectivity relative to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon carbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0064] Subsequently, a gate contact 108 and a source / drain via 110 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming the gate contact 108 and the source / drain via 110, openings for the gate contact 108 and the source / drain via 110 are formed through the third ILD 106 and the third CESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 106. The remaining pads and conductive material form the gate contact 108 and the source / drain via 110 in the openings. The gate contact 108 and the source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed in a different cross section, which can avoid short circuits in the contacts.

[0065] A front-side interconnect structure 114 is formed on the third ILD 106. The front-side interconnect structure 114 includes a dielectric layer 116 and a layer of conductive components 118 within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 116 may also include a polymer layer.

[0066] Conductive components 118 may include wires and vias, which can be formed using an inlay process. Conductive components 118 may include metal wires and metal vias, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads electrically connected to the metal wires and vias may also be present above the metal wires and vias. In some embodiments, contacts may be formed through the back side of the substrate 20 (e.g., the side opposite the front interconnect structure 114) to the lower gate structure 90L and the lower epitaxial source / drain region 62L. Figure 13 The structure shown can be called a stacked transistor 150.

[0067] The embodiments disclosed herein have several advantageous features. Due to the formation of the dielectric pad 102U, the remaining portion of the mask 100 and internal spacer 54 covered by the dielectric pad 102U can be adequately protected during the etching process that further extends the opening 101. This reduces the risk of damage to adjacent upper epitaxial source / drain regions 62U, the first CESL 66, and the second CESL 70 during said etching process. Therefore, the performance and reliability of the stacked transistor 150 can be improved.

[0068] In an embodiment, the semiconductor device includes: a first source / drain region; a first nanostructure located on a first sidewall of the first source / drain region; a first gate structure located around the first nanostructure; a first internal spacer located on the first sidewall of the first source / drain region, wherein the first internal spacer is located between the first gate structure and the first source / drain region; a second internal spacer located on a second sidewall of the first source / drain region, wherein the second sidewall is opposite to the first sidewall; a first dielectric pad located on the sidewall of the second internal spacer, wherein the second internal spacer is located between the first dielectric pad and the first source / drain region; and a first isolation member located on the sidewall of the first dielectric pad, wherein the first dielectric pad is located between the first isolation member and the second internal spacer. In an embodiment, the first dielectric pad includes a first material, wherein the first isolation member includes a second material different from the first material. In an embodiment, the semiconductor further includes a second isolation member located below the second internal spacer, wherein the first dielectric pad is located on the top surface of the second isolation member. In one embodiment, the second isolation member and the second internal spacer comprise the same material. In another embodiment, the second internal spacer is thinner than the first internal spacer. In yet another embodiment, the semiconductor device further comprises: a second source / drain region located below the first source / drain region; and a third internal spacer located between the second source / drain region and the first isolation member, wherein the second internal spacer is thinner than the third internal spacer. In yet another embodiment, the semiconductor device further comprises: a second isolation member located below the first source / drain region, wherein the first isolation member extends into the second isolation member; and a second dielectric pad located on the top surface of the second isolation member, wherein the first dielectric pad and the second dielectric pad comprise the same first material different from the second material of the first isolation member, and wherein the first isolation member is located on the top surface and sidewalls of the second dielectric pad.

[0069] In an embodiment, a method for forming a semiconductor device includes: forming a first nanostructure and forming a second nanostructure over the first nanostructure; growing a first source / drain region and a second source / drain region, wherein the first nanostructure is located on the sidewall of the first source / drain region, and wherein the second nanostructure is located on the sidewall of the second source / drain region; forming a first opening by removing a first portion of the second nanostructure, wherein a second portion of the second nanostructure remains on the sidewall of the second source / drain region; depositing a dielectric pad in the first opening, wherein the dielectric pad is located on the sidewall of the second portion of the second nanostructure; extending the first opening by removing the first portion of the dielectric pad and the first portion of the first nanostructure, wherein the second portion of the dielectric pad remains on the sidewall of the second portion of the second nanostructure, and wherein the second portion of the first nanostructure remains on the sidewall of the first source / drain region; and depositing a first isolation member in the first opening, wherein the first isolation member is located on the sidewall of the second portion of the dielectric pad, and wherein the first isolation member is located on the sidewall of the second portion of the first nanostructure. In one embodiment, the second portion of the first nanostructure has a greater thickness than the second portion of the second nanostructure. In another embodiment, the dielectric pad and the first isolation member comprise different materials. In yet another embodiment, the dielectric pad is located between the second portion of the second nanostructure and the first isolation member. In yet another embodiment, the method further includes forming the second isolation member between the first and second nanostructures prior to forming the first opening, wherein the top surface of the second isolation member is exposed after the first opening is formed. In yet another embodiment, the dielectric pad is deposited on the top surface of the second isolation member. In yet another embodiment, extending the first opening further includes removing a first portion of the second isolation member, wherein the first isolation member is located on the sidewall of the second portion of the second isolation member.

[0070] In an embodiment, a method for forming a semiconductor device includes: forming a first nanostructure; forming a first internal spacer, wherein the first internal spacer is located on the top surface of the first nanostructure; forming a first isolation member below the first nanostructure; forming a first dielectric member, wherein the first isolation member is located on the sidewall of the first dielectric member; growing a first source / drain region above the first dielectric member, wherein the first nanostructure and the first internal spacer are located on the sidewall of the first source / drain region; forming a first opening by removing a first portion of the first nanostructure and a first portion of the first internal spacer, wherein a second portion of the first nanostructure and a second portion of the first internal spacer remain on the sidewall of the first source / drain region, and wherein the first isolation member... The top surface of the first nanostructure is exposed by a first opening; a dielectric pad is deposited in the first opening, wherein the dielectric pad is located on the sidewalls of the second portion of the first nanostructure, the sidewalls of the second portion of the first internal spacer, and the top surface of the first isolation member; the first opening is extended by removing the first portion of the dielectric pad and the first portion of the first isolation member, wherein the second portion of the dielectric pad remains on the sidewalls of the second portion of the first nanostructure and the second portion of the first internal spacer, and wherein the second portion of the first isolation member remains on the sidewall of the first dielectric member; and a second isolation member is deposited in the first opening, wherein the second isolation member is located on the sidewalls of the second portion of the dielectric pad, and wherein the second isolation member is located on the sidewalls of the second portion of the first isolation member. In an embodiment, the second portion of the first internal spacer is thinner than the second portion of the first isolation member. In an embodiment, the second portion of the dielectric pad is located on the top surface of the second portion of the first isolation member. In an embodiment, the method further includes: forming a second nanostructure before forming a first nanostructure, wherein a first insulating member is located between the first nanostructure and the second nanostructure; forming a second internal spacer, wherein the second internal spacer is located on the top surface of the second nanostructure; and growing a second source / drain region before forming a first dielectric member, wherein the second nanostructure and the second internal spacer are located on the sidewalls of the second source / drain region. In an embodiment, extending the first opening further includes removing a first portion of the second nanostructure and a first portion of the second internal spacer, wherein a second portion of the second nanostructure and a second portion of the second internal spacer remain on the sidewalls of the second source / drain region. In an embodiment, the second portion of the first internal spacer is thinner than the second portion of the second internal spacer.

[0071] Some embodiments of this application provide a semiconductor device, including: a first source / drain region; a first nanostructure located on a first sidewall of the first source / drain region; a first gate structure located around the first nanostructure; a first internal spacer located on the first sidewall of the first source / drain region, wherein the first internal spacer is located between the first gate structure and the first source / drain region; a second internal spacer located on a second sidewall of the first source / drain region, wherein the second sidewall is opposite to the first sidewall; a first dielectric pad located on the sidewall of the second internal spacer, wherein the second internal spacer is located between the first dielectric pad and the first source / drain region; and a first isolation member located on the sidewall of the first dielectric pad, wherein the first dielectric pad is located between the first isolation member and the second internal spacer.

[0072] In some embodiments, the first dielectric pad comprises a first material, wherein the first isolation member comprises a second material different from the first material. In some embodiments, the semiconductor device further comprises a second isolation member located below the second internal spacer, wherein the first dielectric pad is located on the top surface of the second isolation member. In some embodiments, the second isolation member and the second internal spacer comprise the same material. In some embodiments, the second internal spacer is thinner than the first internal spacer. In some embodiments, the semiconductor device further comprises: a second source / drain region located below the first source / drain region; and a third internal spacer located between the second source / drain region and the first isolation member, wherein the second internal spacer is thinner than the third internal spacer. In some embodiments, the semiconductor device further comprises: a second isolation member located below the first source / drain region, wherein the first isolation member extends into the second isolation member; and a second dielectric pad located on the top surface of the second isolation member, wherein the first dielectric pad and the second dielectric pad comprise the same first material different from the second material of the first isolation member, and wherein the first isolation member is located on the top surface and sidewalls of the second dielectric pad.

[0073] Other embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first nanostructure and forming a second nanostructure over the first nanostructure; growing a first source / drain region and a second source / drain region, wherein the first nanostructure is located on a sidewall of the first source / drain region, and wherein the second nanostructure is located on a sidewall of the second source / drain region; forming a first opening by removing a first portion of the second nanostructure, wherein a second portion of the second nanostructure remains on the sidewall of the second source / drain region; depositing a dielectric pad in the first opening, wherein... A dielectric pad is located on the sidewall of the second portion of the second nanostructure; the first opening is extended by removing a first portion of the dielectric pad and a first portion of the first nanostructure, wherein a second portion of the dielectric pad remains on the sidewall of the second portion of the second nanostructure, and wherein a second portion of the first nanostructure remains on the sidewall of the first source / drain region; and a first isolation member is deposited in the first opening, wherein the first isolation member is located on the sidewall of the second portion of the dielectric pad, and wherein the first isolation member is located on the sidewall of the second portion of the first nanostructure.

[0074] In some embodiments, the second portion of the first nanostructure has a greater thickness than the second portion of the second nanostructure. In some embodiments, the dielectric pad and the first isolation member comprise different materials. In some embodiments, the dielectric pad is located between the second portion of the second nanostructure and the first isolation member. In some embodiments, the method further includes forming a second isolation member between the first nanostructure and the second nanostructure before forming the first opening, wherein the top surface of the second isolation member is exposed after the first opening is formed. In some embodiments, the dielectric pad is deposited on the top surface of the second isolation member. In some embodiments, extending the first opening further includes removing a first portion of the second isolation member, wherein the first isolation member is located on the sidewall of the second portion of the second isolation member.

[0075] Some embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a first nanostructure; forming a first internal spacer, wherein the first internal spacer is located on the top surface of the first nanostructure; forming a first isolation member below the first nanostructure; forming a first dielectric member, wherein the first isolation member is located on the sidewall of the first dielectric member; growing a first source / drain region above the first dielectric member, wherein the first nanostructure and the first internal spacer are located on the sidewall of the first source / drain region; forming a first opening by removing a first portion of the first nanostructure and a first portion of the first internal spacer, wherein a second portion of the first nanostructure and a second portion of the first internal spacer remain on the sidewall of the first source / drain region, and wherein the top surface of the first isolation member is formed by the first internal spacer. A first opening is exposed; a dielectric pad is deposited in the first opening, wherein the dielectric pad is located on the sidewall of the second portion of the first nanostructure, the sidewall of the second portion of the first internal spacer, and the top surface of the first isolation member; the first opening is extended by removing the first portion of the dielectric pad and the first portion of the first isolation member, wherein a second portion of the dielectric pad remains on the sidewall of the second portion of the first nanostructure and the sidewall of the second portion of the first internal spacer, and wherein a second portion of the first isolation member remains on the sidewall of the first dielectric member; and a second isolation member is deposited in the first opening, wherein the second isolation member is located on the sidewall of the second portion of the dielectric pad, and wherein the second isolation member is located on the sidewall of the second portion of the first isolation member.

[0076] In some embodiments, the second portion of the first internal spacer is thinner than the second portion of the first isolation member. In some embodiments, the second portion of the dielectric pad is located on the top surface of the second portion of the first isolation member. In some embodiments, the method further includes: forming a second nanostructure before forming the first nanostructure, wherein the first isolation member is located between the first nanostructure and the second nanostructure; forming a second internal spacer, wherein the second internal spacer is located on the top surface of the second nanostructure; and growing a second source / drain region before forming the first dielectric member, wherein the second nanostructure and the second internal spacer are located on the sidewalls of the second source / drain region. In some embodiments, extending the first opening further includes removing a first portion of the second nanostructure and a first portion of the second internal spacer, wherein a second portion of the second nanostructure and a second portion of the second internal spacer remain on the sidewalls of the second source / drain region. In some embodiments, the second portion of the first internal spacer is thinner than the second portion of the second internal spacer.

[0077] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: a first source / drain region; a first nanostructure on a first sidewall of the first source / drain region; a first gate structure around the first nanostructure; a first inner spacer on the first sidewall of the first source / drain region, wherein the first inner spacer is between the first gate structure and the first source / drain region; a second inner spacer on a second sidewall of the first source / drain region, wherein the second sidewall is opposite the first sidewall; a first dielectric liner on a sidewall of the second inner spacer, wherein the second inner spacer is between the first dielectric liner and the first source / drain region; and a first isolation feature on a sidewall of the first dielectric liner, wherein the first dielectric liner is between the first isolation feature and the second inner spacer.

2. The semiconductor device of claim 1, wherein, The first dielectric liner comprises a first material, wherein the first isolation feature comprises a second material different from the first material.

3. The semiconductor device of claim 1, further comprising a second isolation component located below the second interior spacer, wherein, The first dielectric liner is on a top surface of the second isolation feature.

4. The semiconductor device of claim 3, wherein, The second isolation feature and the second inner spacer comprise a same material.

5. The semiconductor device of claim 1, wherein, The second inner spacer is thinner than the first inner spacer.

6. The semiconductor device of claim 1, further comprising: a second source / drain region below the first source / drain region; and a third inner spacer between the second source / drain region and the first isolation feature, wherein the second inner spacer is thinner than the third inner spacer.

7. The semiconductor device of claim 1, further comprising: a second isolation feature below the first source / drain region, wherein the first isolation feature extends into the second isolation feature; and a second dielectric liner on a top surface of the second isolation feature, wherein the first dielectric liner and the second dielectric liner comprise a same first material different from a second material of the first isolation feature, and wherein the first isolation feature is on a top surface and a sidewall of the second dielectric liner.

8. A method of forming a semiconductor device, the method comprising: forming a first nanostructure and a second nanostructure above the first nanostructure; growing a first source / drain region and a second source / drain region, wherein the first nanostructure is on a sidewall of the first source / drain region, and wherein the second nanostructure is on a sidewall of the second source / drain region; forming a first opening by removing a first portion of the second nanostructure, wherein a second portion of the second nanostructure remains on the sidewall of the second source / drain region; depositing a dielectric liner in the first opening, wherein the dielectric liner is on a sidewall of the second portion of the second nanostructure; and forming a second opening by removing a third portion of the second nanostructure, wherein a fourth portion of the second nanostructure remains on the sidewall of the second source / drain region. extending the first opening by removing a first portion of the dielectric liner and a first portion of the first nanostmcture, wherein a second portion of the dielectric liner remains on the sidewalls of the second portion of the second nanostmcture, and wherein a second portion of the first nanostmcture remains on the sidewalls of the first source / drain region; and depositing a first spacer component in the first opening, wherein the first spacer component is on sidewalls of the second portion of the dielectric liner, and wherein the first spacer component is on sidewalls of the second portion of the first nanostmcture.

9. The method of claim 8, wherein, the second portion of the first nanostmcture has a greater thickness than the second portion of the second nanostmcture.

10. A method of forming a semiconductor device, the method comprising: forming a first nanostmcture; forming a first internal spacer, wherein the first internal spacer is on a top surface of the first nanostmcture; forming a first spacer component under the first nanostmcture; forming a first dielectric component, wherein the first spacer component is on sidewalls of the first dielectric component; growing a first source / drain region over the first dielectric component, wherein the first nanostmcture and the first internal spacer are on sidewalls of the first source / drain region; forming a first opening by removing a first portion of the first nanostmcture and a first portion of the first internal spacer, wherein a second portion of the first nanostmcture and a second portion of the first internal spacer remain on the sidewalls of the first source / drain region, and wherein a top surface of the first spacer component is exposed by the first opening; depositing a dielectric liner in the first opening, wherein the dielectric liner is on sidewalls of the second portion of the first nanostmcture, sidewalls of the second portion of the first internal spacer, and the top surface of the first spacer component; extending the first opening by removing a first portion of the dielectric liner and a first portion of the first spacer component, wherein a second portion of the dielectric liner remains on the sidewalls of the second portion of the first nanostmcture and the sidewalls of the second portion of the first internal spacer, and wherein a second portion of the first spacer component remains on the sidewalls of the first dielectric component; and depositing a second spacer component in the first opening, wherein the second spacer component is on sidewalls of the second portion of the dielectric liner, and wherein the second spacer component is on sidewalls of the second portion of the first spacer component.

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