FDSOI image sensor and manufacturing method thereof

Abstract

The invention discloses an FDSOI image sensor, a pixel unit structure comprises an FDSOI transistor formed on an SOI layer and a photodiode formed in a bottom semiconductor substrate, and the photodiode comprises a photosensitive well region. The photodiode is located right below the FDSOI transistor and extends to the outer side of the formation area of the FDSOI transistor; a first extension end is arranged on the outer side of the source region and / or the drain region of the FDSOI transistor, and the first extension end is used for enabling incident light to enter the photosensitive well region from the front surface; a plurality of shallow STIs are formed in the first extension end, and each shallow STI penetrates through the SOI layer and is in contact with the insulating buried layer at the bottom; and each shallow STI forms a reflection structure for reflecting the bottom reflection light reflected by the insulating buried layer, and is used for increasing the luminous flux of the incident light entering the photosensitive well region. The invention further discloses a manufacturing method of the FDSOI image sensor. According to the invention, the utilization rate of incident light can be increased, the luminous flux can be increased, the response sensitivity of light can be improved, and the area of the device can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to an FDSOI image sensor; this invention also relates to a method for manufacturing an FDSOI image sensor. Background Technology

[0002] Image sensors are widely used in various fields. Image sensors have undergone significant advancements in pixel size reduction, performance improvement, and structural optimization. With advancements in manufacturing technology, image sensors have shrunk to meet increasingly demanding requirements. In some advanced applications, such as bioimaging, super-resolution microscopy is required. Recently, an 8K imaging system was applied to endoscopic surgery. To achieve high resolution, the pixel size of image sensors continues to shrink. For example... Figure 1 The diagram shown is an equivalent circuit diagram of the pixel unit circuit of an existing 4T CMOS image sensor. In order to achieve better noise performance, the existing CMOS image sensor (CIS) uses a source follower and an addressing transistor M4 composed of a photodiode PD1, a transfer transistor M1, a floating active region FD, a reset transistor M2, and a driver M3. Figure 1 In this designation, the transfer transistor M1 is also denoted by TX, the reset transistor M2 by RST, the driver M3 by SF, and the addressing transistor M4 by RS. However, existing 4T CMOS image sensors have poor fill factor because signal collection, transmission, and readout require four transistors in different areas. As resolution requirements increase, more pixel units need to be implemented within a unit area, and this method of separating signal sensing, amplification, and readout is severely limited by the large unit area.

[0003] To improve gate control capabilities, LIQIAO LIU et al. utilized the characteristics of fully depleted silicon-on-insulator (FDSOI), such as the ability to achieve sensitive back voltage control of the device and the inherent buried oxide (BOX) barrier function, to develop an FDSOI-based photodiode. This photodiode converts light signals into electrical signals. Utilizing the back gate formed by the silicon oxide (BOX) at its bottom, the threshold voltage (Vth) and current can be adjusted, thus enabling light collection and signal amplification within a single transistor. During illumination, the charge generated by photoelectric activity is stored under the BOX, altering the MOSFET's threshold voltage and on-state drain current. When a pixel is selected, a gate voltage is applied and the pixel's drain current is read out, enabling the reading of the light signal. This allows for the sensing, amplification, and reading of large-capacity photoelectric signals within a single transistor, achieving higher pixel capacity in a limited area. However, the application of optical structures based on the FDSOI structure has two limitations. First, because the structure includes a gate, conventional back-illuminated structures cannot be used to increase the area of ​​the photodiode. Second, when using front-illuminated processes, the gate needs to be shielded to avoid being exposed to light. Furthermore, because the structure itself contains a silicon oxide layer, it is prone to reflection, which reduces the light response. To prevent the gate's influence, high luminous flux is mainly achieved by increasing the area at one end. The optical sensitivity of this FDSOI-based structure is strongly dependent on the area; as the photosensitive length (fixed width) increases, the photosensitive time decreases, which limits the application of existing photodiodes with corresponding sensitivity.

[0004] like Figure 2A The diagram shown is a top view of the pixel unit structure of an existing FDSOI image sensor; as shown... Figure 2B The diagram shown is a cross-sectional schematic of the pixel unit structure of an existing FDSOI image sensor. Figure 2B It is along Figure 2A The cross-sectional view at the dashed line AA' in the figure; taking the FDSOI transistor as an NMOS as an example, the pixel unit structure of the existing FDSOI image sensor includes:

[0005] An FDSOI transistor is formed on an SOI layer 109. The FDSOI transistor includes a gate structure, a source region 104, and a drain region 105. The gate structure is formed on the top surface of the SOI layer 109. The source region 104 and the drain region 105 are both heavily N-type doped and self-aligned on both sides of the gate structure. The SOI layer 109 covered by the gate structure forms the channel region of the FDSOI transistor.

[0006] A photodiode is formed in a bottom semiconductor substrate 101, the photodiode including a P-type photosensitive trap region 107 formed in the top region of the bottom semiconductor substrate 101. The photosensitive trap region 107 and the PN junction formed by the N-type doped bottom semiconductor substrate 101 at the bottom constitute the photodiode. The photodiode is located directly below the FDSOI transistor and extends to the outside of the formation region 101a of the FDSOI transistor.

[0007] A buried oxide layer 108 is spaced between the SOI layer 109 and the bottom semiconductor substrate 101.

[0008] A first extension 106 is provided on the outer side of the drain area 105. The first extension 106 is used to allow incident light 113 to enter the photosensitive trap area 107 from the front.

[0009] like Figure 2B As shown, the buried oxide layer 108 reflects the incident light 113, forming bottom-reflected light 114. Light 115 is light that enters the photosensitive trap region 107 directly without reflection; the bottom-reflected light 114 cannot enter the photosensitive trap region 107. Therefore, the luminous flux of the incident light 113 entering the photosensitive trap region 107 is reduced.

[0010] STI102 is formed on the periphery of the FDSOI transistor. The STI102 passes through the SOI layer 109 and the buried oxide layer 108 and enters the bottom semiconductor substrate 101. The bottom surface of the photosensitive trap region 107 is located below the bottom surface of the first STI102.

[0011] A P-type heavily doped substrate lead-out region 111 is formed on the surface region of the photosensitive trap region 107 outside the formation region 101a of the FDSOI transistor, and the substrate lead-out region 111 is connected to the substrate electrode.

[0012] The substrate lead-out region 111 is located in the hybrid substrate region 101b. In the hybrid substrate region 101b, the top of the bottom semiconductor substrate 101 does not have the buried oxide layer 108 and the SOI layer 109. The top surface of the bottom semiconductor substrate 101 is directly flush with the top surface of the SOI layer 109 outside the hybrid substrate region 101b. Alternatively, a second epitaxial layer can be formed on the top surface of the bottom semiconductor substrate 101, and the top surface of the second epitaxial layer is flush with the top surface of the SOI layer 109 outside the hybrid substrate region 101b.

[0013] A raised epitaxial layer is formed on the top of the source region 104 and the top of the drain region 105, respectively, and the first extension end 106 is located outside the corresponding raised epitaxial layer. Figure 2B As shown, the source region 104 is formed by stacking a doped region 104a formed in the SOI layer and a raised epitaxial layer 104b on top, and the drain region 105 is formed by stacking a doped region 105a formed in the SOI layer and a raised epitaxial layer 105b on top.

[0014] The gate structure includes a gate dielectric layer 110 and a gate conductive material layer 103 stacked sequentially.

[0015] The top of the gate conductive material layer 103 is connected to the gate composed of the front metal layer through a contact hole 118, the top of the source region 104 is connected to the source composed of the front metal layer through a contact hole 118, and the top of the drain region 105 is connected to the drain composed of the front metal layer through a contact hole 118.

[0016] Depend on Figure 2B As shown, a shielding layer 112 composed of a front metal layer is also formed in the FDSOI transistor. The shielding layer 112 forms the incident light 113 only on the top of the first extension end 106, and the other areas are blocked by the shielding layer 112 to prevent the incident light 113 from having an adverse effect on the FDSOI transistor.

[0017] Figure 2B The incident light 113 is incident perpendicularly. In reality, the incident light 113 can also be incident at an angle, such as... Figure 2C The diagram shown is a schematic of the pixel unit structure of an existing FDSOI image sensor when the incident light is obliquely incident. Figure 2C In this context, the incident light 113 is incident at an angle. The angled incident light is reflected by the BOX surface, reducing the luminous flux and thus reducing photosensitivity. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to provide an FDSOI image sensor that can increase the utilization rate of incident light, thereby increasing the light flux and improving the light response sensitivity, and thus enabling the reduction of device area. To this end, the present invention also provides a method for manufacturing an FDSOI image sensor.

[0019] To solve the above-mentioned technical problems, the pixel unit structure of the FDSOI image sensor provided by the present invention includes:

[0020] An FDSOI transistor is formed on an SOI layer. The FDSOI transistor includes a gate structure, a source region, and a drain region. The gate structure is formed on the top surface of the SOI layer. The source region and the drain region are both heavily doped with a first conductivity type and are self-aligned on both sides of the gate structure. The SOI layer covered by the gate structure forms the channel region of the FDSOI transistor.

[0021] A photodiode formed in a bottom semiconductor substrate, the photodiode including a photosensitive trap region of a second conductivity type formed in a top region of the bottom semiconductor substrate. The photodiode is located directly below the FDSOI transistor and extends outside the formation region of the FDSOI transistor.

[0022] An insulating buried layer separates the SOI layer from the bottom semiconductor substrate.

[0023] A first extension is provided on the outer side of the source region and / or the drain region. The first extension is used to allow incident light to enter the photosensitive trap region from the front. A plurality of shallow STIs are formed in the first extension. Each shallow STI passes through the SOI layer and contacts the bottom insulating buried layer. The insulating buried layer reflects the incident light and forms bottom reflected light. Each shallow STI forms a reflective structure that reflects the incident light and / or the bottom reflected light to increase the luminous flux of the incident light entering the photosensitive trap region.

[0024] A further improvement is that, on the top view, the shallow STIs are connected to form a grid structure. In the grid structure, the shallow STIs are surrounding the periphery of the SOI layer corresponding to each grid. The shallow STIs around the periphery of the grid will reflect the bottom reflected light entering the grid multiple times.

[0025] A further improvement is that STIs are formed on the periphery of the FDSOI transistor, the STIs penetrate the SOI layer and the insulating buried layer and enter the bottom semiconductor substrate, and the bottom surface of the photosensitive trap region is located below the bottom surface of the first STI.

[0026] A further improvement is that a second conductivity type heavily doped substrate lead-out region is formed in the surface region of the photosensitive trap region outside the formation region of the FDSOI transistor, and the substrate lead-out region is connected to the substrate electrode.

[0027] A further improvement is that the substrate lead-out region is located in the hybrid substrate region, in which the bottom semiconductor substrate does not have the buried insulating layer and the SOI layer on top, and the top surface of the bottom semiconductor substrate is directly flush with the top surface of the SOI layer outside the hybrid substrate region; or, a second epitaxial layer is formed on the top surface of the bottom semiconductor substrate, and the top surface of the second epitaxial layer is flush with the top surface of the SOI layer outside the hybrid substrate region.

[0028] A further improvement is that a raised epitaxial layer is formed on the top of the source region and the top of the drain region, respectively, and the first extension end is located on the outside of the corresponding raised epitaxial layer.

[0029] A further improvement is that the gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.

[0030] A further improvement is that the FDSOI transistor is an NMOS, with the first conductivity type being N-type and the second conductivity type being P-type; or, the FDSOI transistor is a PMOS, with the first conductivity type being P-type and the second conductivity type being N-type.

[0031] A further improvement is that, when the FDSOI transistor is a PMOS, the material of the SOI layer includes SiGe.

[0032] To solve the above-mentioned technical problems, the manufacturing method of the FDSOI image sensor provided by the present invention includes the following steps:

[0033] A semiconductor substrate is provided, wherein in the formation region of the FDSOI transistor, the semiconductor substrate has a superimposed structure of the bottom semiconductor substrate, the buried insulating layer and the SOI layer; a hard mask layer formed by superimposing a first oxide layer and a second nitride layer is sequentially formed on the surface of the semiconductor substrate.

[0034] STI is formed in the semiconductor substrate.

[0035] Define the formation region of the shallow STI.

[0036] Using the first oxide layer as a stop layer, the second nitride layer in the shallow STI formation region is etched to form the first opening.

[0037] Using the SOI layer as a stop layer, the first oxide layer at the bottom of the first opening is etched to extend the first opening downwards.

[0038] Using the hard mask layer with the first opening as a mask, the SOI layer at the bottom of the first opening is oxidized to form the shallow STI layer.

[0039] A further improvement is that the semiconductor substrate further includes a hybrid substrate region in which the top of the bottom semiconductor substrate does not have the buried insulating layer and the SOI layer, and the top surface of the bottom semiconductor substrate is directly flush with the top surface of the SOI layer outside the hybrid substrate region; or, a second epitaxial layer is formed on the top surface of the bottom semiconductor substrate, and the top surface of the second epitaxial layer is flush with the top surface of the SOI layer outside the hybrid substrate region.

[0040] A further improvement is that the FDSOI transistor is an NMOS or a PMOS, or both the NMOS and the PMOS are integrated on the semiconductor substrate.

[0041] A further improvement is that the SOI layer in the PMOS formation region is made of SiGe.

[0042] A further improvement is that the material of the insulating buried layer includes an oxide layer.

[0043] A further improvement is that the material of the bottom semiconductor substrate includes Si, and the material of the SOI layer outside the formation region of the PMOS includes Si.

[0044] This invention features a specially designed structure for the first extension end outside the source and / or drain regions of the FDSOI image sensor. Unlike existing structures that directly use the SOI layer, this invention adds multiple shallow STI layers that only penetrate the SOI layer. These shallow STI layers form a reflective structure that further reflects the bottom reflected light formed by the incident light reflected from the bottom insulating buried layer. This allows the bottom reflected light to be further reflected and then incident on the photosensitive trap region, thereby increasing the luminous flux of the incident light entering the photosensitive trap region. Therefore, this invention can increase the utilization rate of the incident light, thereby increasing the luminous flux and improving the light response sensitivity, and further reducing the device area. Attached Figure Description

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0046] Figure 1 This is an equivalent circuit diagram of the pixel unit circuit of an existing 4T CMOS image sensor;

[0047] Figure 2A This is a top view of the pixel unit structure of an existing FDSOI image sensor.

[0048] Figure 2B This is a cross-sectional schematic diagram of the pixel unit structure of an existing FDSOI image sensor;

[0049] Figure 2C This is a schematic diagram of the pixel unit structure of an existing FDSOI image sensor when the incident light is obliquely incident.

[0050] Figure 3A This is a top view schematic diagram of the pixel unit structure of the FDSOI image sensor according to an embodiment of the present invention;

[0051] Figure 3B This is a cross-sectional structural diagram of the pixel unit structure of the FDSOI image sensor according to an embodiment of the present invention;

[0052] Figure 3C This is a schematic diagram of the pixel unit structure of the FDSOI image sensor according to an embodiment of the present invention when the incident light is obliquely incident;

[0053] Figures 4A-4D This is a schematic diagram of the device structure in each step of the manufacturing method of the FDSOI image sensor according to an embodiment of the present invention. Detailed Implementation

[0054] like Figure 3A The diagram shown is a top view of the pixel unit structure of the FDSOI image sensor according to an embodiment of the present invention; as shown... Figure 3B The diagram shown is a cross-sectional view of the pixel unit structure of the FDSOI image sensor according to an embodiment of the present invention. Figure 3B It is along Figure 3A A cross-sectional view at the dashed line AA' in the figure; the pixel unit structure of the FDSOI image sensor in this embodiment of the invention includes:

[0055] An FDSOI transistor is formed on an SOI layer 209. The FDSOI transistor includes a gate structure, a source region 204, and a drain region 205. The gate structure is formed on the top surface of the SOI layer 209. The source region 204 and the drain region 205 are both heavily doped with a first conductivity type and are self-aligned on both sides of the gate structure. The SOI layer 209 covered by the gate structure forms the channel region of the FDSOI transistor.

[0056] A photodiode is formed in a bottom semiconductor substrate 201, the photodiode including a photosensitive well region 207 of a second conductivity type formed in the top region of the bottom semiconductor substrate 201. The photodiode is located directly below the FDSOI transistor and extends to the outside of the formation region 201a of the FDSOI transistor. The photosensitive well region 207 and the PN junction formed by the bottom of the bottom semiconductor substrate 201, which is doped with a first conductivity type, constitute the photodiode. The bottom of the photosensitive well region 207 may also include an intrinsically doped region, and the photodiode is a PIN junction.

[0057] An insulating buried layer 208 is spaced between the SOI layer 209 and the bottom semiconductor substrate 201.

[0058] A first extension end 206 is provided on the outer side of the source region 204 and / or the drain region 205. Figure 3A In this embodiment, the first extension end 206 is located outside the drain region 205. In other embodiments, the first extension end 206 may also be located outside the drain region 205.

[0059] The first extension end 206 is used to allow incident light 213 to enter the photosensitive trap region 207 from the front; a plurality of shallow STI 301 are formed in the first extension end 206, each of the shallow STI 301 passing through the SOI layer 209 and contacting the bottom insulating buried layer 208; the insulating buried layer 208 reflects the incident light 213 and forms bottom reflected light 214, and each of the shallow STI 301 forms a reflective structure that reflects the incident light 213 and / or the bottom reflected light 214, so as to increase the light flux of the incident light 213 into the photosensitive trap region 207. Figure 3B As shown, light 215 is light that enters the photosensitive trap region 207 directly without reflection; light 215a is light that enters the photosensitive trap region 207 after being reflected by the shallow STI301. Figure 2B Compared to the existing structure, ray 215a is an additional incident ray.

[0060] In this embodiment of the invention, on the top view, each of the shallow STI301 layers is connected to form a grid structure. In the grid structure, the shallow STI301 layers surround the periphery of the SOI layer 209 corresponding to each grid. The shallow STI301 layers around the periphery of the grid will reflect the bottom reflected light 214 entering the grid multiple times. Figure 3A In this embodiment, the grid is a square structure. In other embodiments, the grid may also be other shapes.

[0061] In this embodiment of the invention, STI202 is formed on the periphery of the FDSOI transistor. The STI202 passes through the SOI layer 209 and the insulating buried layer 208 and enters the bottom semiconductor substrate 201. The bottom surface of the photosensitive trap region 207 is located below the bottom surface of the first STI202.

[0062] In this embodiment of the invention, a substrate lead-out region 211 of the second conductivity type is formed in the surface region of the photosensitive trap region 207 outside the formation region 201a of the FDSOI transistor, and the substrate lead-out region 211 is connected to the substrate electrode.

[0063] The substrate lead-out region 211 is located in the hybrid substrate region 201b. In the hybrid substrate region 201b, the bottom semiconductor substrate 201 does not have the buried insulating layer 208 and the SOI layer 209 on top, and the top surface of the bottom semiconductor substrate 201 is directly flush with the top surface of the SOI layer 209 outside the hybrid substrate region 201b. In other embodiments, a second epitaxial layer may be formed on the top surface of the bottom semiconductor substrate 201, and the top surface of the second epitaxial layer is flush with the top surface of the SOI layer 209 outside the hybrid substrate region 201b.

[0064] A raised epitaxial layer is formed on the top of the source region 204 and the top of the drain region 205, respectively, and the first extension end 206 is located outside the corresponding raised epitaxial layer. Figure 3B As shown, the source region 204 is formed by superimposing a doped region 204a formed in the SOI layer and a top raised epitaxial layer 204b, and the drain region 205 is formed by superimposing a doped region 205a formed in the SOI layer and a top raised epitaxial layer 205b.

[0065] The gate structure includes a gate dielectric layer 210 and a gate conductive material layer 203 stacked sequentially. In this embodiment of the invention, the gate conductive material layer 203 is a metal gate, and the gate dielectric layer 210 is made of a high dielectric constant material or silicon dioxide. In other embodiments, the gate conductive material layer 203 may also be a polysilicon gate.

[0066] The top of the gate conductive material layer 203 is connected to the gate composed of the front metal layer through a contact hole 218, the top of the source region 204 is connected to the source composed of the front metal layer through a contact hole 218, and the top of the drain region 205 is connected to the drain composed of the front metal layer through a contact hole 218.

[0067] Depend on Figure 3B As shown, a shielding layer 212 composed of a front metal layer is also formed in the FDSOI transistor. The shielding layer 212 forms the incident light 213 only on the top of the first extension end 206, and the other areas are blocked by the shielding layer 212 to prevent the incident light 213 from having an adverse effect on the FDSOI transistor.

[0068] Depend on Figure 3BAs shown, after the incident light 213 is incident, only a portion of the light 215 directly enters the photosensitive trap region 207, while the remaining light is reflected by the insulating buried layer 208 to form bottom reflected light 214. In this embodiment of the invention, the added shallow STI 301 further reflects the bottom reflected light 214, causing it to reverse and form light 215a that enters the photosensitive trap region 207. Therefore, this increases the luminous flux of the incident light 213 entering the photosensitive trap region 207.

[0069] Figure 3B The incident light 213 is incident perpendicularly. In reality, the incident light 213 can also be incident at an angle, such as... Figure 3C The diagram shown is a schematic of the pixel unit structure of the FDSOI image sensor in an embodiment of the present invention when the incident light is obliquely incident; when the incident light 213 is obliquely incident, the shallow STI 301 will also directly reflect the incident light 213 and form light ray 215a which enters the photosensitive trap region 207.

[0070] In this embodiment of the invention, the FDSOI transistor is an NMOS, with an N-type first conductivity type and a P-type second conductivity type. In other embodiments, the FDSOI transistor can also be a PMOS, with a P-type first conductivity type and an N-type second conductivity type. When the FDSOI transistor is a PMOS, the material of the SOI layer 209 includes SiGe.

[0071] Figure 3B The following explanation uses an NMOS transistor as an example of an FDSOI transistor. Figure 3B It is known that the photosensitive trap region 207 will generate photoelectrons 216 and photogenerated holes 217 under optical action. The photogenerated holes 217 will flow out under the action of the substrate electrode; the photoelectrons 216 will be stored at the bottom of the insulating buried layer 208 at the bottom of the FDSOI transistor, thus changing the threshold voltage of the channel region. In this way, the drain current of the FDSOI transistor in the on state will change according to the collected photoelectrons 216, thereby realizing image sensing.

[0072] This invention provides a special design for the structure of the first extension end 206 outside the source region 204 and / or drain region 205 of the FDSOI image sensor. Unlike existing structures that directly use the SOI layer 209, this invention adds multiple shallow STI 301 layers that only pass through the SOI layer 209. These shallow STI 301 layers form a reflective structure that further reflects the bottom reflected light 214 formed by the incident light 213 reflected from the bottom insulating buried layer 208. This allows the bottom reflected light 214 to be further reflected and then incident into the photosensitive trap region 207, thereby increasing the light flux of the incident light 213 into the photosensitive trap region 207. Therefore, this invention increases the utilization rate of the incident light 213, thereby increasing the light flux and improving the light response sensitivity, and further reducing the device area.

[0073] like Figures 4A to 4D The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the FDSOI image sensor according to an embodiment of the present invention. The manufacturing method of the FDSOI image sensor according to an embodiment of the present invention includes the following steps:

[0074] like Figure 4A As shown, a semiconductor substrate is provided. In the formation region 201a of the FDSOI transistor, the semiconductor substrate has a superimposed structure of the bottom semiconductor substrate 201, the buried insulating layer 208 and the SOI layer 209. A hard mask layer formed by superimposing a first oxide layer 302 and a second nitride layer 303 is sequentially formed on the surface of the semiconductor substrate.

[0075] In the method of this embodiment, the semiconductor substrate further includes a hybrid substrate region 201b. In the hybrid substrate region 201b, the top of the bottom semiconductor substrate 201 does not have the buried insulating layer 208 and the SOI layer 209, and the top surface of the bottom semiconductor substrate 201 is directly flush with the top surface of the SOI layer 209 outside the hybrid substrate region 201b. In other embodiments, a second epitaxial layer may be formed on the top surface of the bottom semiconductor substrate 201, and the top surface of the second epitaxial layer is flush with the top surface of the SOI layer 209 outside the hybrid substrate region 201b.

[0076] In the method of this embodiment of the invention, the FDSOI transistor is an NMOS or a PMOS, or both the NMOS and the PMOS are integrated on the semiconductor substrate simultaneously. Therefore Figure 4A In, including the NMOS formation region 201a, i.e. Figure 3BThe FDSOI transistor formation region 201a and the PMOS formation region 201c are shown in the diagram. In the PMOS formation region, the SOI layer 209 is made of SiGe. The SOI layer in the PMOS formation region 201c is indicated by the designation 209a.

[0077] The material of the insulating buried layer 208 includes an oxide layer.

[0078] The bottom semiconductor substrate 201 is made of Si, and the SOI layer 209a outside the PMOS formation region is also made of Si.

[0079] like Figure 4A As shown, an STI202 is formed in the semiconductor substrate. The steps for forming the STI202 include:

[0080] Photolithography defines the formation area of ​​the STI202.

[0081] The second nitride layer 303 and the first oxide layer 302 are etched sequentially to transfer the pattern defined in the previous photolithography step downwards.

[0082] Then, using the patterned second nitride layer 303 and the first oxide layer 302 as a mask, the semiconductor substrate is etched to form shallow trenches.

[0083] The shallow trenches are then filled with an oxide layer and chemical mechanical polishing is performed to remove the oxide layer outside the shallow trenches, resulting in the STI202 consisting only of an oxide layer filled in the shallow trenches.

[0084] like Figure 4B As shown, the formation region of the shallow STI301 is defined. In the method of this embodiment of the invention, the formation region of the shallow STI301 is defined by a photoresist pattern formed by a photolithography process.

[0085] like Figure 4B As shown, the second nitride layer 303 in the shallow STI301 formation region is etched to form the first opening 304, with the first oxide layer 302 as the stop layer.

[0086] like Figure 4C As shown, the first oxide layer 302 at the bottom of the first opening 304 is etched using the SOI layer 209 as a stop layer, causing the first opening 304 to extend downward.

[0087] like Figure 4D As shown, the SOI layer 209 at the bottom of the first opening 304 is oxidized using the hard mask layer having the first opening 304 as a mask to form the shallow STI301.

[0088] After the shallow STI301 layer is formed, the FDSOI image sensor can be manufactured using existing methods.

[0089] This invention implements a structural and process integration method for increasing single-end luminous flux using a shallow trench isolation (SSTI) mesh structure. By forming a shallower isolation trench after completing a deep shallow trench isolation structure, a mesh-like silicon dioxide layer is formed in the photosensitive area. Multiple reflections through the mesh create a diffuse reflection structure. This results in multiple reflections of light within a limited area, maximizing the utilization of incident light. By increasing luminous flux, the light response sensitivity is improved, thereby enabling a reduction in the area of ​​the FDSOI-based optoelectronic structure.

[0090] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An FDSOI image sensor, characterized in that, The pixel unit structure comprises: An FDSOI transistor formed on an SOI layer, the FDSOI transistor comprising a gate structure formed on a top surface of the SOI layer, a source region and a drain region both having a first conductive type and being self-aligned and formed on both sides of the gate structure; the SOI layer covered by the gate structure constituting a channel region of the FDSOI transistor; A photodiode formed in a bottom semiconductor substrate, the photodiode comprising a light-sensing well region of a second conductive type formed in a top region of the bottom semiconductor substrate; the photodiode being located directly below the FDSOI transistor and extending to outside of a formation region of the FDSOI transistor; The SOI layer and the bottom semiconductor substrate are separated by an insulating buried layer; The source region and / or the drain region have a first extension end outside thereof, the first extension end being used for incident light to be incident from a front surface into the light-sensing well region; a plurality of shallow STIs are formed in the first extension end, each of the shallow STIs penetrating through the SOI layer and contacting the insulating buried layer; the insulating buried layer reflects the incident light to form bottom reflected light, and each of the shallow STIs forms a reflecting structure for reflecting the incident light and / or the bottom reflected light, so as to increase a light flux of the incident light into the light-sensing well region.

2. The FDSOI image sensor of claim 1, wherein: In a top view, the shallow STIs are connected to form a grid structure, in which each of the grids is surrounded by the shallow STIs on a periphery thereof, and the shallow STIs on the periphery of the grid reflect the bottom reflected light multiple times when the bottom reflected light enters the grid.

3. The FDSOI image sensor of claim 1, wherein: A periphery of the FDSOI transistor is formed with an STI, the STI penetrating through the SOI layer, the insulating buried layer and into the bottom semiconductor substrate, and a bottom surface of the light-sensing well region is located below a bottom surface of the first STI.

4. The FDSOI image sensor of claim 3, wherein: A substrate drawing-out region of a second conductive type is formed in a surface region of the light-sensing well region outside of the formation region of the FDSOI transistor, and the substrate drawing-out region is connected to a substrate electrode.

5. The FDSOI image sensor of claim 4, wherein: The substrate drawing-out region is located in a mixed substrate region in which a top of the bottom semiconductor substrate is free of the insulating buried layer and the SOI layer, and a top surface of the bottom semiconductor substrate is directly flat with a top surface of the SOI layer outside of the mixed substrate region; or, a second epitaxial layer is formed on the top surface of the bottom semiconductor substrate, and a top surface of the second epitaxial layer is flat with the top surface of the SOI layer outside of the mixed substrate region.

6. The FDSOI image sensor of claim 1, wherein: A top of the source region and a top of the drain region are respectively formed with a raised epitaxial layer, and the first extension end is located outside of the corresponding raised epitaxial layer.

7. The FDSOI image sensor of claim 1, wherein: The gate structure comprises a gate dielectric layer and a gate conductive material layer which are sequentially stacked.

8. The FDSOI image sensor of any one of claims 1 to 7, wherein: The FDSOI transistor is an NMOS, the first conductive type is N type, and the second conductive type is P type; or the FDSOI transistor is a PMOS, the first conductive type is P type, and the second conductive type is N type.

9. The FDSOI image sensor of claim 8, wherein: When the FDSOI transistor is a PMOS, the material of the SOI layer includes SiGe.

10. A method of manufacturing the FDSOI image sensor as claimed in claim 1, characterized in that, The method comprises the following steps: providing a semiconductor substrate, in the formation region of the FDSOI transistor, the semiconductor substrate has a superposition structure of the bottom semiconductor substrate, the insulating buried layer and the SOI layer; forming a hard mask layer formed by superposition of a first oxide layer and a second nitride layer on the surface of the semiconductor substrate in sequence; forming an STI in the semiconductor substrate; defining a formation region of the shallow STI; etching the second nitride layer of the formation region of the shallow STI with the first oxide layer as a stop layer to form a first opening; etching the first oxide layer at the bottom of the first opening with the SOI layer as a stop layer to extend the first opening downward; oxidizing the SOI layer at the bottom of the first opening with the hard mask layer with the first opening as a mask to form the shallow STI.

11. The method of fabricating an FDSOI image sensor of claim 10, wherein: The semiconductor substrate further comprises a mixed substrate region, in the mixed substrate region, the top of the bottom semiconductor substrate is free of the insulating buried layer and the SOI layer, and the top surface of the bottom semiconductor substrate is directly flush with the top surface of the SOI layer outside the mixed substrate region; or a second epitaxial layer is formed on the top surface of the bottom semiconductor substrate, and the top surface of the second epitaxial layer is flush with the top surface of the SOI layer outside the mixed substrate region.

12. The method of manufacturing an FDSOI image sensor of claim 11, wherein: The FDSOI transistor is an NMOS or a PMOS, or the NMOS and the PMOS are simultaneously integrated on the semiconductor substrate.

13. The FDSOI image sensor of claim 12, wherein: In the formation region of the PMOS, the material of the SOI layer is SiGe.

14. The FDSOI image sensor of claim 13, wherein: The material of the insulating buried layer includes an oxide layer.

15. The FDSOI image sensor of claim 10, wherein: The material of the bottom semiconductor substrate includes Si, and the material of the SOI layer outside the formation region of the PMOS includes Si. The material of the insulating buried layer includes an oxide layer. The material of the bottom semiconductor substrate includes Si, and the material of the SOI layer outside the formation region of the PMOS includes Si.

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