Shallow trench forming method and semiconductor structure

Abstract

The invention discloses a shallow trench forming method and a semiconductor structure. The shallow trench forming method comprises the steps of providing an initial semiconductor structure; the initial semiconductor structure comprises a substrate, an electric connection structure, a first isolation layer and a second isolation layer, the electric connection structure is embedded in the substrate, the first isolation layer is located between the electric connection structure and the substrate, and the second isolation layer is stacked on the surfaces of the electric connection structure, the first isolation layer and the substrate; patterning and etching the initial semiconductor structure to remove the first isolation layer and a second isolation layer area on the surface of the electric connection structure, and partially removing the first isolation layer to form an initial groove located at the top of the first isolation layer; forming a barrier layer with a groove etching window on the initial semiconductor structure with the initial groove, wherein the groove etching window stretches across the substrate, the first isolation layer and the electric connection structure; and forming a shallow trench at the trench etching window based on an etching process. According to the invention, the residual height of the first isolation layer in the shallow trench can be effectively reduced, the controllability is high, and the precision and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming shallow trenches and a semiconductor structure. Background Technology

[0002] In the shallow trench etching process, since the front-end process fills the deep trench with electrical interconnects and isolation layers, when shallow trench etching continues in this area, the isolation layers that are not easily etched will protect the sidewalls, leading to sidewall silicon pillar defects and causing a decrease in the electrical properties and reliability of the semiconductor structure.

[0003] Some existing technologies employ dry etching in steps (etching the isolation layer and silicon substrate separately) and interspersed with wet etching of the sidewall isolation layer. However, for multi-regional topographic structures with different heights and depths, the wet process cannot control the topographic structure of multiple regions, resulting in poor controllability and difficulty in meeting the precision requirements of semiconductor structures. Other existing technologies employ top top topographic structure taperization to reduce subsequent protection of the sidewalls. However, the taperization top topographic structure of deep trenches cannot be stably formed, resulting in a narrow process window and low reliability. Summary of the Invention

[0004] To address the problems of the prior art, this application provides a method for forming shallow trenches and a semiconductor structure. The technical solution is as follows: On the one hand, this application provides a method for forming shallow trenches, including: An initial semiconductor structure is provided; the initial semiconductor structure includes a substrate, an electrical interconnect structure, a first isolation layer and a second isolation layer, the electrical interconnect structure is embedded in the substrate, the first isolation layer is located between the electrical interconnect structure and the substrate, and the second isolation layer is stacked on the surface of the electrical interconnect structure, the first isolation layer and the substrate. The initial semiconductor structure is patterned and etched to remove the first isolation layer and the second isolation layer region on the surface of the electrical interconnect structure, and to partially remove the first isolation layer to form an initial groove located on top of the first isolation layer; A barrier layer with a trench etching window is formed on an initial semiconductor structure having the initial groove; the trench etching window spans the substrate, the first isolation layer, and the electrical interconnect. Shallow trenches are formed at the etching window of the trench using an etching process.

[0005] Further, forming a barrier layer with a trench etching window on the initial semiconductor structure having the initial groove includes: An initial barrier layer is formed on an initial semiconductor structure having the initial groove; the initial barrier layer is stacked on the substrate, the groove wall of the initial groove and the surface of the electrical interconnect structure, and at least partially fills the initial groove; The initial barrier layer is patterned to form a barrier layer with the groove etched window.

[0006] Further, after patterning and etching the initial semiconductor structure to remove the first isolation layer and the second isolation layer region on the surface of the electrical interconnect structure, and partially removing the first isolation layer to form an initial groove located on top of the first isolation layer, the method further includes: An etched filling structure is filled into the initial groove; the etching rate of the etched filling structure is greater than the etching rate of the first isolation layer. The formation of a barrier layer with trench etching windows on the initial semiconductor structure having the initial groove includes: The barrier layer with trench etching windows is formed on the initial semiconductor structure filled with the etching filling structure.

[0007] Furthermore, the etching selectivity ratio between the first isolation layer and the etching filling structure is less than or equal to a preset selectivity ratio, which is 1 / 3 to 2 / 3.

[0008] Furthermore, the material of the etched filling structure includes at least one of polycrystalline silicon, amorphous silicon, anti-reflective layer material, and photoresist.

[0009] Further, the step of filling the initial groove with an etched filling structure includes: An initial fill layer is formed on an initial semiconductor structure having the initial groove; the initial fill layer covers the remaining second isolation layer and fills the initial groove; The initial fill layer is etched back to remove the initial fill layer area on the surface of the residual second isolation layer, thus obtaining the etched fill structure.

[0010] Furthermore, the height ratio between the depth of the initial groove and the depth of the shallow trench is 60% to 80%.

[0011] Furthermore, the ratio of the residual height of the first isolation layer in the shallow trench to the depth of the shallow trench is 0% to 20%.

[0012] Further, the patterning etching of the initial semiconductor structure to remove the first isolation layer and the second isolation layer region on the surface of the electrical interconnect structure, and to partially remove the first isolation layer to form an initial groove located on top of the first isolation layer includes: A first photomask is formed on the initial semiconductor structure; the groove etching window of the first photomask spans the electrical interconnect structure and the first isolation layer; The initial semiconductor structure covered by the first photomask is dry etched to form the initial groove; Remove the first photomask.

[0013] Furthermore, the electrical connection structure and the first isolation layer are filled in the deep trench, and the photomask pattern forming the deep trench is consistent with the pattern of the first photomask.

[0014] Furthermore, before forming a barrier layer with trench etching windows on the initial semiconductor structure having the initial groove, the method further includes: Remove any remaining second isolation layer.

[0015] Further, the barrier layer includes a third isolation layer and a mask layer, the third isolation layer being stacked on the substrate and the electrical interconnect structure, and the mask layer being stacked on the third isolation layer; the formation of the barrier layer with trench etching windows on the initial semiconductor structure having the initial groove includes: A third initial isolation layer is formed on the initial semiconductor structure having the initial groove; An initial mask layer is formed on the third initial isolation layer; A trench etching window is formed that penetrates the third initial isolation layer and the initial mask layer, so that the remaining third initial isolation layer forms the third isolation layer, and the remaining initial mask layer forms the mask layer.

[0016] On the other hand, this application also provides a semiconductor structure fabricated based on the shallow trench formation method described in any of the preceding claims.

[0017] Implementing this application will have the following beneficial effects: This application first etches away part of the first isolation layer material through patterned etching to easily form an initial groove on the top of the first isolation layer. Then, based on the initial semiconductor structure with the initial groove, subsequent shallow trench etching is performed to form a shallow trench. This can effectively weaken the protective effect of the sidewalls of the first isolation layer on the surrounding substrate material, greatly reduce the defects of the sidewall silicon pillars, and effectively reduce the residual height of the first isolation layer in the final shallow trench. Moreover, the formation method of this shallow trench is highly controllable, which is conducive to improving the structural accuracy of the semiconductor structure, and thus conducive to improving the electrical properties and reliability of the semiconductor structure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1A flowchart illustrating a method for forming a shallow trench as provided in this application; Figure 2 A flowchart illustrating a method for forming an initial groove as provided in this application; Figure 3 This is a flowchart of a method for forming a barrier layer in one embodiment of this application; Figure 4 A flowchart of another method for forming shallow trenches provided in this application; Figure 5 A flowchart of a method for forming an etch-filled structure provided in this application; Figure 6 A flowchart of a method for removing residual second isolation layer provided in this application; Figure 7 A flowchart of a method for forming a barrier layer in another embodiment provided in this application; Figure 8 A flowchart illustrating a method for forming a trench etching window provided in this application; Figure 9 A comparative schematic diagram showing the morphology of shallow trenches prepared by existing technology and shallow trenches prepared in this application.

[0020] The attached figures are labeled as follows: 100 - Substrate, 200 - Electrical interconnect structure, 300 - First isolation layer, 301 - Initial trench, 400 - Second isolation layer, 500 - Barrier layer, 501 - Trench etching window, 502 - Third isolation layer, 503 - Mask layer, 510 - Initial barrier layer, 520 - Third initial isolation layer, 530 - Initial mask layer, 600 - Shallow trench, 700 - Etched filling structure, 710 - Initial filling layer, 800 - First photomask, 801 - Trench etching window, 900 - Second photomask, 901 - Process window. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe specific objects or a sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that the depth direction of an element or layer is perpendicular to the surface of the element or layer, and the cross-sectional direction of an element or layer is parallel to the surface of the element or layer. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. When discussing a second element, component, region, layer, or portion, it does not imply that the application necessarily contains a first element, component, region, layer, or portion.

[0024] To address the problem that existing processes, after filling deep trenches with interconnect structures and a first isolation layer, can lead to silicon pillar defects due to sidewall protection during subsequent shallow trench etching, thus negatively impacting the electrical properties and reliability of the semiconductor structure, this application provides a method for forming shallow trenches and a semiconductor structure. The method involves first providing an initial semiconductor structure, including a substrate, interconnect structures, a first isolation layer, and a second isolation layer. The interconnect structures are embedded in the substrate, the first isolation layer is located between the interconnect structures and the substrate, and the second isolation layer is stacked on the interconnect structures, the first isolation layer, and the substrate surface. Next, the initial semiconductor structure is patterned and etched to remove the second isolation layer region on the surface of the first isolation layer and the interconnect structures, and to partially remove the first isolation layer to form an initial groove on top of the first isolation layer. Then, a barrier layer with a trench etching window is formed on the initial semiconductor structure with the initial groove. This trench etching window spans the substrate, the first isolation layer, and the interconnect structures. Finally, a shallow trench is formed at the trench etching window based on an etching process.

[0025] Thus, compared to the existing shallow trench formation process where the first isolation layer generates sidewall protection, resulting in an excessively high residual height of the first isolation layer in the formed shallow trench, the shallow trench formation method provided in this application reduces the height of the first isolation layer in advance to form an initial groove. This effectively weakens the sidewall protection effect of the first isolation layer during the subsequent shallow trench etching process, improves the structural morphology of the silicon pillars on both sides of the first isolation layer, greatly reduces the residual height of the first isolation layer in the shallow trench, improves the morphological accuracy of the shallow trench, and is beneficial to improving the electrical properties and reliability of the semiconductor structure with the shallow trench.

[0026] The following is in conjunction with the appendix Figure 1-8 This application provides a detailed description of a method for forming shallow trenches according to an embodiment.

[0027] First, refer to Figure 1 It provides the initial semiconductor structure.

[0028] The initial semiconductor structure includes a substrate 100, an electrical interconnect structure 200, a first isolation layer 300, and a second isolation layer 400. The substrate 100 is made of silicon, such as monocrystalline silicon, polycrystalline silicon, SOI, and sapphire, which can provide good mechanical support and facilitate epitaxial growth to support the semiconductor structure fabrication process.

[0029] An electrical interconnect 200 is embedded in the substrate 100 for electrically conducting the initial semiconductor structure; in some alternative embodiments, the material of the electrical interconnect 200 includes polycrystalline silicon, which has good conductivity.

[0030] The first isolation layer 300 is located between the electrical connection structure 200 and the substrate 100, and is used to electrically isolate the electrical connection structure 200 and the substrate 100 to prevent abnormal signal crosstalk and improve the stability and reliability of the initial semiconductor structure. In some optional embodiments, the material of the first isolation layer 300 includes silicon oxide, which has good isolation performance.

[0031] The second isolation layer 400 is stacked on the surface of the electrical interconnect 200, the first isolation layer 300, and the substrate 100 to isolate and protect the substrate 100 and the electrical interconnect 200. In some subsequent semiconductor processes, the second isolation layer 400 can also serve as a barrier layer 500 to prevent undesirable damage to the substrate 100 and the electrical interconnect 200 caused by subsequent processes, which is beneficial to maintaining the morphological accuracy, stability, and reliability of the semiconductor structure. In some optional embodiments, the material of the second isolation layer 400 includes silicon oxide, which is not easily etched and can play a good protective role.

[0032] Next, as Figure 1 As shown, the initial semiconductor structure is patterned and etched to remove the first isolation layer and the second isolation layer region on the surface of the electrical interconnect structure, and to partially remove the first isolation layer to form an initial groove located on top of the first isolation layer.

[0033] Specifically, such as Figure 2 As shown, the patterned etching of the initial semiconductor structure to remove the first isolation layer and the second isolation layer region on the surface of the electrical interconnect structure, and to partially remove the first isolation layer to form an initial groove located on top of the first isolation layer includes: A first photomask is formed on the initial semiconductor structure; the groove etching window of the first photomask spans the electrical interconnect structure and the first isolation layer; The initial semiconductor structure covered by the first photomask is dry etched to form the initial groove; Remove the first photomask.

[0034] The first photomask 800 is made of photoresist. Specifically, a whole photoresist layer can be formed on the initial semiconductor structure first, and then the photoresist layer can be patterned to form a groove etching window 801. The groove etching window 801 of the first photomask 800 spans the electrical interconnect structure 200 and the first isolation layer 300. By exposing and developing the first photomask 800, the pattern of the first photomask 800 is transferred to the initial semiconductor structure, so that the second isolation layer 400 region at the top of the first isolation layer 300 and the second isolation layer 400 region at the top of the electrical interconnect structure 200 are removed, and the etching depth is further increased, so that the top of the first isolation layer 300 is partially removed to form the initial groove 301 located on the top of the first isolation layer 300. The etching efficiency is high and the etching forming accuracy of the initial groove 301 is high. In addition, in this step, the material on the top of the electrical interconnect structure 200 is also partially etched, but the loss of the electrical interconnect structure 200 is extremely small and negligible, and will not have a significant adverse effect on the performance of the semiconductor structure.

[0035] Specifically, in some preferred embodiments, the electrical connection structure 200 and the first isolation layer 300 are filled in the deep trench, and the photomask pattern forming the deep trench is consistent with the pattern of the first photomask 800. In this way, the photomask pattern used to form the deep trench can be reused during the initial trench formation process, without the need to introduce an additional photomask pattern. This not only improves the reusability of the existing deep trench photomask pattern, but also reduces the improvement cost and helps to improve the preparation efficiency of the shallow trench 600 formation method.

[0036] Specifically, the height ratio between the depth of the initial groove 301 and the depth of the shallow trench 600 is 60% to 80%. During the fabrication process, the etching depth of the initial groove 301 can be controlled by controlling the dry etching time. Understandably, the height ratio between the depth of the initial groove 301 and the depth of the shallow trench 600 can be any value within the range of 60% to 80%. For example, the height ratio between the depth of the initial groove 301 and the depth of the shallow trench 600 can be 60%, 62%, 63%, 65%, 68%, 70%, 72%, 75%, 80%, etc. Therefore, by removing a significant amount of the first isolation layer 300 material beforehand, the height of the first isolation layer 300 material that needs to be further etched away during subsequent trench etching is reduced. Even if an easily etchable etchable filler material is then filled into the initial groove 301, the etching difficulty at the first isolation layer 300 is greatly reduced, thereby eliminating the need for sidewall protection, effectively increasing the overall etching depth of the first isolation layer 300, reducing the residual height of the first isolation layer 300 in the final shallow trench 600, effectively improving sidewall silicon pillar defects, and thus improving the electrical properties and reliability of the semiconductor structure.

[0037] Next, as Figure 1As shown, a barrier layer with trench etching windows is formed on an initial semiconductor structure having the initial groove.

[0038] The trench etching window 501 spans the substrate 100, the first isolation layer 300, and the electrical interconnect structure 200. The trench etching window 501 is used to form a shallow trench 600 so that the pattern of the trench etching window 501 can be transferred to the semiconductor structure to form a shallow trench 600 with the desired morphology.

[0039] Specifically, such as Figure 3 As shown, in some exemplary embodiments, forming a barrier layer with a trench etching window on the initial semiconductor structure having the initial groove includes: An initial barrier layer is formed on an initial semiconductor structure having the initial groove; the initial barrier layer is stacked on the substrate, the groove wall of the initial groove and the surface of the electrical interconnect structure, and at least partially fills the initial groove; The initial barrier layer is patterned to form a barrier layer with the groove etched window.

[0040] In this optional embodiment, the initial groove 301 is not filled with additional material. Instead, an initial barrier layer 510 is formed directly on the initial semiconductor having the initial groove 301. In this case, since the initial groove 301 is recessed at the surface of the initial semiconductor structure, especially compared to the electrical interconnect 200 and the substrate 100, the initial barrier layer 510 is also recessed above the initial groove 301 in the initial barrier layer 510 region on the surface of the substrate 100 and the electrical interconnect 200. Correspondingly, during the subsequent shallow trench 600 etching process at the trench etching window 501, the region of the first isolation layer 300 needs to be etched. The height is less than the height to be etched in the area of ​​the electrical interconnect 200, and the height to be etched in the area of ​​the first isolation layer 300 is also less than the height to be etched in the area of ​​the substrate 100. This ensures that even if the etching rate of the first isolation layer 300 is less than the etching rates of the electrical interconnect 200 and the substrate 100 during the final shallow trench 600 etching process, the residual height of the first isolation layer 300 in the final shallow trench 600 can be effectively reduced, and may even reach a state where the first isolation layer 300 is flush with the bottom of the shallow trench 600. This effectively eliminates sidewall silicon pillar defects and improves the electrical properties and reliability of the semiconductor structure with the shallow trench 600.

[0041] Specifically, such as Figure 4As shown, in some other exemplary embodiments, after patterning and etching the initial semiconductor structure to remove the first isolation layer and the second isolation layer region on the surface of the electrical interconnect, and partially removing the first isolation layer to form an initial groove located on top of the first isolation layer, and before forming a barrier layer with a trench etching window on the initial semiconductor structure having the initial groove, the method further includes: An etched filling structure is filled into the initial groove; the etching rate of the etched filling structure is greater than the etching rate of the first isolation layer. Accordingly, forming a barrier layer with a trench etching window on the initial semiconductor structure having the initial groove includes: The barrier layer with trench etching windows is formed on the initial semiconductor structure filled with the etching filling structure.

[0042] In this optional embodiment, the initial groove 301 is filled with an etch-fill structure 700 that is easier to etch than the first isolation layer 300. That is, the top portion of the first isolation layer 300, which forms sidewall protection, is replaced with the easily removable etch-fill structure 700, thereby eliminating the sidewall protection provided by the first isolation layer 300. Compared to the original method where the material to be etched during the shallow trench 600 etching process is the same as that of the first isolation layer 300, this embodiment creates the shallow trench 600 at the subsequent trench etching window 501. The materials to be etched during the etching process include the more easily etchable etch-fill structure 700 and a smaller portion of the first isolation layer 300 material below it. This greatly reduces the etching difficulty at the corresponding position of the first isolation layer 300, and the etching depth is increased accordingly to effectively eliminate sidewall silicon pillar defects. This effectively reduces the residual height of the first isolation layer 300 in the shallow trench 600 formed after the shallow trench 600 is etched, which is beneficial to improving the morphological accuracy of the shallow trench 600 and improving the electrical properties and reliability of the semiconductor structure with the shallow trench 600.

[0043] In addition, it should be noted that, Figure 4 The method of forming the etch-filled structure 700 in the initial groove 301 shown is compared to Figure 1 The method of forming without filling the initial groove 301 with any material can further prevent sputtering damage to the substrate 100 and electrical interconnect structure 200 caused by surface height difference, which is beneficial to further improve the morphological accuracy and performance of the final semiconductor structure and semiconductor device.

[0044] Specifically, the etching selectivity ratio between the first isolation layer 300 and the etch-filled structure 700 is less than or equal to a preset selectivity ratio, which is 1 / 3 to 2 / 3. Understandably, the preset selectivity ratio can be any value between 1 / 3 and 2 / 3. For example, the preset selectivity ratio can be 1 / 3, 4 / 9, 1 / 2, 5 / 9, 2 / 3, etc. Thus, by replacing part of the material at the top of the first isolation layer 300 with the etch-filled structure 700, the etch-filled structure 700 is more easily etched than the first isolation layer 300. Etching can significantly increase the etching depth at the corresponding position of the first isolation layer 300 during the etching process of the shallow trench 600, thereby reducing the residual height of the first isolation layer 300 in the shallow trench 600. This is beneficial for improving the morphological accuracy of the shallow trench 600 and also for improving the electrical properties and reliability of the semiconductor structure with the shallow trench 600. For example, in some specific embodiments, the preset selectivity ratio is 1 / 2, that is, the etching selectivity ratio of the first isolation layer 300 and the etch-filled structure 700 is less than or equal to 1 / 2.

[0045] Specifically, the material of the etch-fill structure 700 includes at least one of polycrystalline silicon, amorphous silicon, anti-reflective layer material (BARC), and photoresist. The etching rate of the etch-fill structure 700 is greater than that of the material of the first isolation layer 300, making it easier to be etched away. This effectively eliminates the sidewall protection of the first isolation layer 300, improves sidewall silicon pillar defects, and enhances the electrical properties and reliability of the semiconductor structure.

[0046] Specifically, such as Figure 5 As shown, the etching filling structure in the initial groove includes: An initial fill layer is formed on an initial semiconductor structure having the initial groove; the initial fill layer covers the remaining second isolation layer and fills the initial groove; The initial fill layer is etched back to remove the initial fill layer area on the surface of the residual second isolation layer, thus obtaining the etched fill structure.

[0047] The initial filling layer 710 can be deposited onto the residual second isolation layer 400 and fill the initial groove 301. The initial filling layer 710 also covers the electrical connection structure 200. Then, the initial filling layer 710 is etched back. During the etch-back process, part of the initial filling layer 710 material on the electrical connection structure 200 and the first isolation layer 300 is etched away. The residual second isolation layer 400 acts as a barrier structure to prevent the etch-back process from damaging the substrate 100 material below the residual second isolation layer 400. This forms an etch-filled structure 700 that is flush with or slightly lower than the surface of the residual second isolation layer 400. The etch-filled structure 700 has high forming efficiency and good forming reliability.

[0048] Furthermore, in some preferred embodiments, the material of the initial filling layer 710 is the same as the material of the electrical interconnect structure 200. For example, both the material of the initial filling layer 710 and the material of the electrical interconnect structure 200 are polysilicon. In this case, the etching process of the filling structure 700 can also compensate for the material loss on the surface of the electrical interconnect structure during the formation of the initial groove 301, thereby making up for the damage to the surface of the electrical interconnect structure 200 during the etching process of the initial groove 301, improving the surface quality of the electrical interconnect structure 200, and further improving the performance of the finally obtained semiconductor structure.

[0049] Specifically, such as Figure 6 As shown, in some optional embodiments, before forming a barrier layer with trench etching windows on the initial semiconductor structure having the initial groove, the method further includes: Remove any remaining second isolation layer.

[0050] The material of the second isolation layer 400 may optionally include silicon oxide, which can be removed by wet etching with high removal efficiency and good removal effect; wherein, the residual second isolation layer 400 is mainly located on the surface of the substrate 100, such as Figure 1 In the formation method shown, the step of removing the residual second isolation layer 400 can specifically occur after forming the initial groove 301; in such a way... Figure 4 In the formation method shown, the removal step of the residual second isolation layer 400 can specifically be performed after the formation of the etch-filled structure 700.

[0051] Before forming the barrier layer 500, removing the residual second isolation layer 400 can improve the surface flatness, thereby improving the stability and surface flatness of the subsequent barrier layer 500 formation, which is beneficial to improving the performance of the final shallow trench 600 and semiconductor structure.

[0052] In addition, in some alternative embodiments, the second isolation layer 400 may not be removed, and the barrier layer 500 may be formed directly on the initial semiconductor structure having the initial groove 301 or on the initial semiconductor structure having the etch-filled structure 700 while the second isolation layer 400 remains.

[0053] Specifically, such as Figure 7 As shown, the barrier layer 500 includes a third isolation layer 502 and a mask layer 503. The third isolation layer 502 is stacked on the substrate 100 and the electrical interconnect structure 200, and the mask layer 503 is stacked on the third isolation layer 502. The formation of the barrier layer with trench etching windows on the initial semiconductor structure having the initial groove includes: A third initial isolation layer is formed on the initial semiconductor structure having the initial groove; An initial mask layer is formed on the third initial isolation layer; A trench etching window is formed that penetrates the third initial isolation layer and the initial mask layer, so that the remaining third initial isolation layer forms the third isolation layer, and the remaining initial mask layer forms the mask layer.

[0054] In the absence of initial groove 301, the third initial isolation layer 520 is specifically stacked on the substrate 100, the electrical interconnect structure 200, and the initial groove 301; in the presence of etch fill structure 700, the third isolation layer 502 is specifically stacked on the substrate 100, the electrical interconnect structure 200, and the etch fill structure 700. The third initial isolation layer 520 is an oxide layer used to grow the initial mask layer 530 on the third initial isolation layer 520. At the same time, the third initial isolation layer 520 and the subsequently formed third isolation layer 502 can also serve as part of the barrier layer 500 to further protect and isolate the substrate 100 material and the electrical interconnect structure 200 material in subsequent process steps, resulting in good reliability.

[0055] The initial mask layer 530 is made of silicon nitride, which has good hardness and isolation properties. It can provide good protection and isolation for the underlying substrate 100 and electrical interconnect structure 200, which is beneficial to improving the performance and stability of the final semiconductor structure.

[0056] like Figure 8 As shown, in some exemplary embodiments, forming the trench etching window that penetrates the third initial isolation layer and the initial mask layer includes: A second photomask with a process window is formed on the initial mask layer; the process window of the second photomask spans the substrate, the first isolation layer, and the electrical interconnect structure. Dry etching is performed on the initial mask layer and the third initial isolation layer covered by the second photomask to form the trench etching window; Remove the second photomask.

[0057] The second photomask 900 is made of photoresist. Specifically, a whole photoresist layer can be formed on the initial mask layer 530 first, and then the photoresist layer can be patterned to form a process window 901. The process window 901 of the second photomask 900 spans the substrate 100, the electrical interconnect 200 and the first isolation layer 300. By exposing and developing the second photomask 900, the materials of the initial mask layer 530 and the third initial isolation layer 520 on the first isolation layer 300 area, part of the substrate 100 area and part of the electrical interconnect 200 area are etched, and the pattern of the second photomask 900 is transferred to the initial mask layer 530 and the third initial isolation layer 520 to form the trench etching window 501. The remaining initial mask layer 530 is formed as the mask layer 503 and the remaining third initial isolation layer 520 is formed as the third isolation layer 502.

[0058] Next, as Figure 1 As shown, a shallow trench is formed at the etching window of the trench based on the etching process.

[0059] In this step, the pattern of the trench etching window 501 can be further transferred into the initial semiconductor structure; in such a way... Figure 1 In the formation method shown, a portion of the substrate 100 material and a portion of the electrical interconnect 200 material exposed in the trench etching window 501 are etched. Simultaneously, based on the initial groove 301, the first isolation layer 300 is further etched to form a shallow trench 600 spanning a portion of the substrate 100, the first isolation layer 300, and a portion of the electrical interconnect 200; in such a way... Figure 4 In the formation method shown, the portion of the substrate 100 and the portion of the electrical interconnect structure 200 exposed by the trench etching window 501 are etched. Simultaneously, in the region corresponding to the first isolation layer 300, the etch-filled structure 700 exposed to the trench etching window 501 can be completely etched away, and the first isolation layer 300 is further etched to form a shallow trench 600 spanning a portion of the substrate 100, the first isolation layer 300, and the portion of the electrical interconnect structure 200. In this way, the residual height of the first isolation layer 300 in the shallow trench 600 is effectively reduced, sidewall silicon pillar defects caused by sidewall protection are eliminated, the morphological accuracy of the shallow trench 600 is improved, the fabrication precision is high, and it is beneficial to improve the electrical properties and reliability of the obtained semiconductor structure.

[0060] Specifically, during the complete etching process of this formation method, the total etching depth of the first isolation layer 300 is equal to the sum of the depth of the initial groove 301 and the etching depth of the first isolation layer 300 in the shallow trench 600 etching step where a shallow trench 600 is formed at the trench etching window 501 based on the etching process. Since the surface of the first isolation layer 300 and the surface of the substrate 100 are almost flush in the initial semiconductor structure, the depth of the finally formed shallow trench 600 is equal to the sum of the total etching depth of the first isolation layer 300 and its residual height in the shallow trench 600. In this embodiment, the ratio of the residual height of the first isolation layer 300 in the shallow trench 600 to the depth of the shallow trench 600 is 0% to 20%, that is, the ratio of the total etching depth of the first isolation layer 300 to the depth of the shallow trench 600 is 80% to 100%.

[0061] Understandably, the ratio of the residual height of the first isolation layer 300 in the shallow trench 600 to the depth of the shallow trench 600 can be any value between 0% and 20%. For example, the ratio of the residual height of the first isolation layer 300 in the shallow trench 600 to the depth of the shallow trench 600 can be 0%, 5%, 10%, 13%, 15%, 20%, etc. Within this residual height range, the residual of the first isolation layer 300 in the shallow trench 600 is relatively small. The low residual height has a smaller adverse effect on the morphology of the shallow trench 600, which is beneficial to improving the electrical properties and reliability of the semiconductor structure having the shallow trench 600.

[0062] On the other hand, this application provides a semiconductor structure fabricated based on the shallow trench 600 formation method described above. This semiconductor structure includes a substrate 100, an electrical interconnect structure 200, a first isolation layer 300, and a shallow trench 600. The electrical interconnect structure is embedded in the substrate 100, the first isolation layer 300 is located between the substrate 100 and the electrical interconnect structure 200, and the shallow trench 600 spans the substrate 100, the first isolation layer 300, and the electrical interconnect structure 200. Figure 9 As shown, the left side is a schematic diagram of the morphology of a shallow trench 600 prepared by prior art, and the right side is a schematic diagram of the morphology of a shallow trench 600 prepared in this application. In this semiconductor structure, the residual height of the first isolation layer 300 in the shallow trench 600 is effectively reduced, or the top of the first isolation layer 300 can be flush with the bottom of the shallow trench 600, thereby improving the morphological accuracy of the shallow trench 600 and improving the electrical properties and reliability of the semiconductor structure.

[0063] On the other hand, this application provides a semiconductor device, including the semiconductor structure described above, which has high device morphology precision and greatly improved device performance. This semiconductor device includes at least one of the following: diode, bipolar junction transistor (BJT), MOSFET / JFET, insulated gate bipolar junction transistor (IGBT), complementary metal-oxide-semiconductor (CMOS), high-voltage power field-effect transistor (DMOS), thyristor (SCR), and BCD device. The BCD device combines BJT, CMOS, and DMOS processes, achieving high integration and high efficiency with low power consumption. This semiconductor device can be applied to any electronic product or device, such as mobile phones, tablets, laptops, netbooks, game consoles, televisions, VCDs, DVDs, navigators, cameras, camcorders, voice recorders, MP3 players, MP4 players, and PSPs, and can also be applied to intermediate products in electronic devices to improve the performance of electronic devices.

[0064] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the scope defined in the claims.

Claims

1. A method of forming a shallow trench, characterized by, The method comprises: providing an initial semiconductor structure; the initial semiconductor structure comprises a substrate, an electrical connection structure, a first isolation layer and a second isolation layer, the electrical connection structure is embedded in the substrate, the first isolation layer is located between the electrical connection structure and the substrate, and the second isolation layer is laminated on the surface of the electrical connection structure, the first isolation layer and the substrate; patterned etching the initial semiconductor structure to remove the first isolation layer and the second isolation layer region on the surface of the electrical connection structure, and partially remove the first isolation layer to form an initial recess on the top of the first isolation layer; forming a barrier layer with a trench etching window on the initial semiconductor structure with the initial recess; the trench etching window crosses the substrate, the first isolation layer and the electrical connection structure; forming a shallow trench at the trench etching window based on an etching process.

2. The method of forming a shallow trench according to claim 1, wherein The forming of the barrier layer with the trench etching window on the initial semiconductor structure with the initial recess comprises: forming an initial barrier layer on the initial semiconductor structure with the initial recess; the initial barrier layer is laminated on the surface of the substrate, the initial recess wall and the electrical connection structure, and at least partially fills the initial recess; the initial barrier layer is patterned to form a barrier layer with the trench etching window.

3. The method of forming a shallow trench according to claim 1, wherein After the patterned etching of the initial semiconductor structure to remove the first isolation layer and the second isolation layer region on the surface of the electrical connection structure, and partially remove the first isolation layer to form an initial recess on the top of the first isolation layer, the method further comprises: filling an etching filling structure in the initial recess; the etching rate of the etching filling structure is greater than the etching rate of the first isolation layer; The forming of the barrier layer with the trench etching window on the initial semiconductor structure with the initial recess comprises: forming the barrier layer with the trench etching window on the initial semiconductor structure filled with the etching filling structure.

4. The method of forming a shallow trench according to claim 3, wherein The etching selection ratio between the first isolation layer and the etching filling structure is less than or equal to a preset selection ratio, and the preset selection ratio is 1 / 3-2 / 3.

5. The method of forming a shallow trench according to claim 3, wherein The material of the etching filling structure comprises at least one of polysilicon, amorphous silicon, anti-reflection layer material and photoresist.

6. The method of forming a shallow trench according to claim 3, wherein The filling of the etching filling structure in the initial recess comprises: forming an initial filling layer on the initial semiconductor structure with the initial recess; the initial filling layer covers the residual second isolation layer and fills the initial recess; etching back the initial filling layer to remove the initial filling layer region on the surface of the residual second isolation layer to obtain the etching filling structure.

7. The method of forming a shallow trench according to claim 1, wherein The height ratio between the depth of the initial recess and the depth of the shallow trench is 60%-80%.

8. The method of forming a shallow trench according to any one of claims 1 to 7, wherein The ratio of the residual height of the first isolation layer in the shallow trench to the depth of the shallow trench is 0%-20%.

9. The method of forming a shallow trench according to any one of claims 1 to 7, wherein The patterned etching of the initial semiconductor structure to remove the first isolation layer and the second isolation layer region on the surface of the electrical connection structure, and partially remove the first isolation layer to form an initial recess on the top of the first isolation layer comprises: forming a first mask on the initial semiconductor structure; a recess etching window of the first mask is across the electrically connected structure and the first isolation layer; dry etching the initial semiconductor structure covered by the first mask to form the initial recess; removing the first mask.

10. The method of forming a shallow trench according to claim 9, wherein The electrically connected structure and the first isolation layer are filled in the deep trench, and a mask pattern of the deep trench is consistent with a pattern of the first mask.

11. The method of forming a shallow trench according to any one of claims 1 to 7, wherein Before forming the barrier layer with a trench etching window on the initial semiconductor structure with the initial recess, the method further comprises: removing the residual second isolation layer.

12. The method of forming a shallow trench according to any one of claims 1 to 7, wherein The barrier layer comprises a third isolation layer and a mask layer, the third isolation layer is laminated on the substrate and the electrically connected structure, and the mask layer is laminated on the third isolation layer; The forming the barrier layer with a trench etching window on the initial semiconductor structure with the initial recess comprises: forming a third initial isolation layer on the initial semiconductor structure with the initial recess; forming an initial mask layer on the third initial isolation layer; forming the trench etching window through the third initial isolation layer and the initial mask layer, so that the residual third initial isolation layer forms the third isolation layer, and the residual initial mask layer forms the mask layer.

13. A semiconductor structure, characterized by The method is based on the method for forming a shallow trench as claimed in any one of claims 1-12.

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