Semiconductor device and preparation method thereof
By setting dielectric layers of varying thickness on a substrate and utilizing plasma etching, the simultaneous fabrication of elongated metal filaments and openings was achieved, solving the problems of high process complexity and high cost in existing technologies and improving production efficiency and reliability.
Patent Information
- Application Number
- CN202511904260.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-16
- Publication Date
- 2026-03-06
AI Technical Summary
Existing technologies make it difficult to achieve precise control of oxide layer thickness and complete opening of passivation layer simultaneously in a single photomask process when preparing long strip metal wires with residual oxide layer on the surface. This results in high process complexity, increased cost, and long production cycle.
By setting dielectric layers with varying thicknesses on a substrate, a photoresist mask is formed using a single patterning process. Combined with capacitively coupled and inductively coupled plasma etching processes, the dielectric layer and the barrier layer are etched separately, enabling the simultaneous fabrication of elongated metal wires and openings.
It reduced the cost of photomasks, simplified the process, shortened the preparation cycle, and improved production efficiency and preparation reliability.
Smart Images
Figure CN121620187A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its fabrication method. Background Technology
[0002] Metal fuses are programmable components integrated into semiconductor chips. They can be melted by current or laser to permanently change the function of a circuit and are widely used in fields such as chip redundancy repair and one-time programming.
[0003] Metal filaments are mainly classified into two types: those with and without residual oxide layers on their surfaces. During fabrication, metal filaments are typically processed together with the chip's passivation layer. In existing processes for fabricating elongated metal filaments with residual oxide layers, the microscopic loading effect during etching is insignificant because the pattern area is similar to the passivation layer's opening area. This makes it difficult to simultaneously achieve precise control of the oxide layer thickness in the metal filament region and complete passivation layer opening in a single photomask process. Therefore, the industry standard practice is to use two photomasks and two independent etching steps to achieve precise control of the oxide layer thickness in the metal filament region and complete passivation layer opening, respectively. While this method ensures structure formation, it increases photomask cost, process complexity, and production cycle. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which can simultaneously fabricate elongated metal filaments and openings using a single photomask, thereby reducing fabrication costs, shortening the fabrication cycle, and improving production efficiency.
[0005] The embodiments of the present invention are implemented as follows: In one aspect, the present invention provides a method for fabricating a semiconductor device, comprising: providing a substrate, wherein the substrate includes a first region and a second region along a first direction, a dielectric layer is formed on the surface of the substrate, a first metal layer is formed within the dielectric layer on the substrate in the first region, a second metal layer is formed within the dielectric layer on the substrate in the second region, a barrier layer is provided between the second metal layer and the dielectric layer, and the thickness of the dielectric layer on the top surface of the first metal layer is greater than the thickness of the dielectric layer on the top surface of the second metal layer; forming a photoresist mask on the surface of the dielectric layer by a single patterning process, the photoresist mask including an elongated filament pattern on the first region and an aperture pattern on the second region; etching the dielectric layer using the photoresist mask to remove a portion of the dielectric layer on the second metal layer and expose the barrier layer, and thinning the dielectric layer on the first metal layer to a predetermined thickness to form a metal filament; and etching the exposed barrier layer using the photoresist mask to expose the second metal layer and form a metal pad.
[0006] Optionally, the dielectric layer is etched using a photoresist mask, including: using a barrier layer as an etching stop layer, performing main etching on the dielectric layer to remove the dielectric layer on the second metal layer and the dielectric layer of a first thickness on the first metal layer; after detecting that the barrier layer is exposed, performing over-etching for a preset time to remove the dielectric layer of a second thickness on the first metal layer, so that a dielectric layer of a preset thickness remains on the first metal layer.
[0007] Optionally, etching of the dielectric layer using a photoresist mask includes: etching of the dielectric layer using a capacitively coupled plasma etching process; etching of the exposed barrier layer includes: etching of the barrier layer using an inductively coupled plasma etching process.
[0008] Optionally, etching the dielectric layer using capacitively coupled plasma etching (CAPE) includes: introducing a fluorine-containing gas into a CAPE chamber; the fluorine-containing gas includes at least one of carbon tetrafluoride or trifluoromethane.
[0009] Optionally, the barrier layer is etched using an inductively coupled plasma etching process, including: introducing a chlorine-containing gas into the inductively coupled plasma etching chamber; the chlorine-containing gas includes at least one of boron trichloride and chlorine.
[0010] Optionally, the dielectric layer includes an oxide layer, and the barrier layer includes a composite layer composed of titanium nitride and titanium.
[0011] Optionally, the second metal layer is used to form conductive parts for electrical connection; along the direction perpendicular to the substrate, the second metal layer is multi-layered, and the multiple conductive parts formed are electrically connected to each other through conductive connection parts.
[0012] Optionally, a passivation layer covering the first and second regions is also formed on the surface of the dielectric layer.
[0013] Optionally, after etching the barrier layer, the method further includes removing the photoresist mask.
[0014] In another aspect, the present invention provides a semiconductor device prepared by the above-described semiconductor device preparation method.
[0015] The beneficial effects of this invention include: This application provides a method for fabricating a semiconductor device, comprising: providing a substrate, wherein the substrate includes a first region and a second region along a first direction, a dielectric layer is formed on the surface of the substrate, a first metal layer is formed within the dielectric layer on the first region substrate, a second metal layer is formed within the dielectric layer on the second region substrate, a barrier layer is provided between the second metal layer and the dielectric layer, and the thickness of the dielectric layer on the top surface of the first metal layer is greater than the thickness of the dielectric layer on the top surface of the second metal layer, ensuring that in subsequent synchronous etching, when the barrier layer of the second region is exposed, there is sufficient dielectric layer remaining in the first region to form a dielectric protective layer residue on the surface of the metal filament; and forming a photoresist mask on the surface of the dielectric layer through a single patterning process, wherein the photoresist... The mask includes a strip-shaped fuse pattern on the first region and an opening pattern on the second region. Compared with the traditional process of defining and etching the strip-shaped fuse pattern and the opening pattern separately using two photomasks, this saves photomask costs and reduces process complexity. Using a photoresist mask, the dielectric layer is etched to remove part of the dielectric layer on the second metal layer and expose the barrier layer, completing the preliminary processing of the opening in the second region. At the same time, the dielectric layer on the first metal layer is thinned to a preset thickness to form a metal fuse, ensuring that the dielectric protective layer remains on the surface of the metal fuse. Using a photoresist mask, the exposed barrier layer is etched to expose the second metal layer and form metal pads, ensuring that the chip can communicate normally with the outside. The aforementioned semiconductor device fabrication method creates a condition where the etching rate is the same but the total etching amount differs by pre-fabricating the thickness difference of the dielectric layer in the first and second regions. This solves the problem of etching control difficulties caused by the insignificant micro-loading effect in existing technologies. Through a single-pass patterning process, the traditional method of defining and etching the elongated filament pattern and the aperture pattern separately using two photomasks is combined into a single process, saving photomask costs and reducing process complexity. Simultaneously, by sequentially etching the dielectric layer and the barrier layer, the high selectivity of the two etching processes for different materials allows for precise completion of different processing targets in the two regions, improving fabrication reliability and efficiency. This semiconductor device fabrication method can simultaneously fabricate elongated metal filaments and apertures using a single photomask, thereby reducing fabrication costs, shortening the fabrication cycle, and improving production efficiency. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is one of the fabrication flowcharts of a semiconductor device provided in an embodiment of the present invention; Figure 2 The second flowchart of semiconductor device fabrication provided in the embodiments of the present invention; Figure 3 The third flowchart of the semiconductor device fabrication process provided in the embodiments of the present invention; Figure 4 This is one of the schematic diagrams of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 5 This is a second schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 6 This is the third schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 7 The fourth schematic diagram of the structure of the semiconductor device provided in the embodiment of the present invention.
[0018] Icons: 110-First metal layer; 120-Second metal layer; 121-Conductive part; 122-Conductive connection part; 130-Dielectric layer; 140-Barrier layer; 150-Passivation layer; 160-Photoresist mask; A-First region; B-Second region; C-First direction. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0022] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0023] Please refer to Figure 1 This embodiment provides a method for fabricating a semiconductor device, which may include the following steps: Step S100: Provide a substrate, such as... Figure 4 As shown, along the first direction C, the substrate may include a first region A and a second region B. A dielectric layer 130 is formed on the surface of the substrate. A first metal layer 110 is formed in the dielectric layer 130 on the substrate in the first region A. A second metal layer 120 is formed in the dielectric layer 130 on the substrate in the second region B. A barrier layer 140 is provided between the second metal layer 120 and the dielectric layer 130. The thickness of the dielectric layer 130 on the top surface of the first metal layer 110 is greater than the thickness of the dielectric layer 130 on the top surface of the second metal layer 120.
[0024] Specifically, this fabrication method first provides a substrate, which is a wafer that has completed the preliminary front-end processes. Depending on the function, such as... Figure 4 As shown, the substrate may include a first region A and a second region B disposed along a first direction C. The first region A is a region for forming a metal filament with a protective layer on its surface, and the second region B is a region for forming an opening for realizing electrical connections.
[0025] In this embodiment, a first metal layer 110 and a dielectric layer 130 that completely surrounds the periphery and top of the first metal layer 110 are formed on the substrate in the first region A.
[0026] In one specific embodiment of this application, the first metal layer 110 is an aluminum layer or a copper alloy layer, and the dielectric layer 130 is an oxide layer. Preferably, the dielectric layer 130 is a silicon oxide layer.
[0027] In this embodiment, a second metal layer 120, a barrier layer 140 covering the surface of the second metal layer 120, and a dielectric layer 130 surrounding and above the barrier layer 140 are formed on the substrate in the second region B.
[0028] In one specific embodiment of this application, the second metal layer 120 is an aluminum layer or a copper alloy layer.
[0029] It should be noted that, in one specific embodiment of this application, the surface of the first metal layer 110 is also covered with a barrier layer 140. Preferably, the barrier layer 140 comprises a composite layer composed of titanium nitride and titanium.
[0030] In another specific embodiment of this application, such as Figure 4 As shown, the thickness of the dielectric layer 130 on the top surface of the first metal layer 110 is greater than the thickness of the dielectric layer 130 on the top surface of the second metal layer 120, so as to form a thickness difference, ensuring that in subsequent synchronous etching, when the barrier layer 140 of the second region B is exposed, there is enough dielectric layer 130 remaining in the first region A to form a dielectric protective layer residue on the surface of the metal filament.
[0031] In yet another specific embodiment of this application, such as Figure 4 As shown, a passivation layer 150 covering the first region A and the second region B is also formed on the surface of the dielectric layer 130. In the actual etching process, the passivation layer 150 and the dielectric layer 130 are etched in sequence to realize the preparation of the opening.
[0032] In the actual fabrication of semiconductor devices, this thickness difference can be achieved by forming a stepped structure on the top surface of the first region A and the second region B through chemical mechanical polishing, or by adjusting the height difference between the first metal layer 110 and the second metal layer 120. This application does not impose any restrictions on the specific method of setting this thickness difference, as long as it ensures that the thickness of the dielectric layer 130 on the top surface of the first metal layer 110 is greater than the thickness of the dielectric layer 130 on the top surface of the second metal layer 120.
[0033] Step S200: A photoresist mask 160 is formed on the surface of the dielectric layer 130 through a single patterning process. The photoresist mask 160 includes an elongated filament pattern on the first region A and an opening pattern on the second region B.
[0034] Specifically, a photoresist mask 160 is formed on the dielectric layer 130 by a single spin-coating of photoresist and a single exposure and development process using a photomask integrating a strip-shaped filament pattern and an aperture pattern. Figure 4 As shown, the photoresist mask 160 simultaneously and synchronously defines the elongated filament pattern on the first region A and the aperture pattern on the second region B precisely on the surface of the dielectric layer 130. This step directly eliminates the need for a second photomask and its patterning process in traditional dual-photomask processes, reducing the manufacturing cost of the semiconductor device and shortening its fabrication cycle.
[0035] After completing the patterning definition of the photoresist mask 160, the fabrication method may further include: step S300, using the photoresist mask 160 to etch the dielectric layer 130, removing a portion of the dielectric layer 130 on the second metal layer 120 and exposing the barrier layer 140, and thinning the dielectric layer 130 on the first metal layer 110 to a predetermined thickness to form a metal filament, such as... Figure 5 As shown.
[0036] Specifically, in step S300, the aforementioned photoresist mask 160 is used as a protective layer to simultaneously etch the dielectric layer 130 located in the first region A and the dielectric layer 130 located in the second region B.
[0037] Furthermore, since the thickness of the dielectric layer 130 on the top surface of the first metal layer 110 is greater than the thickness of the dielectric layer 130 on the top surface of the second metal layer 120, under the condition of uniform etching rate, the total amount of material that needs to be etched away to penetrate the dielectric layer 130 on the top surface of the second metal layer 120 and expose the barrier layer 140 below it is fixed. When this etching amount is simultaneously applied to the thicker dielectric layer 130 on the top surface of the first metal layer 110, due to the thickness difference, after the dielectric layer 130 on the top surface of the first metal layer 110 is etched away to the same depth, there will inevitably be some material remaining, such as... Figure 5 As shown.
[0038] This step 300 enables two different etching effects to be achieved in a single continuous operation within a single process chamber: in the second region B, the dielectric layer 130 needs to be completely removed to expose the barrier layer 140 on the surface of the second metal layer 120 below; while in the first region A, the initially thicker dielectric layer 130 needs to be precisely thinned to a preset thickness that meets design requirements, thereby initially forming a metal filament structure covered with a dielectric layer 130 of a specific thickness. In one specific embodiment of this application, the dielectric layer 130 is an oxide layer.
[0039] In one possible implementation of this application, such as Figure 2 As shown, step S300 may specifically include: Step S310: Using the barrier layer 140 as the etching stop layer, perform main etching on the dielectric layer 130 to remove the dielectric layer 130 on the second metal layer 120 and the dielectric layer 130 of the first thickness on the first metal layer 110.
[0040] In this embodiment, this step employs process parameters with strong anisotropic etching capability to remove the exposed dielectric layer 130 as a whole at a high rate. Since the etching rates of the dielectric layer 130 in the first region A and the dielectric layer 130 in the second region B are basically the same under the same process conditions, the etching progress is mainly determined by the thickness of the dielectric layer 130. Therefore, etching stops when the thinner dielectric layer 130 on top of the second metal layer 120 is completely etched away, exposing the barrier layer 140 on the second metal layer 120. The thicker dielectric layer 130 on top of the first metal layer 110 is only etched away by the first thickness, and a considerable thickness of dielectric layer 130 remains on top of the first metal layer 110.
[0041] It should be noted that in actual production, the degree of etching of the dielectric layer 130 is usually determined by the endpoint detection system. The etching process can be automatically stopped the moment the barrier layer 140 on the second metal layer 120 is detected, so as to improve the etching accuracy.
[0042] Preferably, the main etching of the dielectric layer 130 can be performed using a capacitively coupled plasma etching process. The capacitively coupled plasma etching system can generate high-density plasma and precisely control the ion bombardment energy, making it suitable for etching the dielectric layer 130, which has high anisotropy, large aspect ratio, and high selectivity for the underlying material. This facilitates the process requirement of simultaneously processing aperture patterns and fine filament patterns required by this fabrication method.
[0043] To efficiently and selectively etch the silicon oxide dielectric layer 130, in one embodiment of this application, a fluorine-containing gas may be introduced into the capacitively coupled plasma etching chamber. Optionally, the fluorine-containing gas may include at least one of carbon tetrafluoride gas or trifluoromethane gas.
[0044] In the above embodiments, fluorine-containing gases such as carbon tetrafluoride or trifluoromethane are dissociated in a plasma environment, generating reactive fluorine radicals. These fluorine radicals can chemically react with the oxide dielectric layer 130, thereby achieving the volatile etching removal of the dielectric layer 130. Simultaneously, by precisely controlling the gas composition and ratio, the etching selectivity of this chemical reaction on the dielectric layer 130 and its underlying barrier layer 140 can be significantly enhanced. This ensures that when the dielectric layer 130 in the second region B is completely etched, the exposed barrier layer 140 can effectively act as an etching stop layer, preventing excessive damage to the underlying metal.
[0045] To further improve the thickness accuracy of the dielectric layer 130 on top of the first metal layer 110, step S320 can be used to perform over-etching for a preset time after detecting the exposed barrier layer 140, thereby removing the dielectric layer 130 of the second thickness on the first metal layer 110, so that the dielectric layer 130 of the preset thickness remains on the first metal layer 110.
[0046] At this point, the etching stage initiates a pre-set and precisely calculated short etching period. In the second region B, due to the high selectivity etching chemistry, the exposed barrier layer 140 is almost no longer etched; while in the first region A, etching continues, continuously thinning the dielectric layer 130 on top of the first metal layer 110 to a second thickness. By precisely controlling the duration of this over-etching stage, the thickness of the dielectric layer 130 on top of the first metal layer 110 can be precisely processed to the preset target thickness, ultimately improving the fabrication accuracy of the semiconductor device.
[0047] To form electrical connection points suitable for wire bonding, the fabrication method may further include step S400: using a photoresist mask 160 to etch the exposed barrier layer 140 to expose the second metal layer 120, forming metal pads, such as... Figure 6 As shown.
[0048] Preferably, the barrier layer 140 can be etched using an inductively coupled plasma etching process.
[0049] In the above embodiments, the barrier layer 140 is etched using an inductively coupled plasma etching (ICP-E) process. ICP-E generates high-density, low-energy plasma, achieving a high etching rate while maintaining low ion bombardment energy through independent control of the bias potential. This gives ICP-E anisotropic etching capability, enabling precise vertical removal of the exposed barrier layer 140 in the second region B, ensuring the integrity of the pattern dimensions.
[0050] In one embodiment of this application, chlorine-containing gas can also be introduced into the inductively coupled plasma etching cavity.
[0051] Optionally, the chlorine-containing gas includes at least one of boron trichloride and chlorine.
[0052] In the above embodiments, the active chlorine radicals generated by the chlorine-based chemical gas in the plasma can chemically react with the barrier layer 140, thereby achieving the volatile removal of the barrier layer 140. More importantly, the chlorine-based chemical system has a high etching selectivity for the barrier layer 140, such as the titanium nitride layer, and the dielectric layer 130, such as the silicon oxide layer. Therefore, this process can rapidly etch the barrier layer 140, while the etching rate for the dielectric layer 130 remaining above the first metal layer 110 is extremely low. This allows for the establishment of electrical connections through openings while also providing reliable protection for the metal filament structure.
[0053] It should be noted that, in one specific embodiment of this application, along the direction perpendicular to the substrate, the second metal layer 120 is multi-layered, with a dielectric layer 130 between the multi-layered second metal layers 120, and a barrier layer 140 is provided between each second metal layer 120 and the dielectric layer 130.
[0054] In this embodiment, the second metal layer 120 is used to form a conductive portion 121 for electrical connection, and each second metal layer 120 is used to form a conductive portion 121.
[0055] In this embodiment, when the second metal layer 120 is multilayered, the multiple conductive portions 121 formed are electrically connected to each other through conductive connection portions 122.
[0056] In this embodiment, a photoresist mask 160 is used to etch the barrier layer 140 on the exposed top second metal layer 120 to expose the surface of the top second metal layer 120 (the conductive part 121 of the top layer) and form a metal pad.
[0057] Preferably, such as Figure 7 As shown, the second metal layer 120 consists of two layers, namely two conductive portions 121. The two conductive portions 121 are arranged along the etching direction and electrically connected through conductive connection portions 122. The exposed barrier layer 140 is etched using a photoresist mask 160 to expose the upper surface of the top conductive portion 121, forming a metal pad.
[0058] Thus, a semiconductor device structure with a long strip of metal filament with precisely controlled dielectric layer thickness of 130 mm and a fully open aperture for electrical connection is completed.
[0059] Optionally, after step S400, as follows Figure 3 As shown, the preparation method also includes step S410, removing the photoresist mask 160.
[0060] Specifically, the residual photoresist mask 160 on the surface of the semiconductor device can be removed using conventional ashing or wet cleaning processes to obtain a clean semiconductor device, such as... Figure 7 As shown.
[0061] The aforementioned semiconductor device fabrication method creates a condition where the etching rate is the same but the total etching amount differs by pre-fabricating the thickness difference between the dielectric layer 130 on the first region A and the dielectric layer 130 on the second region B. This solves the problem of etching control difficulties caused by the insignificant micro-loading effect in existing technologies. Through a single-pass patterning process, the traditional method of defining and etching the elongated filament pattern and the aperture pattern separately using two photomasks is combined into a single process, saving photomask costs and reducing process complexity. Simultaneously, by sequentially etching the dielectric layer 130 and the barrier layer 140, the high selectivity of the two etching processes for different materials allows for precise completion of different processing targets in the two regions, improving fabrication reliability and efficiency. This semiconductor device fabrication method can simultaneously fabricate elongated metal filaments and apertures using a single photomask, thereby reducing fabrication costs, shortening the fabrication cycle, and improving production efficiency.
[0062] In another aspect, the present invention provides a semiconductor device prepared by the above-described semiconductor device preparation method. The semiconductor device preparation method has been described in detail above and will not be repeated here. The semiconductor device prepared by the described semiconductor device preparation method simultaneously possesses a long strip-shaped metal filament with precisely controlled dielectric layer thickness of 130 mm and a fully open aperture for realizing electrical connection, exhibiting good structural precision and product yield.
[0063] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
[0064] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, the substrate comprising a first region and a second region along a first direction, a dielectric layer being formed on a surface of the substrate, a first metal layer being formed in the dielectric layer on the substrate in the first region, a second metal layer being formed in the dielectric layer on the substrate in the second region, a barrier layer being arranged between the second metal layer and the dielectric layer, a thickness of the dielectric layer on a top surface of the first metal layer being greater than a thickness of the dielectric layer on a top surface of the second metal layer; forming a photoresist mask on the surface of the dielectric layer by a single patterning process, the photoresist mask comprising a long strip fuse pattern on the first region and an opening pattern on the second region; etching the dielectric layer by using the photoresist mask to remove part of the dielectric layer on the second metal layer and expose the barrier layer, and thinning the dielectric layer on the first metal layer to a preset thickness to form a metal fuse; etching the exposed barrier layer by using the photoresist mask to expose the second metal layer to form a metal pad.
2. The method of producing a semiconductor device according to claim 1, wherein The etching of the dielectric layer by using the photoresist mask comprises: performing main etching of the dielectric layer by taking the barrier layer as an etching stop layer to remove the dielectric layer on the second metal layer and a first thickness of the dielectric layer on the first metal layer; after detecting that the barrier layer is exposed, performing over-etching for a preset time length to remove a second thickness of the dielectric layer on the first metal layer, so that a preset thickness of the dielectric layer on the first metal layer remains.
3. The method of manufacturing a semiconductor device according to claim 1, wherein The etching of the dielectric layer by using the photoresist mask comprises: performing etching of the dielectric layer by a capacitively coupled plasma etching process; The etching of the exposed barrier layer comprises: performing etching of the barrier layer by an inductively coupled plasma etching process.
4. The method of producing a semiconductor device according to claim 3, wherein The etching of the dielectric layer by the capacitively coupled plasma etching process comprises: passing a fluorine-containing gas into a capacitively coupled plasma etching cavity; The fluorine-containing gas comprises at least one of carbon tetrafluoride gas or trifluoromethane gas.
5. The method of producing a semiconductor device according to claim 3, wherein The etching of the barrier layer by the inductively coupled plasma etching process comprises: passing a chlorine-containing gas into an inductively coupled plasma etching cavity; The chlorine-containing gas comprises at least one of boron trichloride and chlorine.
6. The method of producing a semiconductor device according to Claim 1, wherein The dielectric layer comprises an oxidation layer, and the barrier layer comprises a composite layer composed of titanium nitride and titanium.
7. The method of producing a semiconductor device according to Claim 1, wherein The second metal layer is used to form an electrically connected conductive part; along a direction perpendicular to the substrate, the second metal layer is a plurality of layers, and a plurality of conductive parts formed by the plurality of layers are electrically connected through a conductive connecting part.
8. The method of producing a semiconductor device according to Claim 1, wherein A passivation layer covering the first region and the second region is further formed on a surface of the dielectric layer.
9. The method of producing a semiconductor device according to Claim 1, wherein After the etching of the barrier layer, the method further comprises: removing the photoresist mask.
10. A semiconductor device, characterized by comprising: The semiconductor device is prepared by the preparation method of any one of claims 1-9.