A method for three-dimensional stacked chip connection by means of a sacrificial layer

Abstract

The present application relates to a kind of method for realizing three-dimensional stacked chip connection by sacrificial layer, comprising: providing at least two layers of the multilayer chip to be stacked, each layer of chip includes functional structure, first easy combination layer and / or second easy combination layer;Wherein, at least one layer of chip further includes sacrificial layer and connecting hole;The multilayer chip is aligned, stacked and bonded according to functional requirement, and forms stacked chip;Using first mask to carry out photoetching to the multilayer chip after stacking, and using first etching material to etch, form the super deep hole that passes through at least part of chip layer;Using second etching material to etch the sacrificial layer, form the cavity that can cover the connecting hole;Depositing and / or growing material, form the connection of functional structure and external through the filling super deep hole.The present application can solve the problem of high-density interconnection between layers of three-dimensional stacked chip device by the combination of ultra-thin thinning layer stacking technology;Meanwhile, it also has the advantages of effectively overcoming particle contamination, improving chip manufacturability and the like.

Description

Technical Field

[0001] This invention relates to multi-layer chip stacking and three-dimensional stacked chip packaging technology and multi-layer stacked chips in the field of semiconductor technology, specifically to a method for achieving three-dimensional stacked chip connection through a sacrificial layer. Background Technology

[0002] With the continuous development of critical dimensions in integrated circuits, current integrated circuits on the market are approaching the nanometer scale, and the challenges posed by quantum tunneling leakage current have become increasingly severe. As device size decreases, the integration density of a single chip has not increased proportionally according to Moore's Law. Therefore, three-dimensional integration has become one of the core methods to improve chip integration density.

[0003] To address the challenges of 3D integration, common methods currently employed include using TSV (ultra-deep via) and µBUMP (microsphere) technologies to interconnect multiple layers of chips at the level of tens of thousands to hundreds of thousands of nodes. Alternatively, high-density planar connections can be achieved through RDL (rewiring hierarchy) of the interposer, interconnecting multiple chips with thousands to tens of thousands of interconnect lines. While these methods can achieve communication bandwidths at the TB / s level, the relatively large size of µBUMPs means that achieving even higher-density interconnects remains a significant challenge. Furthermore, direct bonding methods have recently been used, which can reduce the size of the interconnect holes to the 1µm level. However, this method requires extremely high levels of particle contamination control and is prone to connection failures.

[0004] In view of this, a method for achieving interconnection of three-dimensional stacked chips through a sacrificial layer is proposed to solve the interconnection problem between high-density layers of the three-dimensional stacked chips, as well as the problem of connection failure that is prone to occur due to high requirements for particulate contamination control. Summary of the Invention

[0005] This invention addresses at least one technical problem in the prior art by providing a method for achieving three-dimensional stacked chip interconnection through a sacrificial layer.

[0006] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0007] A method for achieving three-dimensional stacked chip interconnection through a sacrificial layer includes:

[0008] A multilayer chip with at least two layers to be stacked is provided, each chip layer including a functional structure and at least one easily bondable layer; wherein, at least one chip layer also includes a sacrificial layer and a via, and the sacrificial layer, the via and the functional structure form a material connection;

[0009] The multilayer chips are aligned, stacked, and bonded according to functional requirements to form a stacked chip.

[0010] The stacked multilayer chip is photolithographically etched using a first mask and etched using a first etching material to form an ultra-deep hole penetrating at least a portion of the chip layers.

[0011] The sacrificial layer is etched using a second etching material to form a cavity that can cover the connection hole;

[0012] Materials are deposited and / or grown to form functional structures that connect to the outside through the filled ultra-deep pores.

[0013] In some embodiments, the sacrificial layer is made of a non-conductive material.

[0014] In some embodiments, the second etching material is an isotropic etching material.

[0015] In some embodiments, the functional structure includes one or more functional structures in an integrated circuit, electronic device, optical device, electronic circuit, optical path, microfluidic path, detector, or microelectromechanical system.

[0016] In some embodiments, the stacked chip further includes a carrier wafer, which includes one or more of the following composites: a silicon / germanium / compound semiconductor bare die, a silicon / germanium / compound semiconductor with functional structure fabrication, a three-dimensional stacked chip with interlayer interconnection, diamond, silicon dioxide, glass, ceramic, PCB board, blue film, carrier tape, and protective adhesive.

[0017] In some embodiments, at least one layer of the chip further includes a connection pad, the connection pad having a connection pad connection hole, the connection pad forming a material connection with the functional structure through the connection pad connection hole.

[0018] In some embodiments, the stacked chip further includes a first etchable material etch barrier layer and / or the connection pad, wherein the connection pad is made of a material that the first etchable material cannot etch.

[0019] In some embodiments, if the connection pad is made of a material that is not etchable by the second etch material, the filling ultra-deep via is connected to the chip functional structure in sequence through the connection pad and the connection pad connection hole; if the connection pad is made of a material that is etchable by the second etch material, the portion of the connection pad that forms a cavity is etched away by the second etch material, and the functional structure is connected to the outside by deposition and / or growth of material.

[0020] In some embodiments, when the functional structure is a microfluidic pathway, the ultra-deep orifice, cavity, and connecting hole are connected while maintaining fluid void connection, and / or the ultra-deep orifice, connecting pad, and connecting pad connecting hole are connected while maintaining fluid void connection.

[0021] In some embodiments, the retention fluid void connection includes etching the connection hole and / or connection pad connection hole using a second or third etching material.

[0022] As can be seen from the above, by etching ultra-deep holes, sacrificial layers, and depositing or growing materials, the effect of connecting multiple chips with one ultra-deep hole can be achieved; by combining it with ultra-thin layer stacking technology, the problem of high-density interlayer interconnection of three-dimensional stacked chip devices can be solved; in addition, the method of etching after stacking can effectively overcome the problem of poor connection effect caused by particulate contamination, thereby improving the manufacturability of the chip. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the method for achieving three-dimensional stacked chip interconnection through a sacrificial layer provided by the present invention; wherein, Figure 1 (A) is an example of a three-layer chip structure for stacking. Figure 1 Image (B) shows an example of the structure of stacked chips after etching with etching material. Figure 1 (C) is a diagram of a three-dimensional stacked chip structure implemented through a sacrificial layer;

[0024] Figure 2 This is a schematic diagram of a three-dimensional stacked chip with different functional structures provided by the present invention; wherein, Figure 2 Image (A) is a schematic diagram of a solid connection structure formed by filling material. Figure 2 (B) is a schematic diagram of a connection structure that retains fluid voids;

[0025] Figure 3 This is a schematic diagram of the method for connecting three-dimensional stacked chips using a carrier chip provided by the present invention;

[0026] Figure 4 This is a schematic diagram illustrating the method provided by the present invention for etching a barrier material using a bonding pad as the first etching material and realizing a three-dimensional stacked chip using a sacrificial layer; wherein... Figure 4 (A) shows an example of a three-layer chip structure for stacking. Figure 4 Image (B) shows an example of the structure of stacked chips after etching with etching material. Figure 4 (C) is a three-dimensional stacked chip structure diagram showing the etching of the barrier material using the first etching material through the connection pad and the realization through the sacrificial layer;

[0027] Explanation of reference numerals in the attached figures:

[0028] 95. First etching material etching barrier layer; 201. First functional structure; 202. Second functional structure; 203. Third functional structure; 213. Functional structure; 3211. First connecting hole; 3212. Second connecting hole; 3221. Third connecting hole; 3311. First ultra-deep hole; 3321. Second ultra-deep hole; 331. First filled ultra-deep hole; 332. Second filled ultra-deep hole; 3411. Connecting pad; 341. First connecting pad; 342. Second connecting pad; 343. Fifth connecting pad; 3 631, Connecting pad connection hole; 371, First external connecting pad; 372, Second external connecting pad; D400, Stacked chips; 401, First layer chip; 402, Second layer chip; 403, Third layer chip; 413, Carrier die; 5011, First cavity; 5012, Second cavity; 711, First easy-connect layer; 712, Third easy-connect layer; 713, Fifth easy-connect layer; 721, Second easy-connect layer; 722, Fourth easy-connect layer; 741, First sacrificial layer; 742, Second sacrificial layer. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0031] In the description of this application, the term "for example" is used to mean "used as an example, illustration, or description." Any embodiment described as "for example" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0032] Based on the reasons mentioned in the background technology, in order to achieve high-density interconnection of multi-layer three-dimensional stacked chips, a method for connecting three-dimensional stacked chips through a sacrificial layer is proposed, mainly including:

[0033] like Figure 1 As shown, a method for achieving three-dimensional stacked chip interconnection through a sacrificial layer includes providing at least two multilayer chips to be stacked, each chip layer including a functional structure, a first easily bondable layer, and / or a second easily bondable layer; wherein at least one chip layer further includes a sacrificial layer and a connection via, and the sacrificial layer, connection via, and functional structure form a material connection. Figure 1 As shown in (A), the first-layer chip 401, the second-layer chip 402, and the third-layer chip 403 all contain integrated circuit functional structures. The first-layer chip 401 includes a first easily bondable layer 711, a second easily bondable layer 721 (it can be understood that in this embodiment, the first-layer chip 401 includes two easily bondable layers, which are named the first easily bondable layer 711 and the second easily bondable layer 721 for ease of description), a second connecting hole 3212 that can be connected to an ultra-deep via, and a first sacrificial layer 741; the first sacrificial layer 741, the second connecting hole 3212, and the first functional structure 201 form a material connection. The second-layer chip 402 includes a third easy-connect layer 712, a fourth easy-connect layer 722 (it can be understood that in this embodiment, the second-layer chip 402 includes two easy-connect layers, which are named the third easy-connect layer 712 and the fourth easy-connect layer 722 respectively for ease of description), a third connecting hole 3221 that can be connected to an ultra-deep via, and a second sacrificial layer 742. The second sacrificial layer 742, the third connecting hole 3221, and the second functional structure 202 form a material connection. The third-layer chip 403 includes a fifth easy-connect layer 713 (it can be understood that in this embodiment, the third-layer chip 403 includes one easy-connect layer, which is named the fifth easy-connect layer 713 for ease of description), a first connecting pad 341 that can be connected to an ultra-deep via, a second connecting pad 342 for serving as an etching barrier layer, and a connecting pad connecting hole 3631. The first connecting pad 341 and the connecting pad connecting hole 3631 form a material connection with the third functional structure 203. The number of vertically connected connecting holes and connecting pads can be one, or multiple connecting holes forming a combination, or a combination of multiple holes connected to one or more metal connecting wires; even some or all of the connecting holes, connecting pads, or combined connecting holes and combined connecting pads are made using the same hole and / or connecting wire processes in chip manufacturing; no specific limitations are imposed.

[0034] It should be understood that in this embodiment, three connection holes may be provided, which are named first connection hole 3211, second connection hole 3212 and third connection hole 3221 respectively for ease of description.

[0035] The first-layer chip 401, the second-layer chip 402, and the third-layer chip 403 are aligned, stacked, and bonded according to functional requirements to form a stacked chip D400. During bonding, the second easy-bond layer 721 of the first-layer chip 401 is bonded to the third easy-bond layer 712 of the second-layer chip 402, and the fourth easy-bond layer 722 of the second-layer chip 402 is bonded to the fifth easy-bond layer 713 of the third-layer chip 403. Easy-bond layers are used because conventional chip manufacturing materials have high bonding melting points or eutectic points, and solid-solid bonding is difficult, making it hard to bond conventional chips together. Therefore, easy-bond layers are needed, such as borosilicate glass, which is polished and activated before bonding.

[0036] like Figure 1 As shown in (B), a first mask is used to perform photolithography on the stacked chip D400, and a first ultra-deep hole 3311 and a second ultra-deep hole 3321 are formed by etching with a first etching material. The first connection pad 341 and the second connection pad 342 are used as etching barrier layers 95 to stop the etching of the ultra-deep holes. A second etching material is used to etch a sacrificial layer to form a cavity that can cover the connection holes, such as the first cavity 5011 and the second cavity 5012 of the first layer chip 401. The second cavity 5012 covers the second connection hole 3212. It should be noted that the etching time needs to be strictly controlled. On the one hand, it should be able to cover the designed adjacent connection holes, and on the other hand, it should not connect to other nearby connection holes due to etching. That is, after etching, part of the first sacrificial layer 741 and the second sacrificial layer 742 will still be retained.

[0037] like Figure 1 As shown in (C), materials are deposited and / or grown to form a connection between the first functional structure 201, the second functional structure 202 and the third functional structure 203 and the external first external connection pad 371 and the second external connection pad 372 through the first filled ultra-deep hole 331 and the second filled ultra-deep hole 332.

[0038] Both the first sacrificial layer 741 and the second sacrificial layer 742 are made of non-conductive material. For the first filled ultra-deep via 331 and the second filled ultra-deep via 332 used for electrical connection, since the first sacrificial layer 741 and the second sacrificial layer 742 still have material after etching, their insulation properties can ensure that there will be no signal interference between adjacent ultra-deep vias, or that the power supply ultra-deep vias will not leak current through the sacrificial layer.

[0039] After etching the first ultra-deep via 3311 and the second ultra-deep via 3321, the second etching material etches the first sacrificial layer 741 and the second sacrificial layer 742. Since the cavities formed by etching the first sacrificial layer 741 and the second sacrificial layer 742 are such as the first cavity 5011 and the second cavity 5012 of the first chip 401, the second etching material needs to enter the stacked chip through the first ultra-deep via 3311 and the second ultra-deep via 3321, and etch the first sacrificial layer 741 of the first chip 401 laterally to form the first cavity 5011 and the second cavity 5012. In order to ensure the lateral etching capability, the second etching material is an isotropic etching material or has good isotropic etching characteristics.

[0040] The aforementioned first functional structure 201, second functional structure 202, and third functional structure 203 are one or more functional composite structures in integrated circuits, electronic devices, optical devices, electronic circuits, optical pathways, microfluidic pathways, detectors, and microelectromechanical systems. The main objective of this invention is to etch small-sized first ultra-deep holes 3311 and second ultra-deep holes 3321 into a three-dimensional stacked chip, and to etch cavities through the first sacrificial layer 741 and the second sacrificial layer 742, depositing and / or growing materials to form connections. Its characteristic is the formation of high-density cavities and their connection with the deposited material. The connection can be conductive, light-guiding, or, if necessary, flow-guiding (liquid or gas-guiding). Therefore, it can be any functional structure or composite structure for a specific chip, whether it be an integrated circuit, electronic device, optical device, electronic circuit, optical pathway, microfluidic pathway, detector, or microelectromechanical system. This method can be used to fabricate stacked structure connections, and no specific limitation is made.

[0041] Besides achieving three-dimensional stacked chip connection through the method of this invention, multi-layer chips can also be stacked with a carrier wafer to form a connection between the multi-layer chip and the carrier wafer, or the three-dimensional stacked chips can be transported or stored using a carrier wafer. The carrier wafer includes one or more of the following composites: a silicon / germanium / compound semiconductor bare die, a silicon / germanium / compound semiconductor with completed functional structure fabrication, a three-dimensional stacked chip with completed interlayer connections, diamond, silicon dioxide, glass, ceramic, a PCB board, a blue film, a carrier tape, and a protective adhesive; wherein the blue film, carrier tape, and protective adhesive are mainly used during the fabrication of the three-dimensional stacked chips to facilitate their transport or storage. Figure 3The diagram shows a stacked structure of the first-layer chip 401, the second-layer chip 402, and the carrier 413. In specific applications, the carrier is a circuit board fabricated on any one or more materials such as silicon / germanium / compound semiconductor dies, diamond, silicon dioxide, glass, ceramics, or PCB boards. Thus, after the first-layer chip 401 and the second-layer chip 402 are stacked with the carrier 413, because the first-layer chip 401 and the second-layer chip 402 are very thin (e.g., 1µm thick), they can be supported by the carrier 413, connected through the carrier 413, and also connected to external components (not shown in the diagram).

[0042] The aforementioned at least one chip layer also includes a connection pad 3411, which has a connection pad connection hole 3631. The connection pad 3411 forms a material connection with the functional structure through the connection pad connection hole 3631. Figure 1 The connecting pad shown has a connecting hole 3631. Figure 1 The first connecting pad 341 shown in (C) forms a material connection with the third functional structure 203 through the connecting pad connecting hole 3631. Figure 3 The carrier sheet 413 also has connecting pads 3411 and connecting pad connecting holes 3631. The connecting pads 3411, connecting pad connecting holes 3631, the carrier sheet 413, and the functional structure 213 form a material connection. It should be noted that, as Figure 4 The fifth connection pad 343 shown can form a material connection with the functional structure 213 through the second connection hole 3212, or it can be an independent structure, that is, it does not form a connection with the inside of the chip, and is used for etching blocking or redundancy, such as... Figure 1 The second connecting pad 342 is shown.

[0043] The aforementioned stacked chip D400 includes a first etchable material etching barrier layer 95 and / or the connection pad 3411, wherein the connection pad 3411 is made of a material that the first etchable material cannot etch. When the first etchable material etches to the barrier layer or the non-etchable material, on the one hand, the ultra-deep hole etching stops, and on the other hand, different etching signals are generated. The etching machine can determine whether the etching has stopped by using these different etching signals. Figure 2 The first etching material etching barrier layer 95 in the process uses a barrier material to perform the first etching material etching barrier; Figure 1 The first connection pad 341 and the second connection pad 342 of the third layer chip 403 can also be used as the first etching material and the etching barrier material. Figure 4This illustrates a method where the first-layer chip 401 uses a connecting pad as an etching barrier material. When the second deep-filled via 332 is etched to the fifth connecting pad 343, the etching of the via terminates. At this time, the second external connecting pad 372 is intelligently connected to the first-layer chip 401. The first external connecting pad 371 can be connected to the second-layer chip 402 and the third-layer chip 403.

[0044] The aforementioned connection pad 3411 may be either non-etchable or etchable by the second etch material. If the connection pad 3411 is made of a material that the second etch material cannot etch (i.e., the second etch material cannot etch), the filling ultra-deep via sequentially connects to the chip functional structure 213 through the connection pad 3411 and the connection pad connection hole 3631. If the connection pad 3411 is made of a material that the second etch material can etch (i.e., the second etch material can etch), the portion of the connection pad 3411 that forms a cavity is etched away by the second etch material, and then, through deposition and / or growth of material, a connection is formed between the functional structure and the external environment. Figure 1 For example, if the first connecting pad 341 and the second connecting pad 342 are not etchable by the second etching material, then the first connecting pad 341 and the connecting pad connection hole 3631 are connected to the third functional structure 203 of the chip, and the functional structure is connected to the outside through the first filled ultra-deep via 331; the second connecting pad 342 has no connecting pad connection hole and is not connected to the third functional structure 203 of the chip. If the first connecting pad 341 and the second connecting pad 342 are etchable by the second etching material, taking the first connecting pad 341 as an example, the first connecting pad 341 is etched away by the second etching material to form a cavity, and material is deposited and / or grown, forming the functional structure connected to the outside through the first filled ultra-deep via 331; the advantage of doing so is that the material consistency of the structure can be better maintained; the second connecting pad 342 has no connecting pad connection hole and is not connected to the third functional structure 203 of the chip. It should be understood that in this embodiment, there are three functional structures 213, which are named first functional structure 201, second functional structure 202 and third functional structure 203 respectively for ease of description.

[0045] It should be noted that if the functional structure 213 is a microfluidic pathway, because the fluid (gas or liquid) needs to be controlled through the ultra-deep orifice, cavity, connecting hole, and functional structure, the ultra-deep orifice, cavity, and connecting hole are connected by maintaining fluid voids. For example... Figure 2 As shown, Figure 2 (A) is a schematic diagram of the structure in which the filling material forms a solid connection. Figure 2Diagram (B) is a schematic diagram of the structure retaining fluid void connections. Taking the first layer chip 401 as an example, the first filled ultra-deep via 331 and the second filled ultra-deep via 332, the first cavity 5011 and the second cavity 5012, the first connecting hole 3211 and the second connecting hole 3212 respectively form fluid void connections with the first functional structure 201 of the microfluidic pathway. Finally, it forms connections with the first external connecting pad 371 and the second external connecting pad 372.

[0046] To preserve fluid-filled void connections, the deposited and / or grown material must not block ultra-deep holes, cavities, or connecting holes; or further cleaning is required to remove any potential blockages, and hole enlargement may be necessary. In particular, for the first connecting hole 3211, the second connecting hole 3212, and the third connecting hole 3221, which already have filling material, a second or third etching material for etching cavities can be used for etching.

[0047] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0048] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for achieving three-dimensional stacked chip interconnection through a sacrificial layer, characterized in that, Includes the following steps: A multilayer chip with at least two layers to be stacked is provided, each chip layer including a functional structure and at least one easily bondable layer; wherein, at least one chip layer also includes a sacrificial layer and a via, and the sacrificial layer, the via and the functional structure form a material connection; The multilayer chips are aligned, stacked, and bonded according to functional requirements to form a stacked chip. The stacked multilayer chip is photolithographically etched using a first mask and etched using a first etching material to form an ultra-deep hole that penetrates at least part of the chip layers. The sacrificial layer is etched using a second etching material to form a cavity that can cover the connection hole; Deposit and / or grow materials to form functional structures that connect to the outside by filling ultra-deep pores.

2. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 1, characterized in that, The sacrificial layer is made of a non-conductive material.

3. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 1, characterized in that, The second etching material is an isotropic etching material.

4. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 1, characterized in that, The functional structure includes one or more functional structures in integrated circuits, electronic devices, optical devices, electronic circuits, optical pathways, microfluidic pathways, detectors, and microelectromechanical systems.

5. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 1, characterized in that, The stacked chip also includes a carrier wafer, which includes one or more of the following composites: silicon / germanium / compound semiconductor bare die, silicon / germanium / compound semiconductor with completed functional structure fabrication, three-dimensional stacked chip with completed interlayer interconnection, diamond, silicon dioxide, glass, ceramic, PCB board, blue film, carrier tape and protective adhesive.

6. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 1, characterized in that, At least one layer of the chip further includes a connection pad, the connection pad having a connection pad connection hole, the connection pad forming a material connection with the functional structure through the connection pad connection hole.

7. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 1, characterized in that, The stacked chip also includes a first etching material etching barrier layer and / or a connection pad, wherein the connection pad is made of a material that the first etching material cannot etch.

8. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 6, characterized in that, If the connecting pad is made of a material that cannot be etched by the second etching material, then the filling ultra-deep via is connected to the functional structure of the chip in sequence through the connecting pad and the connecting pad connecting hole; If the connecting pad is made of a material that can be etched by the second etching material, the portion of the connecting pad that forms a cavity is etched away by the second etching material, and the functional structure is connected to the outside by deposition and / or growth of material to fill the ultra-deep hole.

9. The method for achieving three-dimensional stacked chip interconnection via a sacrificial layer according to claim 4 or 8, characterized in that, When the functional structure is a microfluidic pathway, the ultra-deep orifice, cavity and connecting hole are connected and fluid void connection is maintained, and / or the ultra-deep orifice, connecting pad and connecting pad connecting hole are connected and fluid void connection is maintained.

10. The method for achieving three-dimensional stacked chip interconnection through a sacrificial layer according to claim 9, characterized in that, The retention fluid void connection includes etching the connection hole and / or connection pad connection hole with a second or third etching material.

Images