Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device including a tapered spacer and a method of manufacturing the same. The semiconductor device includes: a wire contact plug and a conductive pattern spaced apart from each other in a first direction; a wire disposed over the wire contact plug and extending in a second direction perpendicular to the first direction; and a spacer structure configured to contact a sidewall of the wire and a sidewall of the wire contact plug, and configured such that a width of an upper portion of the spacer structure is smaller than a width of a lower portion of the spacer structure.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority and benefit to Korean Patent Application No. 10-2024-0114380, filed on August 26, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The techniques and embodiments disclosed herein generally relate to semiconductor devices and methods of manufacturing the same, and more specifically, to semiconductor devices including tapered spacers and methods of manufacturing the same. Background Technology

[0004] As the integration level of semiconductor devices increases, the design difficulty of integrated circuits (ICs) increases exponentially.

[0005] In the development of semiconductor devices, the number of devices contained in a unit chip area has increased rapidly, while the size of each device has gradually decreased. The high integration of semiconductor devices has led to an increase in the complexity of integrated circuit (IC) processing and IC manufacturing.

[0006] Multiple conductive pattern structures and wires can be arranged within the insulating layer included in a semiconductor device. Reducing the spacing between the multiple conductive pattern structures and wires may increase leakage current and cause interference between the conductive pattern structures and wires. Summary of the Invention

[0007] Various embodiments of this disclosure relate to a semiconductor device that can readily form one or more conductive patterns by modifying the spacing structure adjacent to one or more wires.

[0008] According to one embodiment of the present disclosure, a semiconductor device may include: wire contact plugs and conductive patterns spaced apart from each other in a first direction; wires disposed on the wire contact plugs and extending in a second direction perpendicular to the first direction; and a spacer structure configured to contact the sidewalls of the wires and the sidewalls of the wire contact plugs, such that the width of the upper portion of the spacer structure is smaller than the width of the lower portion of the spacer structure.

[0009] In some embodiments of this disclosure, the spacing structure may include: a first spacer configured to contact the sidewall of a wire and the sidewall of a wire contact plug; a second spacer configured to contact the first spacer and configured such that the width of the upper portion of the second spacer is less than the width of the lower portion of the second spacer; and a third spacer disposed between the second spacer and the conductive pattern.

[0010] In some embodiments, the first spacer may include a material having a lower dielectric constant (lower K) than silicon nitride.

[0011] In some embodiments, the first spacer may include silicon carbide (SiC), silicon oxycarbonate (SiCO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), boron nitride (BN), or a combination thereof.

[0012] In some embodiments, the second spacer may include silicon oxide.

[0013] In some embodiments, silicon oxide may be doped with either nitrogen or fluorine.

[0014] In some embodiments, the third spacer may include silicon carbide (SiC), silicon oxycarbonate (SiCO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), boron nitride (BN), or combinations thereof.

[0015] In some embodiments, the conductive pattern may be configured such that the width of the lower portion of the conductive pattern is smaller than the width of the upper portion of the conductive pattern.

[0016] In some embodiments, the semiconductor device may further include a storage element disposed on a conductive pattern.

[0017] In some embodiments, the conductive pattern may include: a lower plug comprising polysilicon; an ohmic contact layer disposed on the lower plug and comprising a metal silicide; and an upper plug disposed on the ohmic contact layer and comprising a metallic material.

[0018] In some embodiments, the semiconductor device may further include a first impurity region and a second impurity region formed in a substrate, wherein a wire contact plug is connected to the first impurity region.

[0019] In some embodiments, the conductive pattern may be connected to the second impurity region.

[0020] In some embodiments, the first impurity region may be disposed between two adjacent embedded word lines.

[0021] In some embodiments, the wires may be bit lines; the conductive pattern may be a storage node contact plug.

[0022] According to another embodiment of this disclosure, a semiconductor device may include: a plurality of conductive lines spaced apart from each other on a substrate; a plurality of conductive contact plugs disposed below the conductive lines; a plurality of conductive patterns disposed between the conductive lines; and a plurality of spacer structures disposed between the conductive patterns and the conductive lines. Each spacer structure may include: a first spacer configured to contact the sidewalls of the conductive lines and the sidewalls of the conductive contact plugs; a second spacer configured to contact the first spacer and configured such that the width of the upper portion of the second spacer is smaller than the width of the lower portion of the second spacer; and a third spacer disposed between the second spacer and the conductive patterns.

[0023] In some embodiments, the semiconductor device may further include plug isolation layers disposed between conductive patterns, wherein the conductive patterns and plug isolation layers are alternately arranged along the direction in which the wires extend.

[0024] In some embodiments, the plug isolation layer may include an insulating material.

[0025] In some embodiments, the first spacer may include a material having a lower dielectric constant (lower K) than silicon nitride.

[0026] In some embodiments, the first spacer may include silicon carbide (SiC), silicon oxycarbonate (SiCO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), boron nitride (BN), or a combination thereof.

[0027] In some embodiments, the second spacer may include silicon oxide.

[0028] In some embodiments, silicon oxide may be doped with either nitrogen or fluorine.

[0029] In some embodiments, the third spacer may include silicon carbide (SiC), silicon oxycarbonate (SiCO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), boron nitride (BN), or combinations thereof.

[0030] According to another embodiment of this disclosure, a semiconductor device may include: wire contact plugs and conductive patterns spaced apart from each other in a first direction; wires disposed on the wire contact plugs and extending in a second direction perpendicular to the first direction; a first spacer configured to contact the sidewalls of the wires and the sidewalls of the wire contact plugs; a second spacer that is tapered and configured to contact the first spacer; a third spacer disposed between the second spacer and the conductive pattern; and a first impurity region and a second impurity region formed in a substrate, wherein the wire contact plugs are connected to the first impurity region.

[0031] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and intended to provide further description of the claimed embodiments of this disclosure. Attached Figure Description

[0032] The above and other features and advantages of embodiments of this disclosure will become apparent from the accompanying drawings and the following detailed description.

[0033] Figure 1 This is a plan view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0034] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A cross-sectional view of a semiconductor device taken by line A-A'.

[0035] Figure 3 This illustrates some embodiments according to the present disclosure. Figure 1 A cross-sectional view of a semiconductor device taken by line B-B'.

[0036] Figures 4 to 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0037] This disclosure provides embodiments and examples of semiconductor devices including tapered spacers and methods of manufacturing the same, which can be used to substantially solve one or more technical or engineering problems and mitigate limitations or disadvantages encountered in other semiconductor devices. Some embodiments of this disclosure relate to a semiconductor device capable of readily forming one or more conductive patterns by improving the tapered spacer structure adjacent to one or more conductors. In view of the above-mentioned problems, the semiconductor device according to some embodiments of this disclosure utilizes tapered spacers between conductors and conductive patterns to facilitate the formation of such conductive patterns. In this semiconductor device, a first spacer directly contacting the sidewall of the conductor does not contain nitride, thereby preventing conductor nitriding. In this semiconductor device, the first spacer comprises a low dielectric constant (low K) material, and a second spacer comprising a tapered silicon oxide layer is formed on the first spacer, thereby improving the parasitic capacitance between the conductor and the conductive pattern.

[0038] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts. Although various modifications and alternatives may be made to the embodiments of the present disclosure, specific embodiments are shown in the drawings by way of example only. However, these embodiments should not be construed as being limited to the embodiments described herein.

[0039] The embodiments will now be described in conjunction with the accompanying drawings. However, it should be understood that these embodiments are not limited to the specific embodiments, but include various modifications, equivalents, and / or alternatives to the embodiments. The embodiments of this disclosure can provide various beneficial effects, whether directly or indirectly manifested.

[0040] The accompanying drawings are not necessarily drawn to scale. In some examples, the scale of at least some structures in the drawings may be exaggerated to clearly illustrate the features of the embodiments. When a multilayer structure with two or more layers is disclosed in the drawings or detailed description, the relative positional relationship or arrangement of the layers only reflects a particular embodiment, and the scope or spirit of this disclosure is not limited thereto. It should be noted that the relative positional relationship or arrangement of the layers may also be changed as needed. Furthermore, the drawings or detailed description of the multilayer structure may not reflect all the layers present in a particular multilayer structure (e.g., one or more additional layers may exist between the two layers shown). As a specific example, when the first layer in a multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure with one or more other layers between the first and second layers or between the first layer and the substrate.

[0041] The following describes in detail, with reference to the accompanying drawings, some embodiments of semiconductor devices and methods of manufacturing thereof according to the present disclosure.

[0042] Figure 1 This is a plan view illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0043] refer to Figure 1 The semiconductor device 10 may include at least one embedded word line 17, at least one conductor 20, at least one spacer structure (SP), at least one plug isolation layer 26, and at least one conductive pattern 27. Figure 1 The positional relationship between the embedded word line 17, the conductor 20, the spacer structure (SP), the plug isolation layer 26, and the conductive pattern 27 is shown.

[0044] The semiconductor device 10 may include a plurality of memory cells. Each memory cell may include a cell transistor, which includes an embedded word line 17, a wire 20, and a memory element.

[0045] The buried word line 17 can be used as the gate of a unit transistor, can be disposed below the conductor 20, and can extend along a first direction (D1) perpendicular to a second direction (D2) in which the conductor 20 extends. In some embodiments, the buried word line 17 and the conductor 20 can be disposed in the same semiconductor substrate, and the buried word line 17 can be disposed below the conductor 20 relative to one surface of the semiconductor substrate.

[0046] The conductor 20 may include a metallic material and may be located between the spacer structure (SP) and the conductive pattern 27 or between the spacer structure (SP) and the plug isolation layer 26.

[0047] In some embodiments, wire 20 may be a bit line of a semiconductor device.

[0048] The spacer structure (SP) may extend in the same direction (D2) as the conductor 20 and may include insulating material.

[0049] A plug isolation layer 26 may be formed between adjacent conductors 20, and conductive patterns 27 may be isolated from each other by the plug isolation layer 26. The plug isolation layer 26 and conductive patterns 27 may be arranged alternately along a second direction (D2) extending along the conductors 20. In some embodiments, the conductive patterns 27 may be storage node contact plugs.

[0050] The conductive pattern 27 electrically interconnects the memory element disposed in the semiconductor substrate with the impurity region. The conductive pattern 27 may comprise multiple layers of conductive material. (Reference) Figure 1 The conductive patterns 27 and wires 20 may be arranged in an alternating manner along the first direction D1, with the spacer structure SP filling the space between adjacent pairs of conductive patterns 27 and wires 20. A single spacer structure SP may fill each such space between adjacent pairs of conductive patterns 27 and wires 20.

[0051] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A cross-sectional view of a semiconductor device taken by line A-A'. Figure 3 This illustrates some embodiments according to the present disclosure. Figure 1 A cross-sectional view of a semiconductor device taken by line B-B'.

[0052] Reference Figures 1 to 3 The structure of semiconductor device 10 is described in detail.

[0053] Semiconductor device 10 may include substrate 11.

[0054] Substrate 11 can be any material suitable for semiconductor processing. For example, substrate 11 may include, but is not limited to, silicon. Substrate 11 may also include other semiconductor materials, such as germanium. Substrate 11 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate like GaAs (gallium arsenide). Substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0055] In some embodiments, the substrate 11 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiple layers thereof.

[0056] At least one active region 13, at least one first device isolation layer 12a and at least one second device isolation layer 12b may be formed in the substrate 11.

[0057] The active region 13 may be defined by a first device isolation layer 12a and a second device isolation layer 12b. The device isolation layers (12a, 12b) may be formed using a shallow trench isolation (STI) process and may contain insulating material.

[0058] A first impurity region 14a and a second impurity region 14b can be formed on the active region 13.

[0059] The first impurity region 14a and the second impurity region 14b can be used as the source / drain regions of a unit transistor. Both the first impurity region 14a and the second impurity region 14b can include N-type impurities, such as arsenic (As) or phosphorus (P).

[0060] refer to Figure 3 A first trench (T1) may be formed in the substrate 11. A gate insulating layer 16, a buried word line 17, and a gate capping layer 18 may be formed in the first trench (T1).

[0061] The gate insulating layer 16 may be conformally formed along the bottom surface and sidewalls of each first trench (T1). Buried word lines 17 may be formed on the gate insulating layer 16 to fill the lower portion of the first trench (T1).

[0062] A gate capping layer 18 may be formed on the top surface of the buried word line 17. In some embodiments, the sidewalls of the gate capping layer 18 may be covered by a gate insulating layer 16, but in other embodiments, the gate capping layer 18 may be located on the gate insulating layer 16 covering the upper sidewall of the first trench (T1) to fill the upper portion of the first trench (T1). The first trench (T1) may also be referred to as a gate trench. For example, the gate insulating layer 16 may include a high dielectric constant (high K) material, an oxide material, a nitride material, an oxide oxynitride material, or a combination thereof. The gate capping layer 18 may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0063] The buried word line 17 may comprise a low-resistance metallic material. The buried word line may comprise at least one of titanium nitride, tungsten, and molybdenum. According to one embodiment, the buried word line 17 may be formed by stacking titanium nitride and tungsten. According to another embodiment, the buried word line 17 may be formed solely of titanium nitride. The buried word line 17 may be used as the gate of a unit transistor. The buried word line 17 may be referred to as a buried gate electrode.

[0064] The hard mask layer 15 can be used as an etch stop layer for forming the first trench (T1), and after the first trench (T1) is formed, a portion or area of ​​the hard mask layer may remain, which can be referred to as the residual area of ​​the hard mask layer 15. The hard mask layer 15 can be patterned by mask patterning. The hard mask layer 15 may contain, for example, silicon oxide. In addition, for example, the hard mask layer 15 may contain tetraethyl orthosilicate (TEOS).

[0065] A wire contact plug 19 may be formed within the substrate 11. The wire contact plug 19 may be connected to the first impurity region 14a and may be formed within the contact hole (T2).

[0066] The contact hole (T2) can be a region for forming a wire contact plug 19 configured to connect the wire 20 and the first impurity region 14a. The contact hole (T2) can be formed by etching a hard mask layer 15.

[0067] The first impurity region 14a may be exposed through the contact hole (T2). In some embodiments, the wire contact plug 19 may include a conductive material, such as polysilicon or a metallic material.

[0068] refer to Figure 2 Viewed from a direction parallel to the second direction (D2), the width of the wire contact plug 19 may be smaller than the width of the contact hole (T2).

[0069] A wire 20 can be formed on the wire contact plug 19. Then, a wire hard mask 21 can be formed on the wire 20. The stacked structure of the wire contact plug 19, the wire 20 and the wire hard mask 21 can be referred to as a wire structure.

[0070] The conductor 20 may be in the form of a line extending along the second direction (D2). The conductor 20 may contain a conductive material, such as a metal. The conductor hard mask 21 may contain an insulating material.

[0071] The spacer structure (SP) formed along the two sidewalls of the conductor 20 may include multiple layers.

[0072] More specifically, the spacer structure (SP) may include a first spacer 22, a second spacer 24, and a third spacer 25.

[0073] The spacer structure (SP) electrically isolates the conductor 20 from the adjacent conductive pattern 27.

[0074] The first spacer 22 may be arranged along the side of the wire contact plug 19, the wire 20, and the wire hard mask 21, and may fill the bottom and side surfaces of the spacer 23 around the gap. The first spacer 22 may comprise a material with a dielectric constant similar to or higher than that of the second spacer 24.

[0075] The first spacer 22 may be made of or include a material having a lower dielectric constant (lower K) than silicon nitride to reduce parasitic capacitance between the wire structure and the conductive pattern.

[0076] In some embodiments, the first spacer 22 may contain impurities. For example, the first spacer 22 may contain carbon as an impurity. For example, the first spacer 22 may contain silicon carbide (SiCO).

[0077] According to some embodiments, the first spacer 22 may include silicon carbide (SiC), silicon carbide (SiCO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), boron nitride (BN), or combinations thereof. The material included in the first spacer 22 may have a lower dielectric constant (lower K) than silicon nitride, thereby reducing the parasitic capacitance between the wire structure and the conductive pattern 27. Importantly, reducing parasitic capacitance improves the sensing margin of the semiconductor device.

[0078] Furthermore, according to some embodiments of this disclosure, the first spacer 22 in contact with the sidewall of the conductor structure may not include silicon nitride.

[0079] Since the first spacer 22 does not contain silicon nitride, nitriding of the metallic material (e.g., tungsten) contained in the wire 20 is prevented.

[0080] For example, the gap-filling spacer 23 may be a layer comprising silicon nitride, the dielectric constant of which may be higher than that of the first spacer 22. The gap-filling spacer 23 may be a layer used to gap-fill the area of ​​the non-wire contact plug 10 within the contact hole. The gap-filling spacer 23 may be an insulating plug. The first spacer 22 may be configured to surround the bottom and sides of the gap-filling spacer 23.

[0081] The second spacer 24 may be disposed on the first spacer 22. The first spacer 22 may contact the bottom surface and the side surface of the second spacer 24.

[0082] The second spacer 24 may be tapered, with its upper width being smaller than its lower width. The second spacer 24 may be shaped to extend from the conductor hard mask layer 21 toward the conductor 20. Furthermore, the width of the area of ​​the second spacer 24 adjacent to the conductor hard mask layer 21 may be smaller than the width of the area adjacent to the conductor 20.

[0083] The second spacer 24 may include silicon oxide. For example, the second spacer 24 may include nitrogen-doped silicon oxide, fluorine-doped silicon oxide, or silicon oxide doped with both nitrogen and fluorine.

[0084] Because the second spacer 24 has a tapered shape, the formation process of the conductive pattern 27 can be simplified. In addition, because the second spacer 24 has a tapered shape, the thickness of the dielectric material (e.g., silicon oxide and low-k material) layer between the wire 20 and the conductive pattern 27 can be increased, thereby reducing the parasitic capacitance of the wire 20.

[0085] The third spacer 25 may be disposed on the second spacer 24 and may have a shape that is inclined along the side of the second spacer 24.

[0086] In some embodiments, the third spacer 25 may comprise silicon nitride or a material with a dielectric constant (low K value) lower than that of silicon nitride. The material included in the third spacer 25 may include, for example, silicon carbide (SiC), silicon oxycarbide (SiCO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), boron nitride (BN), or combinations thereof.

[0087] Materials with a dielectric constant lower than (lower K) silicon nitride are referred to hereinafter as low-K materials. In some embodiments, the spacer structure (SP) may have a KOK stack structure (low-K-oxide-low-K) or a KON stack structure (low-K-oxide-nitride).

[0088] According to some embodiments, a seed nitride layer may be formed on the sidewalls of the conductor 20 and the conductor hard mask 21 before the first spacer 22 is formed to contact the sidewalls of the conductor 20. The first spacer 22 may then be formed on the seed nitride layer.

[0089] The formation of a seed nitride layer maintains a constant thickness of the first spacer 22 formed on the sidewalls of the conductor 20 and the conductor hard mask 21. Meanwhile, since the second spacer 24 is formed in a tapered shape on the first spacer 22, it facilitates subsequent processes for forming conductive patterns.

[0090] When performing a deposition process on a target object using a material with a dielectric constant lower than silicon nitride (lower K) (such as SiCO), overhangs may occur due to the difference in deposition rates between the top and side surfaces of the target object.

[0091] More specifically, when a seed nitride layer is not formed, in processes that deposit materials with dielectric constants lower than (lower K) silicon nitride (such as SiCO), the deposition rates between the wires and the wire hard mask may differ, which could lead to overhangs.

[0092] According to some embodiments of this disclosure, the spacer structure SP may include a first spacer 22 and a second spacer 24, the first spacer 22 comprising a material with a dielectric constant lower than silicon nitride (low K), and the second spacer 24 comprising silicon oxide, thereby preventing the conductor 20 from sag.

[0093] The third spacer 25 may include a material that is etch-selective relative to the second spacer 24. For example, in some embodiments, the second spacer 24 may include silicon oxide, while the third spacer 25 may include silicon nitride.

[0094] refer to Figure 1 and Figure 3 A plug isolation layer 26 may be formed on the third spacer 25. The plug isolation layer 26 may be formed between adjacent conductor structures in the first direction (D1).

[0095] The plug isolation layer 26 can be formed between conductive patterns 27 that are adjacent to each other in the second direction (D2).

[0096] The plug isolation layer 26 and the conductive pattern 27 may be alternately arranged between adjacent conductor structures in the first direction (D1).

[0097] The plug isolation layer 26 may include silicon nitride or a material having a lower dielectric constant (lower K) than silicon nitride.

[0098] The conductive pattern 27 may be disposed between adjacent conductor structures. The conductive pattern 27 may include an upper plug 27a, an ohmic contact layer 27b, and a lower plug 27c.

[0099] The upper plug 27a may contain a conductive material, such as a metal. The ohmic contact layer 27b may contain, for example, a metal silicide. The lower plug 27c may contain a conductive material such as polysilicon.

[0100] The conductive pattern 27 may have an inverted cone shape, wherein the width of the upper part of the conductive pattern 27 is greater than the width of the lower part of the conductive pattern 27.

[0101] The spacer structure (SP) is formed into a cone shape, such that the conductive pattern 27 between the spacer structures (SP) is formed into an inverted cone shape, thereby ensuring that the upper region of the conductive pattern 27 is used to arrange the storage element 28.

[0102] Furthermore, the spacing (distance) between the lower plug 27c of the conductive pattern 27 and the conductor is ensured, thereby reducing parasitic capacitance. That is, the spacing (distance) between the lower plug 27c and the conductor is intentionally maintained or controlled to have sufficient width to ensure a significant reduction and / or complete prevention of parasitic capacitance, thereby improving the electrical performance of the device.

[0103] Storage element 28 may include, for example, a capacitor containing a storage node. The storage node may be cylindrical or tubular, and according to one embodiment, may be formed from a combination of cylindrical and tubular shapes. Furthermore, the capacitor containing the storage node may also include a dielectric layer and electrode nodes.

[0104] Figures 4 to 16This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0105] Figures 4 to 16 It shows along Figure 1 The cross-sectional view of the semiconductor device taken by lines A-A' and B-B'.

[0106] refer to Figure 4 A device isolation layer 12 is formed on the substrate 11. The device isolation layer 12 may define a plurality of active regions 13.

[0107] The device isolation layer 12 can be formed by a shallow trench isolation (STI) process. The device isolation layer 12 can be formed by etching at least a portion of the substrate 11 to form a trench and filling the trench formed by the etching with an insulating material (e.g., silicon oxide, silicon nitride, or a combination thereof).

[0108] The buried word line structure formed in the substrate 11 may include a gate insulating layer 16, a buried word line 17, and a gate capping layer 18. More specifically, the buried word line structure may include a first trench (T1) formed in the substrate 11, a gate insulating layer 16 formed on the bottom and sides of the first trench (T1), a buried word line 17 formed on the gate insulating layer 16 and filling at least a portion of the first trench (T1), and a gate capping layer 18 formed on the buried word line 17.

[0109] Forming the buried word line structure may include forming a first trench (T1) in the substrate 11. The first trench (T1) may have a line shape passing through the active region 13 and the impurity region 14. The first trench (T1) may be formed by an etching process after forming an etching mask on the substrate.

[0110] A hard mask layer 15A can be formed as an etch barrier layer for forming the first trench (T1), and the hard mask layer 15A can be patterned by an etch mask to form the first trench (T1).

[0111] For example, hard mask layer 15A may include silicon oxide or TEOS (tetraethyl orthosilicate).

[0112] To define the active region 13, a device isolation layer 12 may be formed, and an impurity region 14 may be formed in at least a portion of the active region 13.

[0113] Impurity region 14 can be formed after the embedded word line structure is formed. Impurity region 14 can be formed by etching after ion implantation and doping processes are performed in active region 13.

[0114] Multiple impurity regions 14 may be doped with impurities of the same conductivity type. These impurity regions 14 may then become the source / drain regions of a unit transistor. These impurity regions 14 may be disposed on different active regions 13 and may be separated from each other by a first trench (T1).

[0115] A gate insulating layer 16 may be formed at the bottom and sides of the first trench (T1). The gate insulating layer 16 may be formed after surface damage caused by etching of the first trench (T1) has been repaired.

[0116] The gate insulating layer 16 can be formed by oxidizing the bottom and sides of the first trench (T1). In other embodiments, the gate insulating layer 16 can be formed by a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0117] For example, the gate insulating layer 16 may include a high-K material, an oxide, a nitride, or a combination thereof.

[0118] High-K materials may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or combinations thereof. In another embodiment, high-K materials may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or combinations thereof.

[0119] Buried word lines 17 can be formed on the gate insulating layer 16. The buried word lines 17 can be formed by forming a conductive layer that fills the first trench (T1) and then performing a recess process.

[0120] For example, the resurfacing process may include an etch-back process and a chemical mechanical polishing (CMP) process. For instance, in some embodiments, in the resurfacing process, a CMP process may be performed after a first etch-back process, followed by a second etch-back process. The etch-back process may be repeated after the CMP process.

[0121] The embedded word line 17 is shaped to fill at least a portion of the first trench (T1). The material of the embedded word line 17 can be a metal, a metal nitride, or a combination thereof. For example, the embedded word line 17 may include molybdenum (Mo), tungsten (W), or titanium nitride (TiN). In some embodiments, the embedded word line 17 may include a stacked structure comprising layers of a material arbitrarily selected from molybdenum (Mo), tungsten (W), and / or titanium nitride (TiN).

[0122] After the buried word line 17 is formed, a gate capping layer 18 may be formed on the buried word line 17. The gate capping layer 18 may include an insulating material and may be a region that fills the area in the first trench (T1) where the buried word line 17 is not formed.

[0123] The gate capping layer 18 may include, for example, silicon nitride, silicon oxide, or a stacked structure that may include silicon nitride and silicon oxide.

[0124] The surface of the gate capping layer 18 can be at the same height as the hard mask layer 15A, and the height of the gate capping layer 18 can be made the same as the height of the hard mask layer 15A through CMP process.

[0125] like Figure 5 As shown, a contact hole (T2) can be formed in the substrate 11. The contact hole (T2) can be the region forming the wire contact plug 19. The contact hole (T2) can occupy the region between two adjacent second impurity regions 14b. The contact hole (T2) can be formed by etching the hard mask layer 15A. The planar shape of the contact hole (T2) can be circular or elliptical. After the contact hole (T2) is formed, a portion of the hard mask layer 15 may remain.

[0126] A portion of the substrate 11 can be etched through the contact hole (T2), exposing a portion of the active region 13. In the etching process forming the contact hole (T2), at least a portion of the first impurity region 14a, a portion of the device isolation layer 12, and a portion of the gate capping layer 18 can be removed. More specifically, the first impurity region 14a can be recessed through the contact hole (T2) and exposed to a predetermined depth.

[0127] With the formation of the contact hole (T2), the device isolation layer 12a with some etched areas and the device isolation layer 12b with some unetched areas can be distinguished from each other. More specifically, the device isolation layer 12a with some etched areas can be disposed on both sides of the first impurity region 14a.

[0128] like Figure 6 As shown, a pre-contact plug 19A can be formed in the contact hole (T2). The pre-contact plug 19A can be formed to fill the interior of the contact hole (T2).

[0129] The pre-contact plug 19A may be formed by deposition or selective epitaxial growth. The pre-contact plug 19A may comprise at least one of polycrystalline silicon and monocrystalline silicon.

[0130] like Figure 7 As shown, a conductive wire layer 20A and a hard wire layer 21A can be sequentially formed on the pre-contact plug 19A and the residual hard mask layer 15.

[0131] The conductive layer 20A may comprise a metallic material. For example, the conductive layer 20A may comprise tungsten. According to another embodiment, the conductive layer 20A may comprise a stacked structure of metal and metal nitride. For example, the conductive layer 20A may comprise a stacked structure of tungsten and titanium nitride. Titanium nitride may be used as a barrier metal between the pre-contact plug 19A and the tungsten layer.

[0132] The conductor hard mask layer 21A may contain an insulating material that has etch selectivity for the conductor conductive layer 20A and the pre-contact plug 19A. For example, the conductor hard mask layer 21A may contain silicon nitride.

[0133] like Figure 8 As shown, the conductor 20 and the conductor hard mask 21 can be formed by etching the conductor hard mask layer 21A and the conductor conductive layer 20A. In addition, the conductor contact plug 19 can be formed by etching the pre-contact plug 19A with the same width as the conductor 20.

[0134] Since the wire contact plug 19 formed by the etching process has the same width as the wire 20, a first opening (O1) can be formed on both sides of the wire contact plug 19. The first opening (O1) can be a gap filled by the gap-filling spacer 23.

[0135] The wire contact plug 19, the wire 20, and the wire hard mask 21 can be collectively referred to as the wire structure. This wire structure can have along... Figure 1 The shape extending in the second direction (D2) is shown.

[0136] like Figure 9 As shown, the first spacer layer 22A can be formed on the two sidewalls of the wire contact plug 19, the bottom and sidewalls of the second trench (T1) with the opening portion (O1), and the sidewalls of the hard mask layer 15, the wire 20 and the wire hard mask 21.

[0137] The first spacer layer 22A can also be formed on the wire hard mask 21.

[0138] The first spacer layer 22A may comprise a low-k material, such as a material with a dielectric constant lower than (or even lower K) silicon oxide or silicon nitride. For example, the first spacer layer 22A may comprise SiCO, which is a carbon-containing silicon-based material.

[0139] The first spacer layer 22A can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or cyclic chemical vapor deposition (CyclicCVD). For example, a deposition cycle based on silicon source gas, carbon source gas, and oxygen source gas can be performed to form the first spacer layer 22A containing SiCO.

[0140] like Figure 10 As shown, a gap-filling spacer layer 23A may be formed on the first spacer layer 22A. The gap-filling spacer layer 23A may contain a material with a dielectric constant higher than (higher K) that of the first spacer layer 22A. For example, the gap-filling spacer layer 23A may contain silicon nitride.

[0141] like Figure 11 As shown, the gap-filling spacer 23 can be formed by recessing the gap-filling spacer layer 23A. The gap-filling spacer 23 can be formed by silicon nitride deposited by etching back. The first opening portion (O1) can be filled by the gap-filling spacer 23.

[0142] like Figure 12 As shown, after the gap-filling spacer 23 is formed, a second spacer layer 24A can be formed on the gap-filling spacer 23 and the first spacer layer 22A.

[0143] The second spacer layer 24A can be referred to as a conical spacer layer, and the width of the lower part of the second spacer layer 24A can be greater than the width of the upper part of the second spacer layer 24A.

[0144] The second spacer layer 24A can be formed along the two sidewalls of the conductor structure and can be formed to directly contact the top surface of the gap-filling spacer 23 and the surface of the first spacer layer 22A.

[0145] For example, the second spacer layer 24A may include silicon oxide. Depending on the semiconductor manufacturing process, the second spacer layer 24A may include nitrogen-doped silicon oxide, fluorine-doped silicon oxide, or silicon oxide doped with both nitrogen and fluorine.

[0146] The second spacer layer 24A can be formed by atomic layer deposition (ALD) process and can be deposited in cycles based on silicon source gas and oxygen source gas.

[0147] More specifically, the second spacer layer 24A may include a deposition suppression step in the atomic layer deposition (ALD) process. This deposition suppression step may be a step of selectively depositing the applied reactants.

[0148] After the reactants are injected, if a deposition inhibition material (such as NF3, N2, NH3, F2, etc.) is used in the deposition inhibition step, the reactants can be prevented from depositing on the top of the pattern.

[0149] When a deposition inhibition material is applied to the top of the pattern, it prevents subsequent reactant material from depositing within the pattern. By performing multiple cycles of the deposition inhibition step, a conical insulating layer can be formed, resulting in a thinner deposition of reactant material at the top of the conical insulating layer and a thicker deposition at the bottom.

[0150] like Figure 13 As shown, a portion of the second spacer layer 24A can be etched to form the second spacer 24.

[0151] The second spacer layer 24A may have etch selectivity relative to the first spacer layer 22A, and the second spacer 24 may be formed by an etch-back process.

[0152] The second spacer 24 may have a tapered shape, wherein the width of the upper part of the second spacer 24 is smaller than the width of the lower part of the second spacer 24.

[0153] like Figure 14As shown, a third spacer layer 25A can be formed on the second spacer 24. The third spacer layer 25A can be formed conformally with the second spacer 24. The third spacer layer 25A may contain a low-k material with a dielectric constant lower than (lower K) silicon nitride, or may contain silicon nitride. For example, the third spacer layer 25A can be formed by atomic layer deposition (ALD).

[0154] like Figure 15 As shown, a second opening portion (O2) may be formed. Forming the second opening portion (O2) may include etching at least a portion of the third spacer layer 25A, a portion of the hard mask layer 15, a portion of the first spacer layer 22A, a portion of the second impurity region 14b, and a portion of the device isolation layer 12a.

[0155] Each second opening (O2) may be disposed between adjacent conductor structures and between third spacers 25.

[0156] Forming the second spacer 24 into a tapered shape allows for easy assurance of the upper opening area for the etching process. Furthermore, it also addresses opening defects at the bottom of the second spacer 24.

[0157] A plug isolation layer 26 may be formed on the third spacer 25. The plug isolation layer 26 may be separated by the second opening portion (O2). The plug isolation layer 26 may include silicon nitride.

[0158] With the formation of the second opening (O2), at least a portion of the second impurity region 14b is exposed, and a portion of the gap-filling spacer 23 is also exposed. The exposed portion of the second impurity region 14b can be connected to the conductive pattern 27.

[0159] The second opening (O2) can be formed using anisotropic etching and isotropic etching processes.

[0160] With the formation of the second opening (O2), a first spacer 22, a second spacer 24, and a third spacer 25 can be defined. In some embodiments, the first spacer 22, the second spacer 24, and the third spacer 25 may be included in the spacer structure.

[0161] refer to Figure 16 Conductive pattern 27 can be formed in the second opening portion (O2).

[0162] The conductive pattern 27 can contact the second impurity region 14b and can be arranged adjacent to the conductor structure.

[0163] The conductive patterns 27 and the plug isolation layer 26 may be arranged alternately in a direction parallel to the extension direction (D2) of the wire 20. Adjacent conductive patterns 27 may be isolated from each other by the plug isolation layer 26.

[0164] The conductive pattern 27 may include an upper plug 27a, an ohmic contact layer 27b, and a lower plug 27c.

[0165] The lower plug 27c may include a conductive material such as polysilicon.

[0166] The lower plug 27c can be formed by depositing polycrystalline silicon, followed by planarization and etching back processes.

[0167] The ohmic contact layer 27b may include, for example, a metal silicide. The ohmic contact layer 27b may be formed by annealing after depositing the metal silicide. Silicification may occur at the interface where the lower plug 27c contacts the ohmic contact layer 27b.

[0168] The upper plug 27a may include a conductive material such as a metallic material. The upper plug 27a may be formed by a gap-filling and planarization process using a metallic material. The upper plug 27a may include, for example, tungsten.

[0169] The spacer structure (SP) disposed between the conductor 20 and the conductive pattern 27 may have a KOK (low-K oxide-low-K) stacked structure or a KON (low-K oxide-nitride) stacked structure.

[0170] Because the spacer structure (SP) contains a low-k material, the parasitic capacitance of the conductor 20 is reduced. Furthermore, because the spacer structure (SP) is tapered, the gap (spacing) between the conductor 20 and the conductive pattern 27 is ensured, thereby reducing parasitic capacitance.

[0171] As described above, in some embodiments of the semiconductor device and manufacturing method thereof according to the present disclosure, a tapered spacer is formed between the conductive wire and the conductive pattern to facilitate the formation of the conductive pattern.

[0172] According to embodiments of this disclosure, the first spacer that directly contacts the sidewall of the conductor does not contain nitride, thereby preventing nitriding of the conductor.

[0173] Furthermore, according to embodiments of this disclosure, the first spacer comprises a low dielectric constant (low K) material, and a second spacer comprising a tapered silicon oxide layer is formed on the first spacer, thereby improving the parasitic capacitance between the wire and the conductive pattern.

[0174] The embodiments disclosed herein can provide a variety of beneficial effects that can be directly or indirectly recognized.

[0175] Those skilled in the art will understand that this disclosure may be implemented in other specific ways than those described herein. Furthermore, claims not expressly set forth in the appended claims may be combined to form embodiments, or incorporated as new claims through subsequent amendments after filing.

[0176] Although several exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be devised based on the description and / or illustration in this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device comprising: a wire contact plug and a conductive pattern spaced apart from each other in a first direction; a wire disposed over the wire contact plug and extending in a second direction perpendicular to the first direction; and a spacer structure contacting sidewalls of the wire and sidewalls of the wire contact plug, and an upper portion of the spacer structure having a width smaller than a width of a lower portion of the spacer structure. The spacer structure includes:

2. The semiconductor device of claim 1, wherein, a first spacer contacting the sidewalls of the wire and the sidewalls of the wire contact plug; a second spacer contacting the first spacer, and an upper portion of the second spacer having a width smaller than a width of a lower portion of the second spacer; and a third spacer disposed between the second spacer and the conductive pattern. The first spacer includes:

3. The semiconductor device of claim 2, wherein, a material having a dielectric constant lower than silicon nitride. The first spacer includes silicon carbide (SiC), silicon carbon oxide (SiCO), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), boron nitride (BN), or a combination thereof.

4. The semiconductor device of claim 2, wherein, The second spacer includes silicon oxide.

5. The semiconductor device of claim 2, wherein, The silicon oxide is doped with one of nitrogen or fluorine.

6. The semiconductor device of claim 5, wherein, The third spacer includes silicon carbide (SiC), silicon carbon oxide (SiCO), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), boron nitride (BN), or a combination thereof.

7. The semiconductor device of claim 2, wherein, A lower portion of the conductive pattern has a width smaller than a width of an upper portion of the conductive pattern.

8. The semiconductor device of claim 1, wherein, 9. The semiconductor device of claim 1, further comprising: a storage element disposed on the conductive pattern. The conductive pattern includes:

10. The semiconductor device of claim 1, wherein, a lower plug including polysilicon; an ohmic contact layer disposed on the lower plug and including a metal silicide; and an upper plug disposed on the ohmic contact layer and including a metallic material.

11. The semiconductor device of claim 1, further comprising: first and second impurity regions formed in a substrate, wherein the wire contact plug is connected to the first impurity region. The conductive pattern is connected to the second impurity region.

12. The semiconductor device of claim 11, wherein, The first impurity region is disposed between two adjacent buried word lines.

13. The semiconductor device of claim 11, wherein, 14. The semiconductor device of claim 1, wherein: the wire is a bit line; and the conductive pattern is a storage node contact plug.

15. A semiconductor device comprising: a plurality of wires spaced apart from each other on a substrate; a plurality of wire contact plugs respectively disposed under the wires; a plurality of conductive patterns disposed between the wires; and a plurality of spacer structures disposed between the conductive patterns and the wires, wherein each of the spacer structures includes: a first spacer contacting sidewalls of the wires and sidewalls of the wire contact plugs; a second spacer contacting the first spacer, and an upper portion of the second spacer having a width smaller than a width of a lower portion of the second spacer; and a third spacer disposed between the second spacer and the conductive pattern.

16. The semiconductor device of claim 15, further comprising: ​ ​ a plug isolation layer disposed between the conductive patterns, wherein the conductive patterns and the plug isolation layer are arranged alternately along a direction in which the wire extends.

17. The semiconductor device of claim 16, wherein, The plug isolation layer comprises an insulating material.

18. The semiconductor device of claim 15, wherein, The first spacer comprises: a material having a lower dielectric constant than silicon nitride.

19. The semiconductor device of claim 15, wherein, The first spacer comprises silicon carbide (SiC), silicon carbon oxide (SiCO), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), boron nitride (BN), or a combination thereof.

20. The semiconductor device of claim 15, wherein, The second spacer comprises silicon oxide.

21. The semiconductor device of claim 20, wherein, The silicon oxide is doped with one of nitrogen or fluorine.

22. The semiconductor device of claim 15, wherein, The third spacer comprises silicon carbide (SiC), silicon carbon oxide (SiCO), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), boron nitride (BN), or a combination thereof.

23. A semiconductor device, comprising: wire contact plugs and conductive patterns spaced apart from each other in a first direction; wires disposed on the wire contact plugs and extending in a second direction perpendicular to the first direction; and a first spacer contacting sidewalls of the wires and sidewalls of the wire contact plugs; a second spacer tapering and contacting the first spacer; a third spacer disposed between the second spacer and the conductive patterns, and first and second impurity regions formed in a substrate, wherein the wire contact plugs are connected to the first impurity regions. ​

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