Fuse structure and preparation method thereof, semiconductor device and integrated circuit

Abstract

The invention relates to the technical field of semiconductors, and discloses a fuse structure and a preparation method thereof, a semiconductor device and an integrated circuit. The fuse body is positioned on the substrate; wherein the fuse body is made of a polycrystalline silicon material; etching the stop layer; wherein the etching stop layer is covered right above the fuse body, and the thickness of the etching stop layer is 35 angstroms to 65 angstroms; an oxide layer covering the etch stop layer; wherein a cavity structure is formed in the oxide layer, and the cavity structure is located at the top of the fuse body. The polycrystalline silicon fuse has the beneficial effects that aiming at the problem that the physical expansion is limited when the fuse is burnt, a cavity structure is designed in the oxide layer to form a preset buffer region, so that the polycrystalline silicon fuse body is allowed to expand upwards when being fused, the pressing of a surrounding dielectric layer is avoided, the fuse body is ensured to be fused thoroughly, and the service life of the polycrystalline silicon fuse body is prolonged. Compared with a fuse structure in the prior art, the fuse structure has higher burning adjustment yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a fuse structure and its fabrication method, semiconductor devices, and integrated circuits. Background Technology

[0002] Fuse structures are important components in integrated circuits, widely used in circuit tuning, data protection, and other fields. Their core requirement is a 100% fusing rate, eliminating any possibility of "broken fuses with remaining fuse threads."

[0003] However, during the actual burn-in (power-on) process, it was found that because the top of the fuse is covered with multiple layers such as the front-end dielectric layer (ILD) and the rear-end multi-layer inter-metal dielectric layer (IMD), the volume expansion and heat release of the fuse after being powered on are suppressed, resulting in incomplete burn-in and thus directly affecting the yield of the device. Summary of the Invention

[0004] This application aims to at least partially solve one of the technical problems in related technologies. To this end, this application proposes a fuse structure and its fabrication method, a semiconductor device, and an integrated circuit. The main technical solutions adopted in this application include: In a first aspect, this application provides a fuse structure comprising: a substrate; a fuse body located on the substrate; wherein the fuse body is made of polycrystalline silicon; an etch stop layer; wherein the etch stop layer covers directly above the fuse body and the thickness of the etch stop layer is 35 angstroms to 65 angstroms; an oxide layer covering the etch stop layer; wherein a void structure is formed in the oxide layer and the void structure is located on top of the fuse body.

[0005] To address the issue of limited physical expansion during fuse firing, a pre-set buffer region is formed by designing a void structure in the oxide layer. This allows the polycrystalline silicon fuse to expand upwards when it melts, avoiding the mechanical compression of the surrounding dense dielectric layer and ensuring that the fuse can be completely melted. Compared with fuse structures in related technologies, this method has a higher firing yield.

[0006] Secondly, this application provides a method for preparing a fuse structure, which includes: providing a fuse substrate; wherein the fuse substrate is formed sequentially from bottom to top with a substrate, a shallow trench isolation structure, a fuse body, an etch stop layer with a target thickness, and an oxide layer; and the etch stop layer covers the fuse body; the oxide layer forms a via structure on top of the etch stop layer; the fuse substrate is subjected to multi-stage deposition, and the deposition process parameters are controlled during the multi-stage deposition process to form the fuse structure; wherein the oxide layer in the fuse structure forms a void structure on top of the fuse body.

[0007] By providing a fuse substrate with a specific through-hole structure and an ultra-thin etch stop layer, and then performing a multi-stage deposition process, a void structure can be precisely formed in the oxide layer directly above the fuse body. During fuse burn-in, the volume expansion can be effectively accommodated and the heat can be concentrated, thereby solving the problem of incomplete melting caused by dielectric layer pressing and significantly improving the burn-in yield and reliability of the fuse.

[0008] Optionally, the fuse substrate includes: providing a semiconductor substrate; depositing on the semiconductor substrate to form a shallow trench isolation structure, a fuse, an etch stop layer, and an oxide layer; wherein the oxide layer completely covers the etch stop layer; dry etching the oxide layer to remove the oxide layer on top of the fuse to form a via structure on top of the fuse; dry etching the etch stop layer to remove a portion of the etch stop layer on top of the fuse so that the etch stop layer on top of the fuse reaches a target thickness; wherein the target thickness is between 35 angstroms and 65 angstroms.

[0009] This precise patterning and etching process preserves a portion of the etching stop layer to protect the filament and lays the structural foundation for subsequent void formation.

[0010] Optionally, the fuse substrate is subjected to multi-stage deposition, including: determining a preset deposition environment; performing multi-stage deposition on the fuse substrate using a chemical vapor deposition process in the preset deposition environment; wherein the chemical vapor deposition process includes top radio frequency, side radio frequency and bias radio frequency.

[0011] By defining a pre-defined deposition environment containing a specific gaseous environment and employing a chemical vapor deposition process with three RF power systems—top RF, side RF, and bias RF—independent and precise control over plasma density, distribution uniformity, and ion bombardment energy was achieved, ensuring that void structures could be reliably fabricated on top of the filament.

[0012] Optionally, the preset deposition environment is a gaseous environment containing argon, oxygen and silane.

[0013] Choosing these gas combinations can effectively control the deposition rate and film quality, and lay the foundation for adjusting the balance between deposition and etching in subsequent steps to form a void structure.

[0014] Optionally, the deposition process parameters include radio frequency power parameters and gas flow rate parameters.

[0015] By precisely controlling the radio frequency power parameters, the bombardment energy and angle of ions on the film surface during growth can be controlled to guide the formation of void structures. Furthermore, by adjusting the gas flow rate parameters, the diffusion and consumption of reactants within the characteristic structure can be altered, thereby controlling the deposition rate differences at different locations within the structure and synergistically promoting the formation of void structures.

[0016] Optionally, multi-stage deposition is performed as follows: a first-stage deposition process is performed on a fuse substrate using a first power combination and a first flow rate combination to form a first substrate; wherein, the first power combination refers to the RF power parameters of the top RF, side RF, and bias RF in the first stage; the first flow rate combination refers to the set of gas flow rate parameters of each gas composition in a preset deposition environment; a second-stage deposition process is performed on the first substrate using a second power combination and a second flow rate combination to form a second substrate; wherein, the second power combination refers to the RF power parameters of the top RF, side RF, and bias RF in the second stage; the second flow rate combination refers to the set of gas flow rate parameters of each gas composition in the current deposition environment after the first-stage deposition process; a third-stage deposition process is performed on the second substrate using a third power combination and a third flow rate combination to form a fuse structure; wherein, the third power combination refers to the RF power parameters of the top RF, side RF, and bias RF in the third stage; the third flow rate combination refers to the set of gas flow rate parameters of each gas composition in the current deposition environment after the second-stage deposition process.

[0017] By dynamically adjusting the bias RF power and reactive gas flow rate at different stages, the balance between deposition and etching is precisely controlled, thereby enabling the active guidance of void formation at a specific location directly above the fuse and ensuring the controllability of its size and structure.

[0018] Optionally, the etching stop layer is made of silicon nitride; the oxide layer is made of silicon oxide.

[0019] Silicon nitride exhibits excellent etching selectivity and density, effectively protecting the underlying filament during subsequent etching processes. Silicon oxide, on the other hand, boasts a mature deposition process, stable insulation properties, and good compatibility with subsequent metal layers, reducing the risk of interlayer peeling.

[0020] Thirdly, this application also provides a semiconductor device comprising the above-described fuse structure.

[0021] Fourthly, this application also provides an integrated circuit comprising the aforementioned semiconductor device. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1a This is an overall schematic diagram of a fuse structure provided according to an embodiment of the related art; Figure 1b This is a longitudinal cross-sectional schematic diagram of a fuse structure provided according to an embodiment of this application; Figure 2a This is a flowchart of a method for preparing a fuse structure according to an embodiment of this application; Figure 2b This is a schematic diagram of a structure formed by a deposition process according to an embodiment of this application; Figure 2c This is a schematic diagram of a structure formed by a photolithography process according to an embodiment of this application; Figure 2d This is a schematic diagram of a structure formed by an etching process according to an embodiment of this application; Figure 3 This is a flowchart of a multi-stage deposition method provided according to an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Unless otherwise specified, the experimental methods used in the following examples are conventional methods. Unless otherwise specified, the materials, reagents, methods, and instruments used are all conventional materials, reagents, methods, and instruments in the art, and can be obtained commercially by those skilled in the art.

[0026] Taking the fuse structure made of polycrystalline silicon as an example, please refer to... Figure 1aThe polysilicon fuse structure in the related technology includes a shallow trench isolation (STI) 101, an active area (AA) 103, a polysilicon fuse structure (Poly Fuse) 105, a multilayer structure on top of the fuse, a metal layer (Metal) 107, and a contact hole (CT) 109.

[0027] The shallow trench isolation 101 is an isolation structure located at the bottom layer of the chip, used to separate different active areas and prevent interference between circuits. The polysilicon fuse structure 105 is directly disposed above the shallow trench isolation 101. The active area 103 is the key area in the chip that implements the core circuit functions. The metal layer 107 is mainly made of copper (Cu), with tantalum (Ta) or tantalum nitride (TaN) wrapped around its edges, serving as a conductive line in the circuit to transmit current. The contact hole 109 is used to connect the conductive structures of different layers, ensuring smooth current conduction between layers.

[0028] It should be noted that the multi-layer structure at the top of the fuse is used to cover and protect the polysilicon fuse structure 105, while providing a supporting and insulating environment for the metal layer 107, preventing direct contact between the metal layer and the polysilicon fuse that could lead to a short circuit. However, it also inhibits the burning-out of the polysilicon fuse structure. Specifically, the multi-layer structure at the top of the fuse includes an inter-layer dielectric (ILD) 111 and multiple inter-metal dielectric (IMD) layers. The inter-layer dielectric 111 covers the surface of the polysilicon fuse and is essentially an oxide layer, serving to insulate and protect the polysilicon fuse.

[0029] Multiple inter-metal dielectric layers are used to isolate metal layers 107 of different levels, preventing short circuits between adjacent metal layers due to current leakage, while maintaining the stability of the internal structure of the chip and providing insulation support for the orderly arrangement of metal lines. Specifically, the multiple inter-metal dielectric layers may include a first inter-metal dielectric layer (IMD1) 113, a second inter-metal dielectric layer (IMD2) 115, and a third inter-metal dielectric layer (IMD3) 117, and silicon nitride (IMD) is also disposed between each layer. The first intermetallic dielectric layer 113 and the second intermetallic dielectric layer 115 can be made of low-k materials, and the third intermetallic dielectric layer 117 is made of silicon oxide. These three layers are stacked sequentially above the front dielectric layer 111 to isolate the different metal structures and prevent short circuits. The silicon nitride 119 and silicon carbide 121 isolation layers mainly serve to stop etching and provide insulation protection, preventing subsequent processes from damaging the underlying structure.

[0030] In summary, in order to resolve the contradiction between the protection of the film structure and the melting of the fuse structure, this application aims to make targeted adjustments to the film structure on the top of the polycrystalline silicon fuse. By reserving specific space, a release path is provided for the volume expansion of the polycrystalline silicon fuse during the firing process, thereby ensuring that it can be completely melted and ultimately improving the firing yield.

[0031] This application provides a fuse structure; please refer to... Figure 1b ,like Figure 1b As shown, the fuse structure includes a substrate 102, a fuse body 104, an etch stop layer 106, and an oxide layer 108.

[0032] It is understandable that a fuse structure can refer to a fusible functional structure in an integrated circuit used to realize circuit protection, parameter adjustment, or data storage. Its core principle is to change the working state or parameters of the internal circuit of the integrated circuit chip by switching between "conduction-fuse".

[0033] The substrate 102 can refer to the basic support structure of a semiconductor device. Its material can be silicon (Si), germanium (Ge), or silicon-on-insulator (SOI), etc., to provide stable physical support and electrical basis for the subsequent growth and deposition of various functional layers.

[0034] Understandably, active regions can be defined on the surface of substrate 102 using processes such as ion implantation, so that core functional regions such as source / drain of transistors can be subsequently constructed. At the same time, shallow trench isolation structures can be formed between different active regions. These shallow trench isolation structures are made by etching shallow trenches in the substrate and filling them with insulating materials (such as silicon oxide), and are used to separate different active regions on the substrate to avoid current crosstalk or signal interference between adjacent circuit units.

[0035] Based on the substrate 102, a fuse 104 capable of fusing can be further provided. This fuse can refer to a fusible conductive structure in the device used to realize circuit protection, data storage, or parameter adjustment functions. For example, since polysilicon has good semiconductor properties and fusing properties, the fuse 104 can be made of polysilicon so that the entire device can generate high-temperature fusing when encountering a large current, thereby realizing the switching of circuit states.

[0036] Specifically, the fuse 104 can be directly fabricated above the shallow trench isolation structure on the substrate 102, thereby achieving electrical isolation from the circuit elements in the active region and ensuring that the fuse operation will not damage the core circuit. Furthermore, both ends of the fuse can be connected to the metal interconnect structure of the chip, ensuring that the fuse can be connected to the target circuit and achieve normal function.

[0037] A contact etch stop layer (CESL) 106 is provided on the upper layer of the fuse 104, covering the entire top surface area of ​​the fuse. This etch stop layer can refer to the termination layer of the etching process in semiconductor manufacturing, and is typically made of a dielectric material with high hardness, high insulation, and good chemical stability, serving as an insulating protective layer. For example, the etch stop layer 106 can be made of silicon nitride (…). An isolation layer consisting of .

[0038] It should be noted that, since the etch stop layer covers directly above the fuse, its thickness is crucial. If the etch stop layer is too thick, it will significantly increase the film pressure on top of the fuse, excessively suppressing heat conduction and volume expansion of the fuse; if the etch stop layer is too thin, it cannot guarantee sufficient structural strength and insulation properties, and cannot effectively prevent damage to the fuse below from subsequent oxide layer deposition and etching processes. Therefore, for example, its thickness can be limited to the range of 35 angstroms to 65 angstroms, preferably 50 angstroms, to minimize the obstruction to fuse firing while ensuring process feasibility.

[0039] Furthermore, an oxide layer 108 is formed above the etch stop layer 106. This oxide layer 108 is the front dielectric layer (ILD) in the multilayer structure at the top of the fuse, and can be made of silicon oxide (…). Made of materials thereof or their derivatives, it is capable of insulating the fuse 102 from the metal layer above, preventing short circuits between different functional layers.

[0040] Specifically, a void structure 110 is formed in the oxide layer 108. This void structure 110 is located at the top of the filament and can be a closed cavity structure enclosed by the oxide layer material. Specifically, during the oxide layer deposition process, this void structure can be formed in the region directly above the filament by adjusting the deposition process parameters, and the size of the void structure can also be adjusted by controlling the deposition process parameters to match the size of the filament's melting area.

[0041] Understandably, the core function of this void structure is to provide space for the inevitable volume expansion and heat accumulation of the polycrystalline silicon fuse during the firing process. Specifically, when a large current is applied to the device, the polycrystalline silicon fuse will melt and expand due to the high temperature. At this time, the void structure can effectively accommodate its expansion, thereby avoiding the phenomenon of incomplete melting of the fuse due to the mechanical pressure of the top oxide layer. At the same time, since the gas inside the void structure (such as air or inert gas remaining in the process) has a low thermal conductivity, the void structure can also reduce the loss of heat from the fuse to the surrounding oxide layer, causing the heat to be more concentrated in the melting area, further ensuring that the fuse achieves 100% melting, and ultimately improving the overall firing yield.

[0042] It should be noted that, compared to the polycrystalline silicon fuse structure in related technologies, the structure proposed in this application only has the aforementioned void structure designed in the front dielectric layer (i.e., the oxide layer referred to in this embodiment) of its top multilayer dielectric. The materials, functions, and arrangement of the remaining components, including various intermetallic dielectric layers, metal layers, and contact holes, can be referred to... Figure 1a The relevant technical structures and their corresponding descriptions shown are not repeated here. In other words, the fuse structure involved in this application remains compatible with relevant technologies in terms of its underlying shallow trench isolation structure and the intermetallic dielectric layer, thereby ensuring its inheritance in manufacturing process and the reliability of the overall structure.

[0043] In the above embodiments, to address the problem of limited physical expansion during fuse firing, a void structure is designed in the oxide layer to form a pre-set buffer area, thereby allowing the polycrystalline silicon fuse to expand upward when it melts, avoiding the suppression of the surrounding dielectric layer, and ensuring that the fuse can be completely melted. Compared with the fuse structure in related technologies, it has a higher firing yield.

[0044] This application also provides a method for preparing a fuse structure, used to prepare the above-mentioned fuse structure, such as... Figure 2a As shown, the method includes the following steps: S210 provides a fuse board.

[0045] Here, the fuse substrate can refer to a pre-fabricated intermediate carrier device that can provide a pre-formed basis for subsequent processes. Specifically, the fuse substrate is formed from bottom to top as follows: a substrate, a shallow trench isolation structure, a fuse body, an etch stop layer with a target thickness, and an oxide layer.

[0046] In this context, the substrate can refer to the basic support structure of the semiconductor device. The shallow trench isolation structure is an isolation structure made by etching shallow trenches in the substrate and filling them with insulating material. The fuse can be made of polycrystalline silicon so that the entire device can generate high-temperature melting when encountering high current, thereby achieving circuit state switching. For specific limitations on the substrate, shallow trench isolation structure, and fuse, please refer to the limitations on a fuse structure above, which will not be repeated here.

[0047] Furthermore, an etch stop layer of a target thickness is provided on the upper layer of the fuse body. This target thickness can be a thickness parameter set to balance the protection function and the fuse firing performance.

[0048] An oxide layer is formed on top of the etch stop layer. This oxide layer is the front dielectric layer (ILD) in the filament structure, which covers the surface of the etch stop layer. A vertical stacked structure of the etch stop layer and the oxide layer is formed from bottom to top.

[0049] However, it should be noted that the oxide layer forms a through-hole structure on top of the etch stop layer. This through-hole structure is located in the area directly above the fuse, and this through-hole structure can be understood as a window that is approximately a through hole. It does not completely open the device, but only penetrates the oxide layer and exposes the surface of the etch stop layer below.

[0050] Optionally, its width can be matched to the filament. This through-hole structure can be formed by photolithography and dry etching processes, and its function is to provide space for the formation of void structures in subsequent multi-stage deposition processes, avoiding the formation of invalid voids in other erroneous areas that would affect structural performance.

[0051] Specifically, the fuse substrate can be obtained through the following process steps: First, a semiconductor substrate is provided; second, a shallow trench isolation structure, a fuse, an etch stop layer, and an oxide layer are deposited on the semiconductor substrate; then, the oxide layer is dry-etched to remove the oxide layer on top of the fuse to form a via structure on top of the fuse; finally, the etch stop layer is dry-etched to remove part of the etch stop layer on top of the fuse so that the etch stop layer on top of the fuse reaches the target thickness.

[0052] Here, a semiconductor substrate can refer to the basic support structure of a semiconductor device, i.e., the substrate. For example, the semiconductor substrate can be obtained through semiconductor wafer fabrication processes.

[0053] Next, deposition is performed on the semiconductor substrate to form a shallow trench isolation structure, a fuse, an etch stop layer, and an oxide layer.

[0054] Specifically, a shallow trench isolation structure is first formed on a substrate using photolithography and chemical vapor deposition (CVD). A thick polysilicon layer is then deposited on the surface of the shallow trench isolation structure, followed by ion implantation and photolithography to form a polysilicon filament. Next, a silicon nitride etch stop layer and a silicon oxide layer are deposited using strong chemical vapor deposition. The oxide layer completely covers the etch stop layer, ensuring it is fully encapsulated and preventing oxidation exposure during subsequent processes. The final stacked structure can be referenced. Figure 2b As shown in the figure, from bottom to top, the central area clearly shows the stacked structure of the substrate, shallow trench isolation, fuse, etch stop layer and oxide layer.

[0055] Optionally, the material of the etch stop layer may be silicon nitride ( Materials used for the oxide layer include silicon oxynitride (SiON) and silicon carbide (SiC). Silicon nitride is preferred due to its excellent etching selectivity and density, effectively protecting the underlying filament during subsequent etching processes. The oxide layer can be made of silicon oxide, phosphosilicate glass, or boron-doped phosphosilicate glass. Silicon oxide is preferred because of its mature deposition process, stable insulation properties, and good compatibility with subsequent metal layers.

[0056] Furthermore, in related technologies, after depositing an oxide layer that fully covers the etch stop layer, subsequent processes such as metal layer deposition are performed directly. However, in this embodiment, in order to form a through-hole structure in the oxide layer to accommodate voids, two additional processes are required to ensure that voids can be accurately generated in subsequent multi-stage deposition.

[0057] Specifically, the oxide layer can be dry-etched to remove the oxide layer on top of the fuse, thereby forming a through-hole structure on top of the fuse.

[0058] For example, before dry etching, the oxide layer can be chemically mechanically polished (CMP) to planarize the surface and ensure the accuracy of subsequent photolithography. Then, a photolithography process is performed, coating the oxide layer surface with photoresist (PR). Through exposure and development processes, only the PR in the top region of the fuse is removed, while the PR in other regions is retained, forming a patterned mask. Figure 2c As shown in the diagram, the blue area represents the region where the resistive oxide layer (PR) is retained, and the white area in the middle represents the region at the top of the fuse where the PR has been removed. Finally, dry etching is performed to remove the oxide layer at the top of the fuse that is not protected by the PR, until the underlying etching stop layer is exposed, forming a through-hole structure.

[0059] The etch stop layer can then be dry-etched to remove part of the etch stop layer at the top of the fuse, so that the etch stop layer at the top of the fuse reaches the target thickness.

[0060] Understandably, considering the balance between the protective function of the etch stop layer and the performance of the fuse, the target thickness of the etch stop layer can be between 35 angstroms and 65 angstroms, preferably 50 angstroms, to ensure that the etch stop layer can prevent damage to the fuse from subsequent oxide layer processing while minimizing its obstruction to the heat conduction and volume expansion of the fuse.

[0061] Specifically, after the oxide layer etching is completed, a dry etching process with high selectivity for silicon nitride can be used to quantitatively etch the exposed etch stop layer, ensuring that the remaining etch stop layer thickness reaches the target thickness. The structure formed after etching can be as follows: Figure 2dAs shown: The blank area in the center of the figure is the etched near-through-hole structure. The orange thin layer at the bottom of the through-hole is the etching stop layer of the target thickness. Below the etching stop layer is the polysilicon filament.

[0062] Finally, after the above series of steps, a compliant fuse substrate can be obtained. This precise patterning and etching process retains a portion of the etching stop layer to protect the fuse body, and lays the structural foundation for subsequent void formation.

[0063] S220. Perform multi-stage deposition on the fuse substrate and adjust the deposition process parameters during the multi-stage deposition process to form a fuse structure.

[0064] In this structure, the oxide layer in the fuse body forms a void structure at the top of the fuse body. This void structure can be a closed cavity structure enclosed by the oxide layer material.

[0065] Multi-stage deposition refers to a preparation strategy that divides the deposition process into multiple stages with different process conditions, performed sequentially. Specifically, this deposition can be achieved through methods such as Chemical Vapor Deposition (CVD). Taking CVD as an example, this multi-stage deposition can be achieved by sequentially executing three process steps with different deposition parameters to dynamically control the balance between deposition and etching, ultimately forming a void structure (such as...) in the oxide layer and on top of the filament. Figure 1b (As shown).

[0066] Among them, deposition process parameters can refer to the set of adjustable variables that affect the growth characteristics, microstructure and final morphology of thin films during the deposition process.

[0067] It should be noted that since the deposition process is a complex process involving chemical reactions, mass transport and plasma dynamics, there are many types of adjustable deposition process parameters, such as temperature, pressure, radio frequency power, gas type and flow rate.

[0068] For example, the deposition process parameters that are mainly controlled in the embodiments of this application may include radio frequency power parameters and gas flow rate parameters. The radio frequency power parameter refers to the radio frequency power value applied in the reaction chamber, which is used to excite the reactive gases to form plasma. Its value can affect the plasma density, ion energy, and the degree of anisotropy in the deposition. The gas flow rate parameter refers to the volumetric flow rate of various reactive gases introduced into the reaction chamber. Its value can affect the concentration ratio of reactants, and thus affect the deposition rate and the stoichiometry of the thin film.

[0069] Specifically, by precisely controlling the radio frequency power parameters, the bombardment energy and angle of ions on the surface of the growing film can be controlled, which is key to guiding the formation of void structures. Furthermore, by adjusting the gas flow rate parameters, the diffusion and consumption of reactants within the characteristic structure can be altered, thereby controlling the difference in deposition rate at different locations within the structure and synergistically promoting the formation of void structures.

[0070] In the above embodiments, by providing a fuse substrate with a specific through-hole structure and an ultra-thin etch stop layer, and then performing a multi-stage deposition process, a void structure can be precisely formed in the oxide layer directly above the fuse body. During fuse burn-in, the volume expansion can be effectively accommodated and the heat can be concentrated, thereby solving the problem of incomplete melting caused by dielectric layer pressing and significantly improving the burn-in yield and reliability of the fuse.

[0071] In some implementation methods, please refer to the appendix. Figure 3 Multi-stage deposition is performed on the fused substrate, including: S310. Determine the preset sedimentation environment.

[0072] The preset deposition environment refers to a deposition environment with a set of comprehensive process conditions pre-set during the deposition process. Since the effectiveness of the deposition process is highly dependent on the synergistic effect of these environmental parameters, there are various configuration options for the preset deposition environment to adapt to different structure growth requirements. Specifically, the preset deposition environment can be determined by flexibly setting key parameters such as the temperature, pressure, type and proportion of introduced gas, and radio frequency power of the reaction chamber based on the characteristics and structural requirements of the target structure.

[0073] For example, the preset deposition environment can be a gaseous environment containing argon, oxygen, and silane. Argon primarily serves as a diluent and plasma stabilizer. Oxygen and silane are the main reactant gases, reacting to form silicon dioxide after being excited and decomposed in the plasma, and then deposited. Additionally, a portion of silane can be introduced from the top of the reaction chamber; to distinguish it from the silane used for the reaction, this is referred to as top silane. Introducing top silane during the reaction improves the uniformity of reactant distribution on the substrate surface. Choosing this gas combination effectively controls the deposition rate and film quality, and lays the foundation for adjusting the balance between deposition and etching in subsequent steps to form a void structure.

[0074] Understandably, in addition to the specific gas environment required here, the deposition process usually needs to be carried out under a certain degree of vacuum and a constant reaction temperature to ensure that the deposition process proceeds normally.

[0075] S320. A multi-stage deposition process is performed on the fuse substrate using chemical vapor deposition in a preset deposition environment.

[0076] Chemical vapor deposition (CVD) can be a deposition technique that utilizes gaseous precursors to undergo a chemical reaction on a heated substrate surface to generate a solid thin film.

[0077] Understandably, the key to the formation of voids directly above the filament in chemical vapor deposition (CVD) lies in its reaction characteristics. Specifically, at the start of CVD, reactive gases uniformly cover the substrate surface (including the bottom and sidewalls of the via structure). Deposition occurs simultaneously on all surfaces; the oxide layer on the sidewalls grows inwards, while the oxide layer at the bottom grows upwards. However, because fresh reactive gases are more readily available at the top opening of the via structure, while gases at the bottom must diffuse through the gaps in the sidewalls to reach it, the deposition rate at the top of the via structure is typically slightly faster than at the bottom. As deposition progresses, the oxide layer on the sidewalls of the via structure thickens. Due to the via structure's wide top opening and narrow bottom, the oxide layers on the sidewalls first meet and bridge near the top of the via structure, forming a closed cavity slightly below the via. Once this bridging is formed, it significantly hinders the diffusion of reactive gases into the cavity, causing the internal deposition reaction to slow down or even stop, ultimately forming an enclosed void structure. Furthermore, since this bridging behavior occurs preferentially at the top of the structure, the resulting void is naturally located at the center of the through-hole structure, that is, directly above the fuse.

[0078] Furthermore, chemical vapor deposition processes can precisely control plasma energy and distribution by configuring multiple radio frequency electrode systems to adapt to multi-stage deposition requirements. For example, a three-RF power system can be used, namely top RF (RFTop), side RF (RF Side), and bias RF (RF Bias).

[0079] Top radio frequency (RF) refers to the RF power applied from the top of the deposition chamber, used to generate and maintain high-density plasma at the top of the reaction chamber. Side RF refers to the RF power applied from the sidewalls of the deposition chamber, which improves plasma distribution uniformity and avoids plasma density differences between the chamber edge and center. Bias RF refers to the RF power applied to the reaction stage supporting the substrate, used to control the energy and direction of ions bombarding the substrate surface, thereby controlling the deposition morphology and anisotropy.

[0080] Specifically, multi-stage deposition can be performed as follows: first, a first-stage deposition process is performed on the fuse substrate using a first power combination and a first flow rate combination to form a first substrate; second, a second-stage deposition process is performed on the first substrate using a second power combination and a second flow rate combination to form a second substrate; finally, a third-stage deposition process is performed on the second substrate using a third power combination and a third flow rate combination to form a fuse structure.

[0081] The first stage can refer to the initial deposition layer formation stage, which aims to form a well-covered initial silicon oxide film. The first power combination can refer to the set of bias RF parameters adapted to the initial coverage requirements, i.e., the RF power parameters of the top RF, side RF, and bias RF in the first stage. The first flow combination can refer to the set of gas flow parameters adapted to the initial coverage requirements, i.e., the set of gas flow parameters for each gas composition in the preset deposition environment. The first substrate can refer to the intermediate carrier after the first stage deposition, where a thin layer of silicon oxide is uniformly covered on the surface and the inner walls of the vias.

[0082] Specifically, the bias RF power in the first power combination can be set to a medium level to ensure film compactness while avoiding premature bridging. The first flow combination uses a relatively low reactive gas flow rate to control the initial deposition rate.

[0083] For example, in the first stage, the first power combination may be: a top radio frequency power parameter of 800 W to 1000 W, a side radio frequency power parameter of 3800 W to 4200 W, and a bias radio frequency power parameter of 1900 W to 2100 W. The first flow rate combination may be: an argon gas flow rate of 90 sccm to 110 sccm, an oxygen gas flow rate of 170 sccm to 200 sccm, a silane gas flow rate of 30 sccm to 60 sccm, and a top silane gas flow rate of 10 sccm to 30 sccm, to form a well-covered initial oxide layer on the fuse substrate to obtain the first substrate.

[0084] Next, a second stage of deposition process is performed on the first substrate using a second power combination and a second flow rate combination to form a second substrate.

[0085] The second stage can refer to the critical stage of void formation. The second power combination can refer to the set of power parameters for the top RF, side RF, and bias RF used in this stage. The second flow combination can refer to the set of gas flow parameters for each gas composition set to adjust the reaction after the first stage deposition. The second substrate can refer to the intermediate carrier after the second stage deposition, where the top of the vias has been bridged and closed, and a closed cavity has been formed inside.

[0086] It should be noted that since the core function of the top radio frequency (RF) is to maintain plasma excitation efficiency, and the core function of the side RF is to ensure plasma homogeneity, the power parameters of the top and side RFs can remain consistent with those in the first stage. Only the ion bombardment intensity can be adjusted by changing the bias RF. That is, in the second power combination, the bias RF power can be significantly increased to enhance the etching effect of ion bombardment. In the second flow rate combination, the silane flow rate can be moderately increased to ensure the bottom deposition rate and guarantee stable cavity formation.

[0087] For example, in the second stage, the second power combination can be: the power parameters of the top RF and side RF are consistent with the first power combination, while the power parameter of the bias RF is increased to 5000W to 5500W. The second flow combination can be: argon 100sccm to 120 sccm, oxygen 165sccm to 195 sccm, silane 70sccm to 100 sccm, and top silane 5sccm to 30 sccm. The extremely high bias RF power induces intense anisotropic etching to create differences at different locations, prompting preferential bridging of the sidewall deposited layers in the top central region, thereby initially forming a void structure to obtain the second substrate.

[0088] Finally, the second substrate is subjected to a third stage of deposition using a third power combination and a third flow combination to form a fused wire structure.

[0089] The third stage can refer to the high deposition rate filling and void sealing stage. The third power combination can refer to the set of power parameters for the top radio frequency, side radio frequency, and bias radio frequency used in this stage. The third flow rate combination can refer to the set of gas flow rates set after the second stage of deposition to quickly complete the filling.

[0090] Specifically, to maintain high plasma density, the power parameters of the top and side radio frequencies in the third power combination can remain consistent with those in the first stage. Furthermore, since a preliminary void structure has already formed in the second stage, the bias radio frequency needs to be lower than in the second stage to avoid over-etching. In the third flow rate combination, the reactive gas flow rate can be increased to achieve high-speed deposition.

[0091] For example, in the third stage, the third power combination can be: the power parameters of the top and side radio frequencies remain consistent with the first power combination, while the power parameter of the bias radio frequency is reduced to 4800W to 5200W. The third flow combination can be: argon 100sccm to 120 sccm, oxygen 360sccm to 400 sccm, silane 150sccm to 200 sccm, and top silane 20sccm to 40 sccm. This completes the rapid filling of the remaining space and completely encapsulates the void structure within the oxide layer, ultimately forming a structure like... Figure 1b The fuse structure shown.

[0092] By dynamically adjusting the bias RF power and reactive gas flow rate at different stages, the balance between deposition and etching is precisely controlled, thereby actively guiding the formation of voids at specific locations directly above the filament and ensuring the controllability of their size and structure.

[0093] In the above embodiments, by determining a preset deposition environment containing a specific gas environment and using a chemical vapor deposition process with three radio frequency power supply systems configured as top radio frequency, side radio frequency and bias radio frequency, independent and precise control of plasma density, distribution uniformity and ion bombardment energy is achieved, ensuring that the void structure can be reliably fabricated on the top of the filament.

[0094] It should be understood that although the steps in the flowchart above are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart above may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0095] This application also provides a semiconductor device comprising the above-described fuse structure.

[0096] For specific limitations on a semiconductor device, please refer to the limitations on a fuse structure mentioned above, which will not be repeated here.

[0097] This application also provides an integrated circuit that includes the semiconductor device described above.

[0098] For specific limitations regarding an integrated circuit, please refer to the limitations regarding a semiconductor device mentioned above, which will not be repeated here.

[0099] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0100] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0101] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0102] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Since they are fundamentally similar to the method embodiments, the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0103] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0104] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A fuse structure, characterized by, The fuse structure comprises: a substrate; a fuse body on the substrate; wherein the fuse body is made of polysilicon material; an etching stop layer; wherein the etching stop layer covers the fuse body directly above, and the thickness of the etching stop layer is 35 angstroms to 65 angstroms; an oxidation layer covering the etching stop layer; wherein the oxidation layer is formed with a hollow structure, and the hollow structure is located at the top of the fuse body.

2. A method of producing a fuse structure, characterized by, The method for preparing the fuse structure of claim 1 comprises: providing a fuse substrate; wherein the fuse substrate is sequentially formed with a substrate, a shallow trench isolation structure, a fuse body, an etching stop layer with a target thickness, and an oxidation layer from bottom to top; and the etching stop layer covers the fuse body; and the oxidation layer is formed with a via structure at the top of the etching stop layer; carrying out multi-stage deposition on the fuse substrate, and adjusting deposition process parameters during the multi-stage deposition to form the fuse structure; wherein the oxidation layer in the fuse structure is formed with a hollow structure at the top of the fuse body.

3. The production method according to claim 2, characterized by, The providing of the fuse substrate comprises: providing a semiconductor substrate; carrying out deposition on the semiconductor substrate to form the shallow trench isolation structure, the fuse body, the etching stop layer, and the oxidation layer; wherein the oxidation layer fully covers the etching stop layer; carrying out dry etching on the oxidation layer to remove the oxidation layer at the top of the fuse body to form a via structure at the top of the fuse body; carrying out dry etching on the etching stop layer to remove part of the etching stop layer at the top of the fuse body so that the etching stop layer at the top of the fuse body reaches the target thickness; wherein the target thickness is between 35 angstroms and 65 angstroms.

4. The preparation method according to claim 2, characterized in that, The multi-stage deposition on the fuse substrate comprises: determining a preset deposition environment; carrying out multi-stage deposition on the fuse substrate by using a chemical vapor deposition process in the preset deposition environment; wherein the chemical vapor deposition process comprises a top radio frequency, a lateral radio frequency, and a bias radio frequency.

5. The preparation method according to claim 4, characterized in that, The preset deposition environment is a gas environment with argon, oxygen, and silane.

6. The preparation method according to claim 4, characterized in that, The deposition process parameters comprise radio frequency power parameters and gas flow parameters.

7. The production method according to claim 6, wherein The multi-stage deposition is carried out by: carrying out first-stage deposition processing on the fuse substrate by using a first power combination and a first flow combination to form a first substrate; wherein the first power combination refers to radio frequency power parameters of the top radio frequency, the lateral radio frequency, and the bias radio frequency in the first stage; and the first flow combination refers to a set of gas flow parameters of each gas composition in the preset deposition environment; carrying out second-stage deposition processing on the first substrate by using a second power combination and a second flow combination to form a second substrate; wherein the second power combination refers to radio frequency power parameters of the top radio frequency, the lateral radio frequency, and the bias radio frequency in the second stage; and the second flow combination refers to a set of gas flow parameters of each gas composition in the current deposition environment after the first-stage deposition processing. A third stage of deposition treatment is performed on the second substrate by using a third power combination and a third flow combination, to form the fuse structure; wherein the third power combination refers to the third stage of radio frequency power parameters of the top radio frequency, the lateral radio frequency and the bias radio frequency; the third flow combination refers to a set of gas flow parameters of each gas in the current deposition environment after the second stage of deposition treatment.

8. The preparation method according to claim 2, characterized in that, The material of the etching stop layer is silicon nitride; and the material of the oxidation layer is silicon oxide.

9. A semiconductor device, characterized by comprising: The fuse structure as claimed in claim 1.

10. An integrated circuit, characterized by The semiconductor device as claimed in claim 9.

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