Manufacturing method of polycrystalline silicon fuse structure and semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and discloses a manufacturing method of a polycrystalline silicon fuse structure and a semiconductor device, and the method comprises the steps: depositing a dielectric protection layer; forming a photoresist layer on the dielectric protection layer, and reserving the photoresist layer in the fuse region of the polycrystalline silicon fuse structure so as to expose the dielectric protection layers in the fuse regions of other non-polycrystalline silicon fuse structures; etching to remove the dielectric protection layers of the fuse regions of other non-polycrystalline silicon fuse structures, and removing the photoresist layer of the fuse region of the polycrystalline silicon fuse structure to obtain a pretreated polycrystalline silicon fuse structure; and depositing a stress covering layer to obtain the polycrystalline silicon fuse wire structure with the differentiated film layer, the fuse wire region of the polycrystalline silicon fuse wire structure with the differentiated film layer is covered with the dielectric protection layer and the stress covering layer, and the fuse wire regions of other non-polycrystalline silicon fuse wire structures are covered with the stress covering layers. According to the technical scheme provided by the invention, the burning adjustment yield of the polycrystalline silicon fuse structure can be improved under the condition that good electrical and thermal characteristics of the polycrystalline silicon fuse structure are ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for manufacturing a polycrystalline silicon filament structure and a semiconductor device. Background Technology

[0002] Polysilicon fuses (PSFs) are crucial protective materials in integrated circuits, primarily used to quickly disconnect circuits and prevent damage in the event of abnormal current. Their fusing rate is required to reach 100% to ensure reliable melting in emergency situations. However, when a polysilicon fuse comes into contact with silicon nitride (SiN), the tensile stress in SiN can cause deformation of the polysilicon structure, affecting its electrical and thermal properties, and consequently, the fuse's response time and melting effectiveness. Furthermore, the difference in thermal expansion coefficients between SiN and polysilicon can induce thermal stress concentration, further compromising the fuse's reliability.

[0003] Therefore, improving the firing yield of polycrystalline silicon fuse structures while ensuring their good electrical and thermal properties is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a method for manufacturing a polycrystalline silicon fuse structure and a semiconductor device, which achieves the technical effect of improving the burn-in yield of the polycrystalline silicon fuse structure while ensuring good electrical and thermal properties.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, embodiments of this application provide a method for manufacturing a polycrystalline silicon fused wire structure, the method comprising: Deposit a dielectric protective layer on a polycrystalline silicon filament structure on which metal silicides have been grown; A photoresist layer is formed on the dielectric protective layer, retaining the photoresist layer of the polysilicon fuse structure fuse region to expose the dielectric protective layer of other non-polysilicon fuse structure fuse regions; The dielectric protective layer of the other non-polysilicon fuse structure fuse region is removed by etching, and then the photoresist layer of the polysilicon fuse structure fuse region is removed to obtain a pre-treated polysilicon fuse structure with a dielectric protective layer. A stress capping layer is deposited on the pretreated polycrystalline silicon fuse structure to obtain a polycrystalline silicon fuse structure with differentiated film layers, wherein the fuse region of the polycrystalline silicon fuse structure with differentiated film layers is covered by the dielectric protective layer and the stress capping layer, and the fuse region of other non-polycrystalline silicon fuse structures is covered by the stress capping layer.

[0006] This embodiment provides a method for manufacturing a polysilicon fuse structure. A dielectric protective layer is deposited on the polysilicon fuse structure to provide electrical isolation and thermal stability, preventing damage to the fuse region from electric arcs or short circuits and reducing heat accumulation. Next, the formation and removal of a photoresist layer ensures precise separation of the polysilicon fuse region from other non-polysilicon fuse regions, avoiding manufacturing errors and guaranteeing the accuracy of the polysilicon fuse structure's shape and dimensions. After etching away the dielectric protective layer from other non-polysilicon fuse regions, the dielectric protective layer is retained in the polysilicon fuse region, ensuring the polysilicon fuse structure remains undamaged. Finally, a stress-capping layer is deposited in all areas to adjust the stress distribution between the polysilicon fuse region and other non-polysilicon fuse regions, optimizing mechanical stability and reducing warping or fracture caused by stress concentration. Through the coordinated action of these steps, the stability and reliability of the polycrystalline silicon fuse structure are improved while ensuring that the performance of other non-polycrystalline silicon fuse structures, i.e., other regions of the device, remains unchanged, thereby increasing the yield of the firing process.

[0007] In one embodiment, the dielectric protective layer is silicon oxide or silicon oxynitride.

[0008] In one embodiment, the thickness of the dielectric protective layer is 100-200 angstroms.

[0009] In one embodiment, the method for depositing the dielectric protective layer is chemical vapor deposition, and the process parameters for the chemical vapor deposition are as follows: The deposition temperature of the dielectric protective layer is 380-420℃, the deposition pressure is 4-6 Torr, the bias power is 160-200W, the deposition time is 14-18s, and the deposition gas flow rates are: 30-40 sccm for SiH4; 9000-11000 sccm for N2O; and 8000-10000 sccm for HE.

[0010] In one embodiment, the thickness of the photoresist layer is 7000-8000 angstroms.

[0011] In one embodiment, the etching method is dry etching, and the process parameters for dry etching are as follows: The etching gas used in the etching process is at least one of CF4, CHF3, CH3F, C4F8, O2, and Ar. The etching bias power is 500-2000W, the etching pressure is 40-60mTorr, the etching time is 40-60s, and the etching gas mass flow rate is 100-500sccm.

[0012] In one embodiment, the stress-coating layer is silicon nitride.

[0013] In one embodiment, the method for depositing the stress capping layer is chemical vapor deposition, and the process parameters for the chemical vapor deposition are as follows: The deposition temperature of the stress capping layer is 390-410℃, the deposition pressure is 5-7 Torr, the bias power is 40-60W, the deposition time is 50-70s, and the deposition gas flow rates are: 20-40 sccm for SiH4; 40-60 sccm for NH3; and 19000-21000 sccm for N2.

[0014] In one embodiment, the growth of the metal silicide is performed using physical vapor deposition, and the process parameters for the physical vapor deposition are as follows: The deposition rate of the metal silicide is 300 to 400 angstroms per minute, the deposition time is 10-20 seconds, the material of the metal silicide is a nickel-platinum alloy, titanium or cobalt, and the thickness of the metal silicide is 140-180 angstroms.

[0015] Secondly, embodiments of this application provide a semiconductor device, which is prepared using the manufacturing method of the polycrystalline silicon fused structure described above. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a method for manufacturing a polycrystalline silicon fuse structure, as provided in this application embodiment; Figure 2 A detailed process flow diagram is provided for the embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Polycrystalline silicon fuses (PSFs) are indispensable materials in the field of integrated circuits, commonly used for circuit protection, especially in the event of faults or voltage overloads. Their primary function is to quickly disconnect the circuit when an abnormal current occurs, protecting downstream circuitry from damage. Therefore, the fusing rate of the fuse is crucial, typically requiring a 100% fusing rate. This means that in emergency situations, the fuse must be able to melt quickly and reliably, without any "spun fuse" – where the fuse partially melts while other parts of the circuit remain connected.

[0020] In advanced integrated circuit manufacturing processes, to further improve device performance, especially electron mobility, designers typically place the active region and polysilicon gate directly into silicon nitride (Si3N4). Silicon nitride plays a crucial role in this process, often used as a contact hole etch stop layer (CESL). Due to its physical properties, silicon nitride often exhibits significant tensile stress (approximately 1.3 GPa), which helps optimize the electrical performance of the device, particularly by increasing electron migration speed, thereby improving the overall device efficiency.

[0021] However, when silicon nitride with significant tensile stress directly contacts a polycrystalline silicon fuse, a series of problems may arise. First, the tensile stress of silicon nitride may cause deformation of the polycrystalline silicon structure. The polycrystalline silicon fuse itself is composed of fine silicon grains, and the arrangement and structure of these grains are highly sensitive. When external stress is excessive, it may affect the arrangement of these grains, leading to changes in the physical properties of the polycrystalline silicon. This deformation not only alters the electrical properties of the polycrystalline silicon (such as conductivity and fusing ability) but may also affect its thermal properties. The thermal conductivity and coefficient of thermal expansion of polycrystalline silicon may also change due to the introduction of stress, resulting in a less than expected response time and fusing effect of the fuse, thus affecting the stability and reliability of the entire circuit.

[0022] Furthermore, the contact between silicon nitride and polysilicon can lead to thermal stress concentration. During thermal cycling, the difference in their coefficients of thermal expansion can cause additional thermal stress at the contact interface. This accumulation of thermal stress can further exacerbate the deformation of the polysilicon structure, ultimately affecting the reliability of the fuse.

[0023] Therefore, improving the firing yield of polycrystalline silicon fuse structures while ensuring their good electrical and thermal properties is a pressing technical problem that needs to be solved.

[0024] To address the aforementioned technical problems, according to an embodiment of this application, a method for manufacturing a polycrystalline silicon fuse structure is provided. Figure 1A flowchart illustrating a method for manufacturing a polycrystalline silicon fuse structure provided in this application embodiment is shown below. Figure 1 As shown, the process includes the following steps: Step S1: Deposit a dielectric protective layer on the polycrystalline silicon filament structure on which the metal silicide has been grown.

[0025] Specifically, the dielectric protective layer protects the polycrystalline silicon fused structure from external environmental influences such as moisture, oxidation, or thermal shock. The dielectric protective layer is typically made of silicon oxide (SiO2) or silicon oxynitride (SiNO). These materials possess good insulation properties and chemical stability, effectively isolating the circuit from external environmental influences. Preferably, the dielectric protective layer is deposited using chemical vapor deposition (CVD). The CVD process parameters are as follows: deposition temperature of 380-420℃, ensuring film quality while avoiding thermal damage to the substrate; deposition pressure of 4-6 Torr, controlling the appropriate pressure facilitates the deposition reaction and ensures film quality; bias power of 160-200W, which affects the electric field strength, thus influencing the density and structure of the deposited layer. Appropriate bias power allows for control of film stress and thickness; and deposition time of 14-18s ensures a suitable thickness for the silicon oxide or silicon oxynitride layer, providing sufficient protection without excessive thickness leading to thermal stress concentration. The deposition gas flow rates are as follows: SiH4 (tetrahydrosilane) is used as the silicon source gas at a mass flow rate of 30-40 sccm for depositing silicon materials; N2O (nitrous oxide) is used as the oxygen source gas at a mass flow rate of 9000-11000 sccm to provide oxygen in the reaction and help form the silicon oxide layer; HE (helium oxide) is used as the dilution gas at a mass flow rate of 8000-10000 sccm to adjust the reaction atmosphere, reduce the deposition temperature and pressure, and ensure the stability of the deposition process. These process parameters ensure a dielectric protective layer thickness of 100-200 angstroms.

[0026] In a preferred embodiment, the metal silicide is grown by physical vapor deposition, and the process parameters of physical vapor deposition are: the deposition rate of the metal silicide is 300 to 400 angstroms per minute, the deposition time is 10-20 s, the material of the metal silicide is nickel-platinum alloy, titanium or cobalt, and the thickness of the metal silicide is 140-180 angstroms.

[0027] Specifically, the growth of metal silicides employs physical vapor deposition (PVD), a method that transforms metallic materials into thin films and deposits them onto a substrate through a vapor-phase reaction. In this process, the chosen metal silicides are nickel-platinum alloys, titanium, or cobalt. Each material offers specific advantages in electronic devices: nickel-platinum alloys possess excellent conductivity and high-temperature resistance, making them suitable for high-reliability circuit protection. Titanium exhibits strong corrosion resistance and is commonly used as a thin-film material in high-temperature environments. Cobalt has a high melting point and good mechanical strength, making it suitable for applications requiring high electrical performance and durability. The deposition rate is 300 to 400 angstroms per minute, indicating a relatively thin metal silicide layer that can be deposited quickly and uniformly. The deposition time is 10-20 seconds, ensuring that the thickness and quality of the deposited layer meet requirements. The metal silicide deposition thickness is 140-180 angstroms, a range that ensures electrical connectivity without causing poor contact or other performance issues due to excessive thickness.

[0028] Step S3: A photoresist layer is formed on the dielectric protection layer, retaining the photoresist layer of the fuse region of the polysilicon fuse structure to expose the dielectric protection layer of the fuse regions of other non-polysilicon fuse structures.

[0029] Specifically, a fuse region is a region in a semiconductor circuit that can be melted, typically used for protection, programmable circuit breaking, or fuse functions. Fuse regions are made of polysilicon (poly-Si) because polysilicon can be melted by heating or electric current. A photoresist layer is used for pattern transfer via photolithography. Under light irradiation, certain areas become soluble or insoluble through a chemical reaction, thus forming the desired pattern. During manufacturing, photoresist protects specific areas from unwanted exposure to subsequent processes such as etching and ion implantation. In this embodiment, the photoresist layer needs to be uniformly coated to ensure a consistent thickness across the entire surface during subsequent exposure and development. After the photoresist layer is coated, pattern transfer is performed using photolithography. During photolithography, a selected light source (such as ultraviolet light) irradiates the photoresist layer, and only certain areas undergo a chemical reaction, becoming soluble. The desired pattern is then transferred onto the photoresist layer using a mask or photomask. After exposure, the photoresist in the unexposed areas is removed using a developer. The photoresist layer in the polysilicon fuse structure is selectively retained, while the dielectric protective layer in other non-polysilicon fuse structure areas is exposed to ensure that this part can maintain the protective effect of the photoresist in subsequent processes.

[0030] In a preferred embodiment, the thickness of the photoresist layer is 7000-8000 angstroms.

[0031] Specifically, the thickness of the photoresist layer is 7000-8000 angstroms. If the thickness is too thin, the photoresist may not effectively protect the fused area during subsequent etching, resulting in unclear or inaccurate patterns; while an excessively thick photoresist layer may lead to unnecessary process complexity, affecting the control and effectiveness of subsequent steps. A photoresist layer of appropriate thickness also helps avoid photoresist detachment or unevenness caused by being too thick or too thin.

[0032] Step S5: Etch away the dielectric protective layer of the fuse region of other non-polysilicon fuse structures, and then remove the photoresist layer of the fuse region of the polysilicon fuse structure to obtain the pretreated polysilicon fuse structure with the dielectric protective layer formed.

[0033] Specifically, etching is used to remove excess material, leaving the desired pattern or structure. In this embodiment, it is used to remove the dielectric protective layer of the fuse region in other non-polysilicon fuse structures. Next, the photoresist layer of the fuse region in the polysilicon fuse structure is removed using ASHER (plasma dry cleaning) and WET (wet cleaning) methods to obtain a pretreated polysilicon fuse structure for forming the dielectric protective layer.

[0034] In a preferred embodiment, the etching method is dry etching, and the process parameters for dry etching are as follows: the etching gas used is at least one of CF4, CHF3, CH3F, C4F8, O2, and Ar; the etching bias power is 500-2000W, the etching pressure is 40-60mTorr, the etching time is 40-60s, and the mass flow rate of the etching gas is 100-500sccm.

[0035] Specifically, the basic principle of dry etching is to utilize the reaction of ions or free radicals in the etching gas with the surface to be etched, thereby removing the dielectric protective layer. Dry etching offers more precise control compared to wet etching, allowing for fine control over etching depth, selectivity, and pattern fidelity. In dry etching, fluoride gases such as CF4, CHF3, and C4F8 are primarily used to etch silicon-containing materials. Fluorine reacts with silicon or oxides to form volatile fluorides (such as SiF4 and SiO2F2), thus removing the material. CH3F is used to remove organic materials, or in some cases, it is mixed with other gases to optimize the etching reaction. O2 enhances oxide removal during the etching process, helping to remove organic materials and oxide layers. Ar is generally used as an inert gas, serving as a carrier gas for the etching process, helping to provide a uniform plasma distribution within the reaction chamber, while also accelerating ions.

[0036] The bias power controls the energy of ion acceleration, affecting the etching depth and selectivity. Higher power increases ion energy, leading to increased etching rate and depth, but may also result in unwanted sputtering or over-etching. Insufficient power may result in incomplete etching or an incomplete reaction. In this process, a power range of 500-2000W allows for adjustment based on the characteristics of the dielectric protective layer and etching precision requirements to achieve optimal results.

[0037] Etching pressure controls the plasma density and ion collision frequency. Higher pressure increases plasma density and accelerates ion generation and reaction rates; however, excessively high pressure may lead to decreased etching selectivity, resulting in etching of non-target areas. A pressure range of 40-60 mTorr is moderate, balancing etching rate and selectivity while reducing excessive sputtering.

[0038] Etching time affects the etching depth and precision. Too long a time may result in excessive etching depth, damaging unwanted areas; too short a time may lead to incomplete etching. A time range of 40-60 seconds is sufficient to achieve the desired etching depth.

[0039] The gas flow rate determines the concentration of the etching gas, affecting the plasma density and its reactivity. Too low a flow rate may result in incomplete etching, while too high a flow rate may lead to poor etching selectivity. A flow rate range of 100-500 sccm provides sufficient reactive gas to ensure continuous plasma generation and maintain adequate reactivity during etching.

[0040] Step S7: Deposit a stress capping layer on the pretreated polycrystalline silicon fuse structure to obtain a polycrystalline silicon fuse structure with differentiated film layers, wherein the fuse region of the polycrystalline silicon fuse structure with differentiated film layers is covered with a dielectric protective layer and a stress capping layer, and the fuse region of other non-polycrystalline silicon fuse structures is covered with a stress capping layer.

[0041] Specifically, a stress-coating layer covers all areas to regulate mechanical stress and protect the polysilicon fuse structure. Stress management improves device stability and prevents uneven fuse warping or breakage. Differentiated coatings mean different regions have different stresses or thicknesses to optimize fuse fusing performance and reliability. For example, the stress in the fuse region of a polysilicon fuse structure, where a dielectric protective layer exists, differs from that in the fuse region of a non-polysilicon fuse structure, ensuring preferential fusing in the fuse region upon power-up, while simultaneously ensuring that device performance in other non-polysilicon fuse regions remains unaffected.

[0042] In a preferred embodiment, the stress-coating layer is silicon nitride, which has the following characteristics: high mechanical strength, good chemical inertness, and adjustable internal stress (compressive or tensile stress). Using silicon nitride can enhance the mechanical stability of the fuse structure; reduce fuse warping or breakage due to stress concentration; and provide additional insulation and protection.

[0043] In a preferred embodiment, the method for depositing the stress capping layer is chemical vapor deposition (CVD). The CVD process parameters are as follows: deposition temperature of the stress capping layer is 390-410℃, deposition pressure is 5-7 Torr, bias power is 40-60W, deposition time is 50-70s, and deposition gas flow rates are as follows: SiH4 gas mass flow rate is 20-40 sccm; NH3 gas mass flow rate is 40-60 sccm; and N2 gas mass flow rate is 19000-21000 sccm.

[0044] Specifically, chemical vapor deposition (CVD) ensures a uniform stress-coated film. A deposition temperature of 390-410℃ reduces thermal damage to the polycrystalline silicon filament structure. It also sufficiently activates the gas reaction, guaranteeing a dense and uniform silicon nitride film. A deposition pressure of 5-7 Torr, being relatively low, helps control the film growth rate. A bias power of 40-60W enhances ion bombardment activation of the film, regulating internal stress (compressive or tensile). A deposition time of 50-70 seconds avoids excessive stress caused by an overly thick film, preserving the inherent characteristics of the polycrystalline silicon filament structure.

[0045] This embodiment provides a method for manufacturing a polysilicon fuse structure. A dielectric protective layer is deposited on the polysilicon fuse structure to provide electrical isolation and thermal stability, preventing damage to the fuse region from electric arcs or short circuits and reducing heat accumulation. Next, the formation and removal of a photoresist layer ensures precise separation of the polysilicon fuse region from other non-polysilicon fuse regions, avoiding manufacturing errors and guaranteeing the accuracy of the polysilicon fuse structure's shape and dimensions. After etching away the dielectric protective layer from other non-polysilicon fuse regions, the dielectric protective layer is retained in the polysilicon fuse region, ensuring the polysilicon fuse structure remains undamaged. Finally, a stress-capping layer is deposited on all areas to adjust the stress distribution between the polysilicon fuse region and other non-polysilicon fuse regions, optimizing mechanical stability and reducing warping or fracture caused by stress concentration. Through the coordinated action of these steps, the stability and reliability of the polycrystalline silicon fuse structure are improved while ensuring that the performance of other non-polycrystalline silicon fuse structures, i.e., other regions of the device, remains unchanged, thereby increasing the yield of the firing process.

[0046] The specific implementation of the present invention will now be described in conjunction with a specific process. Figure 2This is a detailed process flow diagram provided for embodiments of this application. It should be noted that Poly refers to a polysilicon filament structure, and STI refers to shallow trench isolation. The specific process steps are as follows: Step S1001: Perform metal silicide process to grow NiSi using physical vapor deposition technology. The deposition rate of the metal silicide is 350 angstroms per minute, the deposition time is 15 seconds, the material of the metal silicide is nickel-platinum alloy, and the thickness of the metal silicide is 160 angstroms.

[0047] Step S1002: A dielectric protective silicon oxide layer is deposited on the polycrystalline silicon filament structure with completed metal silicide growth using chemical vapor deposition. The deposition temperature is 400℃, the deposition pressure is 5 Torr, the bias power is 180W, the deposition time is 16s, and the deposition gases are SiH4 with a gas mass flow rate of 35 sccm, N2O with a gas mass flow rate of 10000 sccm, and HE with a gas mass flow rate of 9000 sccm. The thickness of the resulting dielectric protective silicon oxide layer is 150 angstroms.

[0048] Step S1003: Form a photoresist layer with a thickness of 7500 angstroms on the dielectric protection layer, retaining the photoresist layer of the fuse region of the polysilicon fuse structure to expose the dielectric protection layer of the fuse regions of other non-polysilicon fuse structures.

[0049] Step S1004: Dry etching is used, with CF4 as the etching gas, a bias power of 1000W, an etching pressure of 50mTorr, an etching time of 50s, and a gas mass flow rate of 300sccm. The dielectric protective layer of the fuse region of other non-polysilicon fuse structures is removed, and then the photoresist layer of the fuse region of the polysilicon fuse structure is removed to obtain the pretreated polysilicon fuse structure with the dielectric protective layer formed.

[0050] Step S1005: Chemical vapor deposition is used at a deposition temperature of 400℃, a deposition pressure of 6 Torr, a bias power of 50W, a deposition time of 60s, and deposition gas flow rates of: SiH4 gas mass flow rate of 30 sccm; NH3 gas mass flow rate of 50 sccm; and N2 gas mass flow rate of 20000 sccm. A stress capping layer of silicon nitride is deposited on the pretreated polycrystalline silicon fuse structure to obtain a polycrystalline silicon fuse structure with differentiated film layers. The fuse region of the polycrystalline silicon fuse structure with differentiated film layers is covered with a dielectric protective layer and a stress capping layer, while the fuse regions of other non-polycrystalline silicon fuse structures are covered with a stress capping layer.

[0051] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. The above descriptions are merely embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

[0053] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method of fabricating a polysilicon fuse structure, characterized by, The method comprises: depositing a dielectric protection layer on the polysilicon fuse structure of grown metal silicide; forming a photoresist layer on the dielectric protection layer, leaving the photoresist layer of the polysilicon fuse structure fuse area to expose the dielectric protection layer of other non-polysilicon fuse structure fuse area; etching to remove the dielectric protection layer of the other non-polysilicon fuse structure fuse area, and then removing the photoresist layer of the polysilicon fuse structure fuse area to obtain a pretreated polysilicon fuse structure with a dielectric protection layer; depositing a stress cover layer on the pretreated polysilicon fuse structure to obtain a polysilicon fuse structure with differentiated film layers, wherein the polysilicon fuse structure fuse area is covered with the dielectric protection layer and the stress cover layer, and the other non-polysilicon fuse structure fuse area is covered with the stress cover layer.

2. The method of claim 1, wherein, The dielectric protection layer is silicon oxide or silicon oxynitride.

3. The method of claim 1, wherein, The thickness of the dielectric protection layer is 100-200 angstroms.

4. The method of claim 1, wherein, The method of depositing the dielectric protection layer is chemical vapor deposition, and the process parameters of the chemical vapor deposition are: The deposition temperature of the dielectric protection layer is 380-420℃, the deposition pressure is 4-6 Torr, the bias power is 160-200W, the deposition time is 14-18s, and the deposition gas flow rate is: the gas mass flow rate of SiH4 is 30-40sccm; the gas mass flow rate of N2O is 9000-11000sccm; the gas mass flow rate of HE is 8000-10000sccm.

5. The method of claim 1, wherein, The thickness of the photoresist layer is 7000-8000 angstroms.

6. The method of claim 1, wherein, The method of etching is dry etching, and the process parameters of the dry etching are: The etching gas used in the etching is at least one of CF4, CHF3, CH3F, C4F8, O2 and Ar; The bias power of the etching is 500-2000W, the etching pressure is 40-60mTorr, the etching time is 40-60s, and the gas mass flow rate of the etching gas is 100-500sccm.

7. The method of claim 1, wherein, The stress cover layer is silicon nitride.

8. The method of claim 1, wherein, The method of depositing the stress cover layer is chemical vapor deposition, and the process parameters of the chemical vapor deposition are: The deposition temperature of the stress cover layer is 390-410℃, the deposition pressure is 5-7 Torr, the bias power is 40-60W, the deposition time is 50-70s, and the deposition gas flow rate is: the gas mass flow rate of SiH4 is 20-40sccm; the gas mass flow rate of NH3 is 40-60sccm; the gas mass flow rate of N2 is 19000-21000sccm.

9. The method of claim 1, wherein, The grown metal silicide is deposited by physical vapor deposition, and the process parameters of the physical vapor deposition are: The deposition rate of the metal silicide is 300 angstroms per minute to 400 angstroms per minute, the deposition time is 10-20s, the material of the metal silicide is nickel platinum alloy, titanium or cobalt, and the thickness of the metal silicide is 140-180 angstroms.

10. A semiconductor device, characterized by comprising: The semiconductor device is prepared by the manufacturing method of the polysilicon fuse structure according to any one of claims 1-9.

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