Chip packaging structure and method

Abstract

The invention relates to the technical field of semiconductor processing, in particular to a chip packaging structure and method.The chip packaging structure comprises basic packaging modules, a rewiring layer and protruding points, the multiple basic packaging modules are vertically stacked, and anisotropic conductive adhesive is arranged between every two vertically-adjacent basic packaging modules; a rewiring layer is arranged on the exposed bonding pad of the basic packaging module at the end part; and a plurality of salient points are arranged on the surface of the rewiring layer. Compared with the prior art, single modules are firstly tested and screened, and damaged modules are removed, so that the overall yield is improved; interconnection points among the modules are fewer and more standardized, and the stress is dispersed to the module level by the plastic package body instead of directly acting on all chips, so that the stress is reduced; in-module short-distance interconnection and inter-module standardized vertical interconnection are adopted, the process difficulty and cost are remarkably reduced, the product yield and long-term reliability are improved, and the packaging size is accurately controlled.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, specifically a chip packaging structure and method. Background Technology

[0002] With the explosive growth in storage capacity demand from applications such as artificial intelligence and high-performance computing, increasing storage density by increasing the number of chip stacking layers has become the mainstream technology direction in the industry.

[0003] However, increasing the stacking height also brings a series of challenges: the overall yield of a solution where all chips are stacked at once and interconnected uniformly will be significantly reduced due to defects in a single chip or interconnect failures at some point; the increase in height will exacerbate thermal and mechanical stress, affecting the long-term reliability of the package; the increase in height requires longer interconnect channels, which increases the difficulty and cost of the process; traditional stacking methods are often accompanied by a simultaneous increase in package size, which limits their application in scenarios such as ultra-thin mobile devices.

[0004] Therefore, it is necessary to design a chip packaging structure and method to improve overall yield and long-term reliability, reduce process difficulty and cost, and enable precise control of package size. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a chip packaging structure and method to improve overall yield and long-term reliability, reduce process difficulty and cost, and enable precise control of packaging volume.

[0006] To achieve the above objectives, the present invention provides a chip packaging structure, including a base packaging module, a redistribution layer, and bumps. Several base packaging modules are vertically stacked, and anisotropic conductive adhesive is provided between two adjacent base packaging modules. A redistribution layer is provided on the exposed pads of the base packaging modules at the ends, and several bumps are provided on the surface of the redistribution layer.

[0007] The basic packaging module includes vertical leads, chips, leads, and epoxy resin. Several homogeneous chips are stacked in a staggered manner in the vertical direction and interconnected by leads. Vertical leads are provided on the side of the chips. The vertical leads, chips, and leads are encapsulated in epoxy resin.

[0008] When the basic package modules are stacked vertically, the ends of the vertical leads contact the anisotropic conductive adhesive or redistribution layer to achieve interconnection between the basic package modules and between the basic package modules and the redistribution layer.

[0009] The diameter of the vertical lead is 12~50μm, and the height of the vertical lead is higher than the total stacking height of the chip.

[0010] The aforementioned leads are electrically connected between chips using wire bonding technology.

[0011] The number of basic packaging modules is matched to the system capacity requirements.

[0012] A chip packaging method includes the following steps: Step 1, using photodegradable adhesive as bonding glue on a glass temporary carrier, and mounting chips according to the design layout; Step 2, using wire bonding technology to complete the electrical interconnection between several chips with gold wires; Step 3, forming vertical leads at reserved positions next to the chips using a wire bonding machine with a half-cutting blade; Step 4, encapsulating with epoxy resin, and grinding and polishing the module with vertical leads until the circular end face of the vertical leads is exposed; Step 5, decomposing the photodegradable adhesive by laser irradiation, separating the glass carrier, and obtaining independent basic packaging modules; Step 6, aligning the vertical leads of two adjacent basic packaging modules with anisotropic conductive adhesive and performing thermo-press bonding to achieve electrical and mechanical connection; Step 7, fabricating a redistribution layer on the exposed pads of the basic packaging module located at the end, and then fabricating bumps.

[0013] Steps 1 to 5 can be used to create several basic encapsulation modules in parallel.

[0014] Compared with existing technologies, this invention first tests and screens individual modules to eliminate damaged modules, thereby improving the overall yield; there are fewer and more standardized interconnect points between modules, and the molding compound disperses stress at the module level rather than directly affecting all chips, thereby reducing stress; the use of short-pitch interconnects within modules and standardized vertical interconnects between modules significantly reduces process difficulty and cost, improves product yield and long-term reliability, and enables precise control of package size. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of the present invention.

[0016] Figure 2 This is a schematic diagram of the packaging method of the present invention. Detailed Implementation

[0017] The present invention will now be further described with reference to the accompanying drawings.

[0018] See Figure 1 The present invention is a chip packaging structure, including a basic packaging module, a redistribution layer, and bumps. Several basic packaging modules 1 are stacked vertically. Anisotropic conductive adhesive 2 is provided between two adjacent basic packaging modules 1. A redistribution layer 3 is provided on the exposed pad of the basic packaging module 1 at the end. Several bumps 4 are provided on the surface of the redistribution layer 3.

[0019] The basic packaging module 1 includes vertical leads 11, chips 12, leads 13, and epoxy resin 14. Several homogeneous chips 12 are stacked in a staggered manner in the vertical direction and interconnected by leads 13. Vertical leads 11 are provided on the side of the chips 12. Vertical leads 11, chips 12, and leads 13 are encapsulated in epoxy resin 14.

[0020] When the basic packaging modules 1 are stacked vertically, the end of the vertical lead 11 contacts the anisotropic conductive adhesive 2 or the redistribution layer 3 to achieve interconnection between the basic packaging modules 1 and the interconnection between the basic packaging modules 1 and the redistribution layer 3.

[0021] The diameter of the vertical lead 11 is 12~50μm, and the height of the vertical lead 11 is higher than the total stacking height of the chip 12, so as to facilitate the electrical and mechanical connection of the vertical lead 11.

[0022] Lead 13 uses wire bonding technology to achieve electrical connection between chips 12.

[0023] The number of basic encapsulation modules 1 matches the system capacity requirements.

[0024] See Figure 2 A chip packaging method includes the following steps: Step 1, using photodegradable adhesive as bonding glue on a glass temporary carrier, and mounting chips according to the design layout; Step 2, using wire bonding technology to complete the electrical interconnection between several chips with gold wires; Step 3, forming vertical leads at reserved positions next to the chips using a wire bonding machine with a half-cutting blade; Step 4, encapsulating with epoxy resin and grinding and polishing the module with vertical leads until the circular end face of the vertical leads is exposed; Step 5, decomposing the photodegradable adhesive by laser irradiation, separating the glass carrier, and obtaining independent basic packaging modules; Step 6, aligning the vertical leads of two adjacent basic packaging modules with anisotropic conductive adhesive and performing thermo-press bonding to achieve electrical and mechanical connection; Step 7, after fabricating a redistribution layer on the exposed pads of the basic packaging module located at the end, then fabricating bumps.

[0025] Steps 1 through 5 can be used to create several basic encapsulation modules in parallel to improve efficiency.

[0026] This invention first tests and screens individual modules to eliminate damaged modules, thereby improving the overall yield; there are fewer and more standardized interconnect points between modules, and the molding compound disperses stress at the module level rather than directly affecting all chips, thereby reducing stress; the use of short-pitch interconnects within modules and standardized vertical interconnects between modules significantly reduces process difficulty and cost, improves product yield and long-term reliability, and enables precise control of package size.

Claims

1. A chip package structure, comprising a base package module, a redistribution layer, a bump, characterized in that: A plurality of basic packaging modules (1) are vertically stacked, anisotropic conductive adhesive (2) is arranged between two adjacent basic packaging modules (1) in the vertical direction, a redistribution layer (3) is arranged on the exposed pad of the basic packaging module (1) at the end, and a plurality of bumps (4) are arranged on the surface of the redistribution layer (3), The basic packaging module (1) comprises vertical leads (11), chips (12), leads (13) and epoxy resin (14), a plurality of homogeneous chips (12) are stacked in the vertical direction and interconnected by leads (13), vertical leads (11) are arranged on the side of the chip (12), and the vertical leads (11), the chip (12) and the lead (13) are plastic encapsulated in the epoxy resin (14), When the basic packaging modules (1) are vertically stacked, the end of the vertical lead (11) is in contact with the anisotropic conductive adhesive (2) or the redistribution layer (3), realizing the interconnection between the basic packaging modules (1) and the interconnection between the basic packaging module (1) and the redistribution layer (3).

2. The chip package structure of claim 1, wherein: The diameter of the vertical lead (11) is 12-50μm, and the height of the vertical lead (11) is higher than the total stacking height of the chip (12).

3. The chip package structure of claim 1, wherein: The lead (13) realizes the electrical connection between the chips (12) by wire bonding process.

4. The chip package structure of claim 1, wherein: The number of basic packaging modules (1) is matched with the system capacity demand.

5. A method of packaging a chip package structure as claimed in any one of claims 1 to 4, characterized by: The method comprises the following steps: step 1, on a glass temporary carrier, using photodegradable glue as bonding glue, according to the design layout, chip mounting is performed; step 2, using wire bonding process, gold wire is used to complete the electrical interconnection between a plurality of chips; step 3, at the reserved position on the side of the chip, a vertical lead is formed by using a half-cut wedge-shaped knife of a wire bonding machine; step 4, epoxy resin is used for plastic encapsulation, and the module with vertical leads is polished until the round end surface of the vertical lead is exposed; step 5, the photodegradable glue is decomposed by laser irradiation, and the glass carrier is dissociated, to obtain an independent basic packaging module; step 6, the vertical leads of two adjacent basic packaging modules are aligned and hot-pressed by anisotropic conductive adhesive, to realize electrical and mechanical connection; step 7, after the redistribution layer is made on the exposed pad of the basic packaging module at the end, the bumps are made.

6. The packaging method of a chip package structure according to claim 5, wherein: Steps 1-5 can be used to make a plurality of basic packaging modules in parallel.

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