Trans-impedance amplifier for crossbar circuit

Abstract

The invention provides a transimpedance amplifier for a crossbar circuit. The crossbar circuit includes a plurality of bit lines crossing a plurality of word lines and a plurality of crossbar devices. Each of the plurality of cross-point devices is connected to at least one word line and at least one bit line. The crossbar circuit may further include a transimpedance amplifier to generate an output voltage representative of a sum of currents flowing through a first bit line of the plurality of bit lines. The transimpedance amplifier may include an operational amplifier, a current mirroring circuit connected to an output of the operational amplifier, and one or more resistors connected to the current mirroring circuit and a supply voltage.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 361,306, filed July 28, 2023, entitled “Transimpedance Amplifier for Cross-Switching Circuits,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure generally relate to electronic devices, and more specifically, to transimpedance amplifiers for use in cross-switching circuits that include resistive random access memory (RRAM or ReRAM). Background Technology

[0003] A cross-switch circuit refers to a circuit structure with interconnecting conductive lines, where storage elements, such as resistive switching materials, are sandwiched at the intersections of the interconnecting conductive lines. The resistive switching materials may include, for example, memristors (also known as resistive random access memory (RRAM or ReRAM)). Cross-switch circuits can be used to implement in-memory computing applications, non-volatile solid-state memories, image processing applications, neural networks, etc. Summary of the Invention

[0004] The following is a brief summary of the invention disclosed to provide a basic understanding of some aspects of this disclosure. The summary is not a broad overview of this disclosure. It is not intended to identify key or essential elements of this disclosure, nor is it intended to define any scope of any particular matter or claim. The sole purpose of the summary is to simplify the presentation of some concepts of this disclosure in the more detailed description that follows.

[0005] According to one or more aspects of this disclosure, an apparatus is provided. The apparatus includes a plurality of bit lines intersecting a plurality of word lines; a plurality of cross-point devices; and a transimpedance amplifier. Each of the plurality of cross-point devices is connected to at least one word line and at least one bit line. The transimpedance amplifier generates an output voltage representing the sum of currents flowing through the first bit line among the plurality of bit lines. The transimpedance amplifier includes: an operational amplifier; a current mirror circuit connected to the output of the operational amplifier; and one or more resistors connected to the current mirror circuit and a power supply voltage.

[0006] In some embodiments, the operational amplifier is a unity-gain amplifier.

[0007] In some embodiments, the inverting input of the operational amplifier is connected to the first bit line, and the non-inverting input of the operational amplifier is connected to a reference voltage.

[0008] In some embodiments, the inverting input of the operational amplifier is connected to the output of the operational amplifier in a unity feedback configuration.

[0009] In some embodiments, the apparatus further includes a switch located between the inverting input of the operational amplifier and the output of the operational amplifier. The switch is configured to selectively connect the inverting input of the operational amplifier to the output of the operational amplifier.

[0010] In some embodiments, the current mirror circuit includes a first transistor and a second transistor, wherein a first current flowing through the first transistor corresponds to the sum of currents flowing through the first bit line, and the first current is mirrored as a second current flowing through the second transistor.

[0011] In some embodiments, the output voltage generated by the transimpedance amplifier can be expressed as Vout = Vcc - I2. R FB Where Vout is the output voltage generated by the transimpedance amplifier, Vcc is the power supply voltage, I2 is the second current flowing through the second transistor, and R FB This indicates the resistance value of one or more resistors connected to the current mirror circuit and the power supply voltage.

[0012] In some embodiments, the output of the operational amplifier is electrically connected to the first source terminal of the first transistor. The second source terminal of the second transistor is electrically connected to at least one of the one or more resistors.

[0013] In some embodiments, the first gate terminal of the first transistor is electrically connected to the second gate terminal of the second transistor.

[0014] In some embodiments, the first drain terminal of the first transistor is electrically connected to the second drain terminal of the second transistor.

[0015] In some embodiments, the output voltage of the transimpedance amplifier is provided to the analog-to-digital converter (ADC).

[0016] In some embodiments, the one or more resistors are not located in the feedback loop of the operational amplifier.

[0017] In some embodiments, the crossover device includes at least one of a memristor, a phase-change memory (PCM), a floating-gate device, a spintronic device, a ferroelectric device, or a resistive random access memory (RRAM) device. The crossover device may include a transistor or a designated device used as a selector. Attached Figure Description

[0018] This disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments thereof. However, the drawings should not be used to limit this disclosure to the particular embodiments, but are for explanation and understanding only.

[0019] Figure 1 This is a block diagram illustrating an example of a cross switch circuit according to some embodiments of the present disclosure; Figure 2A and 2B This is a schematic diagram illustrating examples of intersection devices according to some embodiments of the present disclosure; Figure 3 This is a schematic diagram illustrating a prior art transimpedance amplifier; Figure 4 This is a schematic diagram illustrating an example of a transimpedance amplifier according to some embodiments of the present disclosure. Detailed Implementation

[0020] Some aspects of this disclosure provide transimpedance amplifiers for cross-switching circuits. Cross-switching circuits may include crossed conductive lines (e.g., row lines, column lines, etc.) and crosspoint devices arranged in one or more arrays. Each of the crosspoint devices may be connected to both row and column lines. The crosspoint devices may include, for example, memristors, phase-change memory (PCM) devices, floating-gate devices, spintronic devices, ferroelectric devices, or resistive random access memory (RRAM) devices.

[0021] The crossbar switch circuit can perform vector matrix multiplication (VMM). For example, an input voltage can be applied to each selected row in the crossbar switch circuit. The input voltage can flow through the crosspoint devices on the rows of the crossbar switch circuit. The conductance of each crosspoint device can be adjusted to a specific value (also known as a "weight"). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar switch circuit can be expressed as I=VG, where I represents the output signal matrix, which is current; V represents the input signal matrix, which is voltage; and G represents the conductance matrix of the crosspoint devices. Therefore, according to Ohm's law, the output voltage is weighted by the conductance of each crosspoint device. The weighted current is output through each column line and can be accumulated according to Kirchhoff's current law.

[0022] The cross-switching circuit typically uses a transimpedance amplifier (TIA) to convert accumulated current into an analog voltage, and then the analog voltage into a digital output. The stability and performance of a traditional TIA can be significantly affected by complex capacitive loads and current variations, both of which can fluctuate dramatically during VMM operation. The interaction between the operational amplifiers in the cross-switching circuit (e.g., operational amplifiers used to implement analog-to-digital converters and / or digital-to-analog converters), the varying current load, and the varying voltages applied to the cross-point device further exacerbates the stability challenges.

[0023] This disclosure provides a transimpedance amplifier (TIA) for use in a cross-switching circuit. The transimpedance amplifier may include an operational amplifier, a current mirror circuit connected to the output of the operational amplifier, and one or more resistors connected to the current mirror circuit and a power supply voltage. The resistors connected to the current mirror circuit are not in the feedback loop of the operational amplifier. In some embodiments, the operational amplifier is a unity-gain amplifier. The inverting and non-inverting inputs of the operational amplifier may be connected to a bit line and a reference voltage of the cross-switching circuit, respectively. The current mirror circuit may include a first transistor and a second transistor. A first current flowing through the first transistor may correspond to the sum of currents flowing through the bit line connected to the TIA. The first current may be mirrored as a second current flowing through the second transistor. The output of the TIA is related to the power supply voltage, the resistance value of the resistor connected to the current mirror circuit, and the second current flowing through the second transistor.

[0024] Unlike conventional TIAs, the TIA described in this disclosure can generate an output voltage unaffected by capacitive loads and current variations in the cross-switching circuit. By removing the feedback resistor and load from the operational amplifier loop to the mirror node in the current mirror circuit, the TIA design described in this disclosure improves the overall circuit stability of the cross-switching circuit employing this TIA design.

[0025] Figure 1 This is a block diagram illustrating an example 100 of a crossover switch circuit according to some embodiments of the present disclosure. As shown, the crossover switch circuit 100 may include multiple interconnecting conductors, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n and column lines 113a, 113b, ..., 113i, ..., 113n in an n-row by m-column crossover switch array. The crossover switch circuit 100 may further include crossover point devices 120a, 120b, ..., 120z, etc. Each crossover point device may connect one row line and one column line. For example, crossover point device 120ij may connect row line 111i and column line 113j. The number of column lines 113a-m may be the same as the number of row lines 111a-n, or they may be different. The crossover switch circuit 100 may further include word line (WL) logic 105, which is connected to the crossover point devices via row lines 111a-n. The WL logic 105 may include any suitable component, such as one or more digital-to-analog converters (DACs), amplifiers, etc., that can be used to apply input signals through row lines 111a-n to selected cross-point devices. Each input signal may be a voltage signal, a current signal, etc.

[0026] Row lines 111a-n may include a first row line 111a, a second row line 111b, ..., 111i, ... and an nth row line 111n. Each of row lines 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal wire. In some embodiments, each row line 111a-n may be a word line.

[0027] Column lines 113a-m may include a first column line 113a, a second column line 113b, ..., and an m-th column line 113m. Each of the column lines 113a-m may be and / or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal wire. In some embodiments, each column line 113a-m may be a bit line.

[0028] Each cross-point device 120a-z can be and / or include any suitable device with tunable resistors, such as memristors, phase-change memory (PCM) devices, floating-gate devices, spintronic devices, ferroelectric devices, RRAM devices, etc.

[0029] Each row line 111a-n may be connected to one or more row switches 131 (e.g., row switches 131a, 131b, ..., 131n). Each row switch 131 may include any suitable circuit structure capable of controlling the current flowing through the row lines 111a-n. For example, the row switch 131 may be and / or include CMOS switching circuitry.

[0030] Each column line 113a-m can be connected to one or more column switches 133 (e.g., switches 133a, ..., 133m). Each column switch 133a-m may include any suitable circuit structure capable of controlling the current flowing through the column line 113a-m. For example, the column switch 133a-m may be and / or include CMOS switching circuitry. In some embodiments, one or more of the switches 131a-n and 133a-m may further provide fault protection, electrostatic discharge (ESD) protection, noise reduction, and / or other suitable functions for one or more portions of the cross-switch circuit 100.

[0031] Output sensor 140 may include any suitable component for converting the current flowing through column lines 113a-m into an output signal, such as one or more TIAs (transimpedance amplifiers) 140a, ..., 140m. Each TIA 140a-m converts the current flowing through the corresponding column line into a corresponding voltage signal. Each ADC 150 (e.g., ADC 150a, ..., 150m) converts the voltage signal generated by its corresponding TIA into a digital output. In some embodiments, output sensor 140 may further include one or more multiplexers (not shown). In some embodiments, each of the TIAs 140a-m may include a combination of Figure 4 The TIA 400 mentioned above.

[0032] Programming circuit 160 can program crosspoint devices 120a-z selected by switches 131 and / or 133 to suitable conductance values. For example, programming a crosspoint device may involve applying a suitable voltage or current signal to the crosspoint device. The resistance value of each crosspoint device can be electrically switched between a high resistance state and a low resistance state. Setting a crosspoint device may involve switching the resistance value of the crosspoint device from a high resistance state to a low resistance state. Resetting a crosspoint device may involve switching the resistance value of the crosspoint device from a low resistance state to a high resistance state.

[0033] The cross-switch circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows of the cross-switch circuit 100 (e.g., one or more selected rows). The input signal can flow through the cross-point devices of the rows of the cross-switch circuit 100. The conductance values ​​of the cross-point devices can be adjusted to specific values ​​(also referred to as "weights"). According to Ohm's law, the input voltage signal is multiplied by the conductance value of the cross-point device, generating a current flowing through the cross-point device. According to Kirchhoff's laws, the sum of the currents flows through the activated cross-point devices in the corresponding columns (also referred to as "bit line currents"), which can be read from the column. According to Ohm's law and Kirchhoff's laws, the input-output relationship of the cross-switch array can be expressed as I=VG, where I represents the output signal matrix, which is the current; V represents the input signal matrix, which is the voltage; and G represents the conductance matrix of the cross-point devices. Therefore, according to Ohm's law, the input signal is weighted by the conductance of each cross-point device. The weighted current (“bit line current”) is output through each column line and accumulated according to Kirchhoff’s laws. This can be achieved through in-memory computation (IMC) via parallel multiplication and summation performed in the crossbar switch array.

[0034] The crossover switch circuit 100 can be configured to perform vector matrix multiplication (VMM). A VMM operation can be represented as Y = XA, where each of Y, X, and A represents a corresponding matrix. More specifically, for example, the input vector X can be mapped to the input voltage V of the crossover switch circuit 100. Vector A can be mapped to the conductance value G. The output current I can be read and mapped back to the output result Y. In some embodiments, the crossover switch circuit 100 can be configured to implement part of a neural network by performing VMM.

[0035] In some embodiments, the cross-switch circuit 100 can perform convolution operations. For example, performing a two-dimensional convolution on input data may involve applying a single convolution kernel to the input signal. Performing a depthwise convolution on input data may involve convolving each channel of the input data with a corresponding convolution kernel for that channel and stacking the convolutional outputs. The convolution kernel may have a specific size defined by multiple dimensions (e.g., width, height, channels, etc.). The convolution kernel may be applied to portions of the input data of the same size to produce an output. The output may be mapped to an element in the convolution result located at a position corresponding to that portion of the input data.

[0036] Programming circuit 160 can program cross-switching circuit 100 to store convolution kernels for performing two-dimensional convolution operations. For example, the convolution kernel can be converted into a vector and mapped to multiple intersection devices connected to a given bit line in a cross-array. Specifically, the conductance values ​​of the intersection devices can be programmed to represent the values ​​of the convolution kernel. In response to the input signal, cross-switching circuit 100 can output a current signal representing the convolution of the input signal and the two-dimensional convolution kernel via the given bit line. In some embodiments, cross-switching circuit 100 can store multiple two-dimensional convolution kernels by mapping each two-dimensional convolution kernel to an intersection device connected to a corresponding bit line. Cross-switching circuit 100 can output multiple output signals (e.g., current signals) representing the convolution result via column lines 113a-m.

[0037] Figure 2A and 2B This is a schematic diagram illustrating example crosspoint devices 1220a and 1220b according to some embodiments of the present disclosure. Each of the crosspoint devices 1220a and 1220b may be referred to as a transistor-resistor (1T1R) configuration.

[0038] like Figure 2A and 2B As shown, cross-point devices 1220a-b may include an RRAM device 1201 and a transistor 1203 connected in series. The transistor may include three terminals, which may be labeled as the gate (G), source (S), and drain (D), respectively. Reference Figure 2AThe first terminal of the RRAM device 1201 can be connected to the drain terminal of the transistor 1203. The second terminal of the RRAM device 1201 can be connected to the bit line 1211. The source terminal of the transistor 1203 can be connected to the word line 1215. The gate terminal of the transistor 1203 can be connected to the select line 1213.

[0039] like Figure 2B As shown, in some embodiments, the second terminal of the RRAM device 1201 may be connected to word line 1215, and the source terminal of the transistor 1203 may be connected to bit line 1211. Word line 1215 may correspond to... Figure 1 Row lines 111a-n. Bit line 1211 can correspond to Figure 1 The column line 113a-m.

[0040] Transistor 1203 can function as a selector and a current controller, and can set a current limit for RRAM device 1201 during programming. The gate voltage of transistor 1203 can set a current limit for crosspoint devices 1220a-b during programming, thereby controlling the conductance and analog behavior of crosspoint devices 1220a-b. For example, when crosspoint devices 1220a-b are set from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) can be provided via bit line (BL) 1211 or word line (WL) 1215. Another voltage, also known as the select voltage or gate voltage, can be applied to the transistor gate via select line (SEL) 1213 to turn on the gate and set the current limit, while word line (WL) 1215 or bit line (BL) can be grounded. When crosspoint devices 1220a-b are reset from a low-resistance state to a high-resistance state, the gate voltage can be applied to the gate of transistor 1203 via select line 1213 to turn on the transistor gate. Meanwhile, a reset signal can be sent to RRAM device 1201 via word line 1215 or bit line 1211, and bit line 1211 or word line 1215 can be grounded.

[0041] Figure 3 This is a schematic diagram illustrating a conventional TIA 300. The TIA 300 may include an operational amplifier 310 and a feedback resistor (e.g., resistor R). FB1 and R FB2 ).

[0042] like Figure 3 As shown, circuit 301 is combined with Figure 1 The equivalent circuit of a portion of the crossbar switching circuit 100. Circuit 301 may include a plurality of word lines WL0, WL1, ..., WLn connected to bit line BL. Each word line may correspond to... Figure 1 The row lines 111a-n in the text. The bit line BL can correspond to... Figure 1 The column line 113a-m. Figure 1 The crossover devices 120a-z in the diagram can be represented by resistor Rcell and capacitor Ccell. Cbl can represent the capacitance of the bit line. Ccc can represent the capacitance of adjacent word lines and / or select lines. Cload can represent the capacitance of the ADC (Anti-ADC). Figure 3 (Not shown) and / or load capacitance of other components in the cross-switch circuit of the TIA 300.

[0043] The inputs of the operational amplifier 301 can be connected to bit line BL and reference voltage VREF, respectively. One or more cross-point devices connected to bit line BL can be selected and / or enabled for programming and / or in-memory calculations. Input voltage (e.g., Figure 3 The Vwl_0, Vwl_1, ..., Vwl_n shown can be applied to the selected crosspoint device via word lines connected to the selected crosspoint device.

[0044] The TIA 300 uses the operational amplifier 310 to force the input voltage to be held at the reference voltage VREF. The output of the TIA 300 can be calculated based on the following formula: Vtia=VREF-I1 R FB (1) Where VREF is the reference voltage; I1 is the bit line current; R FB This is the resistance value of the feedback resistor located in the feedback loop of the operational amplifier 310. The operation and performance of the TIA 300 can be significantly affected by the complex capacitive loads (e.g., Ccell, Cbl, Ccc, Cload, etc.) and current variations in the TIA 300 loop. For example, the capacitive load is related to the number of activated word lines, thus affecting the TIA. This factor is related to the frequency response, and the number of activated word lines can also affect other lines in the circuit. In large-scale cross-switch circuits, such as those with 256 rows and 256 columns, the capacitive load variation can be very large, considering the large number of combinations of word lines and bit lines that may be activated at any given time. In addition, the current load can vary dynamically due to the different resistances between rows and columns in the cross-switch circuit. For example, 256 rows and columns may include 256 different resistors, each with a different programming weight. Therefore, the current in the circuit can vary significantly. The simultaneous presence of capacitive and current load variations makes ensuring the stability of the transimpedance amplifier extremely challenging.

[0045] Figure 4 This is a schematic diagram illustrating an example TIA 400 according to some embodiments of the present disclosure.

[0046] As shown in the figure, the TIA 400 may include an operational amplifier 410, a current mirror circuit 420, and one or more resistors 430 (e.g., resistor R). FB1 R FB2 (etc.). The first input 411 of the operational amplifier 410 (e.g., the inverting input) can be electrically connected to the bit line BL of the crossover switching circuit. As described above, one or more crossover devices connected to the bit line can be selected and / or enabled for programming and / or in-memory calculations. An input voltage can be applied to the selected crossover device via a word line connected to the selected crossover device.

[0047] The second input 413 of the operational amplifier 410 (e.g., the non-inverting input) can be electrically connected to a reference voltage ( Figure 4 The operational amplifier 410's output 415 can be electrically connected to the current mirror circuit 420. In some embodiments, the operational amplifier 410 can be a unity-gain amplifier. The operational amplifier's first input 411 (e.g., an inverting input) can be connected to the operational amplifier's output 415 in a unity-feedback configuration. In some embodiments, a switch 417 can be located between the operational amplifier's first input 411 and output 415. The switch 417 can selectively connect the first input 411 to the operational amplifier's output 415.

[0048] The current mirror circuit 420 may include a first transistor 421, a second transistor 423, and / or any other suitable components for mirroring and reversing current. The gate terminal of the first transistor 421 (also referred to as the "first gate terminal") may be connected to the gate terminal of the second transistor 423 (also referred to as the "second gate terminal"). The output 415 of the operational amplifier 410 may be connected to the source terminal of the first transistor 421 (also referred to as the "first source terminal"). The drain terminal of the first transistor 421 (also referred to as the "first drain terminal") may be connected to the drain terminal of the second transistor 423 (also referred to as the "second drain terminal"). The source terminal of the second transistor 423 (also referred to as the "second source terminal") may be electrically connected to one or more resistors 430. The resistors 430 may be connected to a power supply voltage Vcc.

[0049] The first current I1 flowing through the first transistor 421 can correspond to the bit line current. The first current I1 can be mirrored from the high-frequency node P1 to the right side of the current mirror circuit 420 (also referred to as the "mirror node of the current mirror circuit 420") as a second current I2. That is, the current mirror circuit 420 can reverse the direction of the first current I1. In some embodiments, the amplitude of the second current I2 is greater than the amplitude of the first current I1. In some embodiments, the amplitude of the second current I2 and the amplitude of the first current I1 can be the same or approximately the same.

[0050] The output voltage Vout of the TIA 400 can be determined according to the following formula: Vout = Vcc-I2 R FB (2) Where Vcc is the power supply voltage; I2 is the second current flowing through the second transistor 423; and RFB represents the resistance value of the feedback resistor. FB The value can be obtained by changing one or more resistors R FB1 R FB2 The image is adjusted by the mirror node connected to the current mirror circuit 420. Therefore, the output voltage generated by the TIA 400 is not affected by the capacitive load and current changes of the cross-switch circuit.

[0051] The output voltage Vout can be input to an ADC (e.g., Figure 1 The ADC 150a-n in the TIA 400 generates a digital output based on the output voltage Vout. Unlike conventional TIAs (e.g., the TIA 300) that use operational amplifiers to force the voltage to remain at a reference voltage, the TIA 400 generates an output voltage related to the supply voltage Vcc, which can be adjusted over a wider dynamic range than the reference voltage VREF used by conventional TIAs. This effectively increases the dynamic range of the ADC, thereby improving its performance and allowing for more flexible ADC designs.

[0052] The output voltage Vout corresponds to, for example Figure 4 The voltage at node P2 is shown. Since node P2 has no feedback, it is an open-loop pole. Therefore, the load of the cross-switch circuit and the load connected to the ADC of the TIA 400 have no effect on the output voltage Vout. By removing the feedback resistor and load from the operational amplifier loop to the mirror node of the current mirror circuit, the TIA design of this disclosure improves the overall circuit stability of the cross-switch circuit incorporating the TIA design.

[0053] As used herein, the terms “approximately,” “about,” and “substantially” can refer to normal tolerances in the art, such as within two standard deviations of the mean, within ±20% of the target size in some embodiments, within ±10% of the target size in some embodiments, within ±5% of the target size in some embodiments, within ±2% of the target size in some embodiments, within ±1% of the target size in some embodiments, and even within ±0.1% of the target size in some embodiments. The terms “approximately” and “about” can include the target size. Unless otherwise expressly stated or obvious from the context, all numerical values ​​described herein are modified by the term “approximately.”

[0054] In this disclosure, a range includes all numerical values ​​within that range. For example, a range of 1 to 10 may include any single number, combination of numbers, subranges, and fractions of 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0055] This disclosure has set forth numerous details in the foregoing description. However, it will be apparent that this disclosure can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagrams rather than in detail to highlight the scope of the invention.

[0056] The terms “first,” “second,” “third,” “fourth,” etc., used in this article are markings used to distinguish different components and do not necessarily have the ordinal meaning of the numerical designations used.

[0057] The terms “example” or “exemplary” as used herein mean as an example, instance, or illustration. Any aspect or design described herein as an “example” or “exemplary” is not necessarily to be construed as being more preferred or advantageous than other aspects or designs. Rather, the purpose of using the terms “example” or “exemplary” is to present concepts in a specific manner. In this application, the term “or” means to include “or”, not to exclude “or.” That is, unless otherwise specified or apparent from the context, “X includes A or B” means any natural inclusive permutation and combination. That is, if X includes A; X includes B; or X includes both A and B, then in any of the foregoing, “X includes A or B” is satisfied. Furthermore, “a” and “an” as used in this application and the appended claims should generally be understood as “one or more” unless otherwise specified or clearly indicated from the context as referring to the singular form. “An embodiment” or “one embodiment” as used in this specification means that a particular feature, structure, or characteristic associated with that embodiment is included in at least one embodiment. Therefore, the phrase “an embodiment” or “one embodiment” appearing in different places in this specification does not necessarily refer to the same embodiment.

[0058] In this disclosure, when referring to an element or layer as "located" above another element or layer, the element or layer may be located directly above the other element or layer, or there may be an intermediate element or layer. In contrast, when referring to an element or layer as "located directly" above another element or layer, there may be no intermediate element or layer.

[0059] While it will be readily apparent to those skilled in the art upon understanding the foregoing description that other changes and modifications to this disclosure are possible, it should be understood that any specific embodiments shown and described illustratively should not be considered limiting. Therefore, the details of the various embodiments are not intended to limit the scope of the claims, which themselves merely set forth the disclosed technical features.

Claims

1. An apparatus comprising: a plurality of bit lines intersecting a plurality of word lines; a plurality of cross-point devices, wherein each cross-point device is connected to at least one word line and at least one bit line; a transimpedance amplifier configured to generate an output voltage representing a sum of currents flowing through a first bit line of the plurality of bit lines, wherein the transimpedance amplifier comprises: an operational amplifier; a current mirror circuit connected to an output of the operational amplifier; one or more resistors connected to the current mirror circuit and a supply voltage.

2. The apparatus of claim 1, wherein, The operational amplifier is a unity gain amplifier.

3. The apparatus of claim 2, wherein an inverting input of the operational amplifier is connected to the first bit line and a non-inverting input of the operational amplifier is connected to a reference voltage.

4. The apparatus of claim 3, wherein, An inverting input of the operational amplifier is connected to an output of the operational amplifier.

5. The apparatus of claim 1, wherein the current mirror circuit comprises a first transistor and a second transistor, wherein a first current flowing through the first transistor corresponds to the sum of currents flowing through the first bit line, and the first current is mirrored as a second current flowing through the second transistor.

6. The apparatus of claim 5, wherein, The output voltage generated by the transimpedance amplifier can be represented as: Vout = Vcc-I R FB , where Vout is an output voltage generated by the transimpedance amplifier, Vcc is a supply voltage, I is a second current flowing through the second transistor, and R FB represents a resistance value of one or more resistors connected to the current mirror circuit and the supply voltage.

7. The apparatus of claim 5, wherein, An output of the operational amplifier is connected to a first source terminal of the first transistor and a second source terminal of the second transistor is electrically connected to at least one of the resistors.

8. The apparatus of claim 7, wherein, A first gate terminal of the first transistor is electrically connected to a second gate terminal of the second transistor.

9. The apparatus of claim 7, wherein, A first drain terminal of the first transistor is connected to a second drain terminal of the second transistor.

10. The apparatus of claim 1, wherein, The output voltage of the transimpedance amplifier is provided to an analog-to-digital converter.

11. The apparatus of claim 1, wherein, The one or more resistors are not located in a feedback loop of the operational amplifier.

12. The apparatus of claim 1, wherein, The cross-point devices comprise at least one of a memristor, a phase change memory (PCM) device, a floating gate device, a spintronic device, a ferroelectric device, or a resistive random access memory (RRAM) device.

13. The apparatus of claim 1, further comprising a switch configured to selectively connect an inverting input of the operational amplifier to an output of the operational amplifier.

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