Multi-core network adapter

Abstract

The invention relates to a multi-core network adapter. A network adapter includes a host interface, a plurality of port circuits, a plurality of network adapter cores, and a crossbar circuit. The host interface is to communicate with one or more hosts. A plurality of port circuits are used to communicate with a packet network. The network adapter core is used to serve one or more hosts in terms of transmitting and receiving packets over a packet network, while identifying the one or more hosts as respective independent network adapters. The crossbar circuit is used to connect the network adapter core to the port circuit.

Description

Multi-core network adapter Technical Field

[0001] This disclosure generally relates to network communications, and in particular to multi-core network adapters. Background Technology

[0002] Computing and communication systems such as data centers and high-performance computing (HPC) clusters typically consist of multiple hosts that exchange large amounts of data with each other. Therefore, network adapters in such systems need to operate at high bandwidths, sometimes on the order of several terabits per second (Tbps). Summary of the Invention

[0003] The network adapter includes a host interface, multiple port circuitry, multiple network adapter cores, and a crossbar switch circuit. The host interface is used to communicate with one or more hosts. The multiple port circuitry is used to communicate with a packet network. The network adapter cores serve the one or more hosts in transmitting and receiving packets through the packet network, while identifying them as respective independent network adapters to the one or more hosts. The crossbar switch circuitry is used to connect the network adapter cores to the port circuitry.

[0004] In some embodiments, the network adapter core is used to select port circuits for transmitting packets to the network by applying criteria designed to balance traffic load among the plurality of port circuits.

[0005] In some embodiments, (i) two or more network adapter cores are used to arrange packet descriptors of packets destined for a port circuit into corresponding queues associated with the port circuit; and (ii) the port circuit is used to pop the packet descriptors from the queues of the network adapter cores according to a scheduling criterion and send the corresponding packets to the packet network. Typically, the scheduling criterion aims to apply fairness among subsets of non-empty queues of the network adapter cores.

[0006] In some embodiments, the port circuitry is configured to receive packets from the packet network, determine, for each packet, a network adapter core to process the packet, and send the packet to the determined network adapter core. In one example embodiment, the port circuitry is configured to determine the network adapter core based on a destination address specified in the packet. In a disclosed embodiment, the port circuitry is configured to determine the network adapter core based on a value specified in the packet header.

[0007] In some embodiments, the host interface is configured to communicate with one or more hosts via a peripheral bus and can be configured to set up multiple links on the peripheral bus to connect each network adapter core to one or more of the hosts. In one example embodiment, the host interface is configured to assign one or more unique physical functions of the peripheral bus to each of the network adapter cores.

[0008] Typically, any one of the network adapter cores is used to transmit packets with any one of the port circuits, any one of the port circuits is used to transmit packets with any one of the network adapter cores, and the cross switch circuit is used to connect any one of the network adapter cores to any one of the port circuits.

[0009] According to the embodiments described herein, a method is also provided in a network adapter, the network adapter including a host interface, multiple port circuits, multiple network adapter cores, and crossbar switch circuitry. The method includes: communicating with one or more hosts using the host interface and communicating with a packet network using the multiple port circuits. The network adapter cores are connected to the port circuits using the crossbar switch circuitry. The multiple network adapter cores of the network adapter serve one or more hosts in transmitting and receiving packets over the packet network, while identifying one or more hosts as respective independent network adapters.

[0010] This disclosure will be more fully understood through the following detailed description of embodiments of this disclosure in conjunction with the accompanying drawings, in which: Attached Figure Description

[0011] Figure 1 schematically illustrates a block diagram of a multi-core network interface controller (NIC) according to an embodiment described herein;

[0012] Figures 2A-2E schematically illustrate block diagrams of example topologies for connecting a host to a multi-core NIC according to embodiments described herein;

[0013] Figure 3 schematically illustrates a block diagram of packet transmission in a multi-core NIC according to the embodiments described herein;

[0014] Figure 4 schematically illustrates a flowchart of a packet transmission method in a multi-core NIC according to an embodiment described herein;

[0015] Figure 5 schematically illustrates a block diagram of packet reception in a multi-core NIC according to the embodiments described herein;

[0016] Figure 6 schematically illustrates a flowchart of a packet reception method in a multi-core NIC according to embodiments described herein; and

[0017] Figure 7 schematically illustrates a block diagram of a computing system including a multi-core NIC according to an embodiment described herein. Detailed Implementation

[0018] Overview

[0019] The embodiments described herein provide a high-performance network adapter architecture that is scalable to achieve throughput of several terabits per second.

[0020] In this article, the term "network adapter" refers to any suitable device that provides network access for a host or multiple hosts. Non-limiting examples of network adapters include Ethernet network interface controllers (NICs, Network Interface Controllers), InfiniBand... TM (IB) Host Channel Adapter (HCA) and Data Processing Unit (DPU, also known as "Smart NIC"). For clarity, the embodiments described herein primarily refer to multi-core NICs comprising multiple NIC cores, but the disclosed techniques can be applied in a similar manner to any other suitable type of network adapter.

[0021] In the disclosed embodiments, the network adapter includes multiple network adapter cores. The network adapter also includes: a configurable host interface that allows the network adapter cores to serve one or more hosts; and a crossover circuit connecting the network adapter cores to multiple port circuits. Each network adapter core operates as an independent, full-featured network adapter. Specifically, each network adapter core identifies itself to the hosts as an independent network adapter.

[0022] As will be explained in detail below, the disclosed architecture provides a host with the "look and feel" of multiple independent network adapters while balancing network behavior characteristics across network adapter cores. For example, if one or more ports become congested or otherwise experience performance degradation, the disclosed architecture ensures that the performance degradation is distributed and balanced across the various network adapter cores. Therefore, hosts requiring high bandwidth can easily distribute traffic across different network adapter cores, ensuring that traffic handled by different network adapter cores has similar latency.

[0023] This paper discusses various mechanisms of the multi-core architecture disclosed herein, including host interface configuration, load balancing, and send and receive path processing.

[0024] System Description

[0025] Figure 1 schematically illustrates a block diagram of a multi-core network interface controller (NIC) 20 according to an embodiment described herein. NIC 20 serves one or more hosts 24, enabling one or more hosts 24 to transmit packets to and receive packets from network 28.

[0026] Host 24 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), or any other suitable host. Network 28 may include, for example, an Ethernet network, an IB network, an NVLINK network, or any other suitable network type.

[0027] NIC 20 includes a host interface 32, multiple port circuits 40 (for simplicity, also referred to as "ports"), multiple NIC cores 44, and crossbar switch circuits 48.

[0028] Host interface 32 is configured to connect the NIC to host 24. Host interface 32 can communicate with host 24 using any suitable interface or protocol. In some embodiments, host interface 32 communicates with host 24 via a peripheral bus (e.g., Peripheral Component High-Speed ​​Interconnect (PCIe), NVLink, Ground Reference Signaling (GRS), Low Power Interconnect (LPI), Low Latency Interconnect (LLI), or Fast Compute Link (CXL) bus). Alternatively, a suitable chip-to-chip (C2C) interface or die-to-die (D2D) interface, or any other suitable interface, can be used. In the example embodiments described herein, host interface 32 communicates with host 24 via communication link 36 (e.g., a PCIe bus including multiple PCIe Physical Functions (PFs), CXL, NVLink, GRS, LPI, LLI, or any other chip-to-chip or die-to-die communication link).

[0029] Port 40 serves as the network interface for connecting NIC 20 to network 28. NIC core 44 performs various packet processing tasks for NIC 20, such as, for example, Remote Direct Memory Access (RDMA) transmissions, Ethernet or Infiniband protocol processing, security, encryption and decryption, storage operations, packet header modification, operations related to telemetry and congestion control, scatter / aggregate operations, and various other operations.

[0030] Crossbar switch 48 connects NIC core 44 and port 40. Crossbar switch 48 enables either NIC core 44 to communicate (transmit and receive) with either port 40. Typically, the operation of crossbar switch 48 does not involve buffering or queuing of data or metadata. Buffering or queuing is typically performed in port 40 and NIC core 44. Therefore, the latency of crossbar switch 48 is minimal.

[0031] As shown in Figure 1, the configuration of NIC 20 is an example configuration chosen for clarity of concept only. In alternative embodiments, any other suitable configuration can be used. For example, in Figure 1, NIC 20 includes four NIC cores 44 (labeled "NIC Core 0" – "NIC Core 3") and eight ports 40 (labeled "Port 0" – "Port 7"). Alternatively, NIC 20 may include any other suitable number of NIC cores and ports. Similarly, NIC 24 can serve any suitable number of hosts 24.

[0032] In one example implementation, each NIC core 44 has a bandwidth of 1.6 Tbps, and the total bandwidth of NIC 20 is 6.4 Tbps. Alternatively, any other suitable bandwidth can be used.

[0033] In some embodiments, NIC 20 includes a controller (not shown) that is responsible for the overall management and configuration of NIC 20 and its components. In one example embodiment, one of the NIC cores 44 (e.g., "NIC core 0") serves as the controller. Alternatively, a separate controller device may be used.

[0034] Host interface topology

[0035] Figures 2A-2E schematically illustrate block diagrams of example topologies for connecting one or more hosts 24 to a multi-core NIC 20 (specifically, to NIC core 44 within the NIC 20) according to embodiments described herein. Typically, a given topology is configured by configuring host interfaces 32.

[0036] In the embodiments described herein, each NIC core 44 is allocated one or more corresponding communication links 36 to the host interface 32. In the non-limiting examples of Figures 2A-2E, each link 36 is a corresponding PCIe Physical Function (PF). A given PF 36 is allocated for communication between a given NIC core 44 and a given host 24. Typically, a PF 36 is not shared by multiple NIC cores 44, nor by multiple hosts 24.

[0037] In Figure 2A, four NIC cores 44 (“NIC core 0” – “NIC core 3”) communicate with a single host 24 using four corresponding PF 36. This host is in turn connected to two other hosts 24 (in this example, the GPUs are designated “GPU0” and “GPU1”). All three hosts 24 are served by the four NIC cores 44.

[0038] In Figure 2B, the first NIC core 44 (“NIC core 0”) communicates with two hosts 24 (“host / GPU 0” and “host / GPU 1”) using two corresponding PCIe PF 36. The second NIC core 44 (“NIC core 1”) communicates with two other hosts 24 (“host / GPU 2” and “host / GPU 3”) using two other corresponding PCIe PF 36.

[0039] In Figure 2C, two NIC cores 44 (“NIC core 0” and “NIC core 0”) communicate with host 24 (“host / GPU 0”) using PF 36. Two other NIC cores 44 (“NIC core 2” and “NIC core 3”) communicate with another host 24 (“host / GPU 1”) using other PF 36.

[0040] In Figure 2D, two NIC cores 44 (“NIC core 0” and “NIC core 1”) communicate with two hosts 24 (“host / GPU 0” and “host / GPU 1”), enabling the two NIC cores to serve two hosts simultaneously. A PF 36 connects “NIC core 0” to “host / GPU 0”; a second PF 36 connects “NIC core 0” to “host / GPU 1”; a third PF 36 connects “NIC core 1” to “host / GPU 0”; and a fourth PF 36 connects “NIC core 1” to “host / GPU 1”.

[0041] In Figure 2E, four NIC cores 44 (“NIC core 0” – “NIC core 3”) communicate with four corresponding hosts 24 (“host / GPU 0” – “host / GPU 3”) using four corresponding PCIe PF 36. Each NIC core 44 is assigned to serve a corresponding host 24.

[0042] The five topologies shown in Figures 2A-2E are not intended to be an exhaustive list of all possible topologies, but rather to provide examples to demonstrate the flexibility of the host interface. In alternative embodiments, host interface 32 can be configured to provide any other suitable topology. In one embodiment, the controller of NIC 20 (e.g., "NIC core 0") configures host interface 32 to provide the desired topology.

[0043] Packet transmission processing

[0044] Figure 3 schematically illustrates a block diagram of the packet transmission process in a multi-core NIC 20 according to an embodiment described herein. The figure focuses on the elements of the NIC core 44 and port 40 associated with packet transmission from NIC 20 to network 28.

[0045] In the embodiment of Figure 3, each NIC core 44 includes multiple core-side descriptor queues 52. Each core-side descriptor queue 52 corresponds to (i) a port number identifying a specific port 40, and (ii) a Virtual Channel (VL) index identifying a specific Quality of Service (QoS) level. In other words, each core-side descriptor queue 52 is assigned a queue descriptor to packets that are (i) pre-programmed for transmission via a given port 40, and (ii) associated with a VL.

[0046] Each NIC core 44 is also associated with a corresponding memory region called packet buffer 56 for storing packets awaiting transmission. Each NIC core 44 also includes an arbitrator 60, which selects the port through which to transmit each pending packet.

[0047] In this example, each port 40 includes multiple port-side descriptor queues 64. Each port-side descriptor queue 64 corresponds to a specific VL, that is, it is assigned to queue descriptors that are waiting to be transmitted via that port and have that VL (QoS) level.

[0048] The arrows in the diagram indicate that information (e.g., packet descriptors and packet data) is transmitted from NIC core 44 to port 40 via crossbar switch 48. As shown, either port 40 can receive packets to be transmitted from either NIC core 44.

[0049] Figure 4 schematically illustrates a flowchart of a packet transmission method in a multi-core NIC 20 according to an embodiment described herein. The method can be better understood in conjunction with Figures 3 and 4.

[0050] NIC core-side transmission processing

[0051] Phases 70-82 in Figure 4 are performed by each NIC core 44. To transmit packets via a particular NIC core 44, host 24 typically publishes the packet descriptor (called a Work Queue Element (WQE)) to a queue accessible to the NIC core. The packet transmission process begins with NIC core 44 selecting the WQE to serve in WQE selection phase 70. In packet readout phase 74, NIC core 44 reads the packet data from host memory and stores the packet data (typically including the packet header and packet payload) in packet buffer 56.

[0052] During port selection phase 78, arbitrator 60 of NIC core 44 selects one of the ports 40 for transmitting packets to network 28. When selecting a port, arbitrator 60 typically uses criteria designed to balance traffic load across the ports 40. In one example embodiment, arbitrator 60 checks (i) the status of the port-side descriptor queue 64 for each port 40, and (ii) the congestion control status of each port 40. Based on this information, arbitrator 60 selects the port with the lowest occupancy. Alternatively, arbitrator 60 of NIC core 44 can apply any other suitable load balancing scheme.

[0053] After selecting a port for the packet and identifying the VL assigned to the packet, the NIC core 44 publishes the packet's descriptor to the core-side descriptor queue 52 of the selected port and VL in the publishing phase 82. The method then loops back to the aforementioned phase 70 to generate the next packet.

[0054] The processes in stages 70-82 are typically executed in parallel by the individual NIC cores 44 of NIC 20. Therefore, at any given time, the core-side descriptor queues 52 of each NIC core 44 queue the descriptors of packets awaiting transmission. Packet buffers 56 hold the corresponding packets.

[0055] Port-side transmission processing

[0056] Phases 86-106 in Figure 4 are executed by each port 40. The port-side portion of the transmission process comprises two parallel sub-processes. In phases 86-94 (left), port 40 obtains descriptors of packets to be processed from each NIC core 44, while maintaining fairness in serving the NIC cores. In phases 98-106 (right), port 40 transmits the corresponding packets to network 28.

[0057] The sub-procedure for obtaining the descriptor of the packet to be processed from NIC core 44 includes the following:

[0058] During the pending queue identification phase 86, port 40 identifies a subset of core-side descriptor queues 52 that are (i) already assigned to the port and (ii) not empty. These core-side descriptor queues 52 are candidate queues from which the port will select the next packet to be transmitted.

[0059] During queue selection phase 90, the port selects one of the core-side descriptor queues 52 from the identified subset (non-empty queues associated with this port that contain descriptors to be processed). When selecting a queue, port 40 typically applies selection criteria designed to maintain fairness among the multiple NIC cores 44. In some embodiments, this selection criteria, while maintaining fairness, prioritizes queues with higher priority VLs (higher QoS levels) over queues with lower priority VLs (lower QoS levels).

[0060] During the descriptor transmission phase 94, port 40 retrieves the packet descriptor from the head of the selected core-side queue 52 and publishes the descriptor to the port-side queue 64 of the port.

[0061] The sub-process of transmitting packets to network 28 includes the following (per VL):

[0062] During descriptor popping phase 98, port 40 pops the next packet descriptor from the head of the port-side descriptor queue.

[0063] During the packet reading phase 102, port 40 reads the packet data (header and payload) of the corresponding packet from the packet buffer 56 of the NIC core 44 that generated the packet.

[0064] During transmission phase 106, port 40 sends packets to network 28.

[0065] The method flow shown in Figure 4 is an example flow chosen for clarity of concept only. In alternative embodiments, any other suitable flow may be used.

[0066] Packet reception processing

[0067] Figure 5 schematically illustrates a block diagram of packet reception in a multi-core NIC 20 according to an embodiment described herein. The figure focuses on the elements of the NIC core 44 and port 40 associated with receiving packets from network 28.

[0068] In the embodiment of Figure 5, each port 40 includes a port-side descriptor queue 114 (not to be confused with port-side descriptor queue 64 in Figure 3), and each NIC core 44 includes a core-side descriptor queue 120 (not to be confused with core-side descriptor queue 52 in Figure 3). The port-side descriptor queue 114 for a given port 40 is used to store descriptors of packets received by the port from network 28. The core-side descriptor queue 120 for a given NIC core 44 is used to store descriptors of packets received by port 40 and forwarded from the port to the NIC core.

[0069] In the disclosed embodiments, the identifier of the NIC core 44 (from multiple NIC cores 44) designated to process a given received packet is derived from the destination address specified in the packet. In some embodiments, the destination address is an Internet Protocol (IP) address specified in the received packet. In other embodiments, the destination address is a Media Access Control (MAC) address specified in the packet. Other suitable types of destination addresses may also be used. In alternative embodiments, port 40 may obtain the identifier of the NIC core 44 designated to process a given received packet from any other suitable value specified in the received packet header.

[0070] In the embodiment of Figure 5, each port 40 includes a NIC-core Look-Up Table (LUT) 118, which stores the mapping between destination addresses and NIC cores. The LUT 118 typically contains multiple entries. Each entry specifies (i) a destination address or a range of destination addresses, and (ii) an identifier for the NIC core 44 that processes received packets with this destination address (or whose destination address is within the specified range).

[0071] Port 40 uses the mapping in LUT 118 to determine which NIC core 44 is used to process a given received packet. In one embodiment, the controller of NIC 20 (e.g., "NIC core 0") uses this mapping to configure LUT 118 for port 40. The mapping between destination addresses and NIC cores is typically the same for all ports 40. In some embodiments, LUT 118 for different ports 40 may store different subsets of mappings as needed.

[0072] In addition, each port 40 is associated with a corresponding memory area called packet buffer 110, which stores packets that have been received from network 28 and are waiting to be transmitted to NIC core 44.

[0073] Figure 6 schematically illustrates a flowchart of a packet reception method in a multi-core NIC 20 according to an embodiment described herein. The method can be better understood in conjunction with Figures 5 and 6.

[0074] Port-side receive processing

[0075] Each port 40 executes stages 130-146 in Figure 6. The packet reception process begins with port 40 receiving packets from network 28 in reception stage 130. In packet storage stage 134, port 40 stores the packet data (header and payload) in the port's packet buffer 110. In descriptor storage stage 138, port 40 generates packet descriptors for the received packets and publishes the packet descriptors to the port-side descriptor queue 114.

[0076] In core selection phase 142, port 40 queries LUT 118 using the destination address of the received packet. LUT 118 returns the identifier of the NIC core 44 that should process the packet. In descriptor transfer phase 146, port 40 transfers the packet descriptor from port-side descriptor queue 114 to core-side descriptor queue 120 of the selected NIC core 44.

[0077] Core-side transmission processing

[0078] Phases 150-158 in Figure 6 are performed by each NIC core 44. The core-side portion of the receive process begins in phase 150, where NIC core 44 pops the next descriptor from the head of the core-side descriptor queue 120. In phase 154, NIC core 44 reads packet data (header and payload) from the packet buffer 110 of the port that forwarded the packet. In phase 158, NIC core 44 sends the packet to the target host.

[0079] The configurations of the multi-core NIC 20 and its various components shown in Figures 1, 2A-2E, 3, and 5 are illustrative configurations chosen for clarity of concept only. In alternative embodiments, any other suitable configuration may be used.

[0080] The method flow shown in Figure 6 is an example flow chosen for clarity of concept only. In alternative embodiments, any other suitable flow may be used.

[0081] Example System Use Cases

[0082] Figure 7 schematically illustrates a block diagram of a computing system 1000 (e.g., a data center or high-performance computing (HPC) cluster) according to embodiments described herein. According to at least one embodiment, system 1000 includes multiple subsystems, such as multiple mutually coupled processing devices, multiple network devices, and multiple networks. The computing system 1000 is designed with multiple integrated circuits (referred to as processing devices), each of which may include one or more CPUs and GPUs, thereby forming a powerful and flexible architecture.

[0083] Various processing devices are interconnected via NVLink or other high-speed interconnect technologies to enable high-speed communication between subsystems and are connected via NIC or DPU to ensure efficient data transmission across computing system 1000 and to one or more external networks 1030, 1036.

[0084] Seamless data exchange and parallel processing are enabled through NVLink coupling of the processing device, thereby improving overall computing performance. The processing device connects to multiple networks via one or more NICs or DPUs, enabling the system to handle complex multi-network tasks with high bandwidth and low latency. This configuration is ideal for demanding applications requiring powerful processing capabilities, such as artificial intelligence (AI), machine learning (ML), and data-intensive computing, while ensuring robust connectivity and scalability across diverse network environments. The integrated circuits of the Computing System 1000 may include one or more CPUs and one or more GPUs.

[0085] Figure 7 also illustrates an example architecture of a multi-GPU architecture. As shown, the computing system 1000 includes a processing device 1002 with a multi-GPU architecture. Specifically, the processing device 1002 may be a system-on-a-chip (SoC) and includes multiple subsystems, such as CPU 1006, GPU 1008, and GPU 1010. CPU 1006 can be coupled to GPU 1008 via die-to-die (D2D) or chip-to-chip (C2C) interconnects 1012 (e.g., ground reference signaling interconnect (GRS interconnect)). CPU 1006 can be coupled to GPU 1010 via D2D or C2C interconnects 1014. CPU 1006 can also be coupled to GPU 1008 and GPU 1010 via PCIe interconnects.

[0086] CPU 1006 can be coupled to one or more NICs or DPUs, which in turn are coupled to one or more networks. For example, as shown in Figure 7, CPU 1006 is coupled to a first NIC / DPU 1026, which is coupled to network 1030. CPU 1006 is also coupled to a second NIC / DPU 1028, which is coupled to network 1030. NIC / DPU 1026 and NIC / DPU 1028 can be coupled to network 1030 via, for example, Ethernet (ETH), NVLINK, or InfiniBand (IB) connections.

[0087] The computing system 1000 also includes a processing device 1004 with a multi-GPU architecture. Specifically, the processing device 1004 includes multiple subsystems, including a CPU 1016, a GPU 1018, and a GPU 1020. The CPU 1016 can be coupled to the GPU 1018 via a D2D or C2C interconnect 1022. The CPU 1016 can be coupled to the GPU 1020 via a D2D or C2C interconnect 1024. The CPU 1016 can also be coupled to the GPU 1018 and GPU 1020 via a PCIe interconnect. The CPU 1016 can be coupled to one or more NICs or DPUs, which in turn are coupled to one or more networks. For example, as shown in Figure 7, the CPU 1016 is coupled to a first NIC / DPU 1032, which in turn is coupled to a network 1036. CPU 1016 is also coupled to a second NIC / DPU 1034, which in turn is coupled to network 1036. NIC / DPU 1032 and NIC / DPU 1034 can be coupled to network 1036 via Ethernet (ETH), NVLINK, or InfiniBand (IB) connections.

[0088] In at least one embodiment, processing device 1002 and processing device 1004 can communicate with each other via NIC / DPU 1038, for example via PCIe interconnect. Processing device 1002 and processing device 1004 can also communicate with each other via high-bandwidth communication interconnect 1040, such as NVLink interconnect or other high-speed interconnect.

[0089] In various embodiments, any of the NIC / DPUs 1026, 1028, 1032, 1034, and 1038 in system 1000 may include the multi-core NIC described herein.

[0090] ***

[0091] Various parts of the multi-core NIC 20 and its components can be implemented in hardware (e.g., one or more application-specific integrated circuits (ASICs) or FPGAs), software, or a combination of hardware and software elements. In some embodiments, certain components of the multi-core NIC 20 (e.g., the controller of the NIC 20 or the NIC core 44) can be implemented partially or entirely using one or more general-purpose processors programmed in software to perform the functions described herein. This software can be downloaded to any processor in electronic form (e.g., via a network), or alternatively, attached back, or provided and / or stored on a non-transitory tangible medium (e.g., magnetic, optical, or electronic memory). For clarity, elements unnecessary for understanding the principles of the disclosed solution are omitted from the figures.

[0092] It should be understood that the above embodiments are merely illustrative references, and the present invention is not limited to the content specifically shown and described above. Rather, the scope of the present invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications that can be conceived by those skilled in the art after reading the foregoing description and which are not disclosed in the prior art. References cited in this patent application should be considered as part of this application; however, if the definition of any term in such references conflicts with the definition expressly or implicitly given in this specification, the definition in this specification shall prevail.

Claims

1. A network adapter, the network adapter comprising: A host interface used to communicate with one or more hosts; Multiple port circuits for communication with packet networks; Multiple network adapter cores are configured to serve one or more hosts in transmitting and receiving packets over the packet network, while identifying the one or more hosts as respective independent network adapters. And a cross switch circuit for connecting the network adapter core to the port circuit.

2. The network adapter according to claim 1, wherein, The network adapter core is used to select the port circuits for transmitting packets to the network by applying criteria designed to balance the traffic load among the multiple port circuits.

3. The network adapter according to claim 1, wherein: Two or more network adapter cores in the network adapter core are used to arrange packet descriptors of packets destined for port circuits into corresponding queues associated with the port circuits; Furthermore, the port circuitry is used to pop the packet descriptor from the queue of the network adapter core according to the scheduling criteria and send the corresponding packet to the packet network.

4. The network adapter according to claim 3, wherein, The scheduling criterion aims to apply fairness among a subset of the non-empty queues in the network adapter core.

5. The network adapter according to claim 1, wherein, The port circuitry is used to receive packets from the packet network, determine the network adapter core to process each packet, and send the packet to the determined network adapter core.

6. The network adapter according to claim 5, wherein, The port circuitry is used to determine the network adapter core based on the destination address specified in the packet.

7. The network adapter according to claim 5, wherein, The port circuitry is used to determine the network adapter core based on the values ​​specified in the packet header.

8. The network adapter according to claim 1, wherein, The host interface is used to communicate with one or more hosts via a peripheral bus and can be configured to set up multiple links on the peripheral bus, thereby connecting each network adapter core to one or more of the hosts.

9. The network adapter according to claim 8, wherein, The host interface is used to assign one or more unique physical functions of the peripheral bus to each of the network adapter cores.

10. The network adapter according to claim 1, wherein: Any one of the network adapter cores is used to transmit packets with any one of the port circuits in the port circuits; Any one of the port circuits is used to transmit packets with any one of the network adapter cores in the network adapter core; and the cross switch circuit is used to connect any one of the network adapter cores in the network adapter core to any one of the port circuits.

11. A method in a network adapter, the network adapter including a host interface, multiple port circuits, multiple network adapter cores, and a crossbar switch circuit, the method comprising: Use the host interface to communicate with one or more hosts; Use the aforementioned multiple port circuits to communicate with the packet network; The network adapter core is connected to the port circuit using the cross switch circuit; And the plurality of network adapter cores using the network adapter, serving the one or more hosts in transmitting and receiving packets over the packet network, while identifying the one or more hosts as respective independent network adapters.

12. The method according to claim 11, wherein, Serving the host includes: in the network adapter core, selecting port circuits for transmitting packets to the network by applying criteria designed to balance traffic load among the multiple port circuits.

13. The method of claim 11, comprising: In two or more network adapter cores, packet descriptors of packets destined for port circuits are arranged into corresponding queues associated with the port circuits. The port circuit pops the packet descriptor from the queue of the network adapter core according to the scheduling criteria, and sends the corresponding packet from the port circuit to the packet network.

14. The method according to claim 13, wherein, The scheduling criterion aims to apply fairness among a subset of the non-empty queues in the network adapter core.

15. The method of claim 11, comprising: In the port circuit, packets are received from the packet network, and for each packet, a network adapter core to process the packet is determined, and the packet is sent to the determined network adapter core.

16. The method according to claim 15, wherein, Determining the network adapter core includes: determining the network adapter core based on the destination address specified in the packet.

17. The method according to claim 15, wherein, Determining the network adapter core includes determining the network adapter core based on values ​​specified in the packet header.

18. The method according to claim 11, wherein, Performing communication with one or more hosts via a peripheral bus includes configuring the host interface to set up multiple links on the peripheral bus to connect each network adapter core to one or more of the hosts.

19. The method according to claim 18, wherein, Configuring the host interface includes assigning one or more unique physical functions of the peripheral bus to each network adapter core in the network adapter core.

20. The method of claim 11, wherein: Packets are transmitted between any network adapter core in the network adapter core and any port circuit in the port circuit; Packets are transmitted between any port circuit in the port circuit and any network adapter core in the network adapter core; And using the cross switch circuit to connect any network adapter core in the network adapter core to any port circuit in the port circuit.

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