Electromagnetic wiping device based on cooperative control of ARM and FPGA
By using ARM and FPGA to coordinate control, a high-frequency, high-precision PWM signal is generated and combined with a suction-type wiping head, solving the power supply and wiping head compatibility issues of traditional electromagnetic wiping devices. This achieves uniformity and safety of the galvanized layer and meets the real-time wiping requirements of high-speed galvanizing production lines.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-26
- Publication Date
- 2026-03-10
AI Technical Summary
Traditional electromagnetic wiping devices have shortcomings in power supply control and wiping head structure, resulting in large power output ripple, unstable wiping intensity, slow dynamic response, and inability to adapt to rapid wiping scenarios. Furthermore, the wiping head has insufficient adaptability and safety.
It adopts ARM and FPGA collaborative control to generate high-frequency and high-precision PWM drive signals, combined with multi-channel data acquisition and closed-loop adjustment, and is equipped with a suction-type wiping head and establishes a fault disconnection mechanism to achieve stability and safety in the wiping process.
It achieves uniformity and smoothness of the galvanized layer surface, adapts to the needs of high-speed galvanizing production lines, improves the sensitivity and precision of the system, ensures precise control of wiping intensity and power output, and enhances the safety and reliability of the equipment.
Smart Images
Figure CN121629302A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of galvanized layer electromagnetic wiping equipment, and particularly relates to an electromagnetic wiping device based on ARM and FPGA cooperative control. BACKGROUND
[0002] In the galvanizing process of steel wire surface, in order to eliminate the influence of impurities, oxide layers and excess zinc liquid on the surface of the galvanized layer on the quality of subsequent processing, electromagnetic wiping technology is needed to ensure the uniformity and smoothness of the coating, but this technology has double pain points of power supply control and wiping head structure in traditional application. In terms of power supply, the traditional device uses single MCU control, which is limited by the computing power and cannot generate high-frequency and high-precision PWM driving signals, resulting in large power output ripple, unstable wiping strength, slow dynamic response and low analog quantity acquisition rate, which cannot adapt to fast wiping scenes and dynamically adjust parameters according to different device types. In terms of wiping head, the traditional fixed structure wiping head can only match a single specification of steel wire, and needs to be disassembled and replaced when switching workpieces, which prolongs the downtime of the production line, and has no mechanical adjustment function. Relying on power parameter control to control the wiping effect is easy to cause poor contact or excessive extrusion, and lacks reliable fault protection mechanism, so it cannot be disconnected in time when a fault occurs, which is easy to damage the steel wire, the wiping head and even cause power overload. The ARM chip has high-performance logic scheduling, complex algorithm processing and multi-task management capability, and the FPGA has high-speed parallel processing advantage. The cooperation of the two can solve the problems of traditional power precision and response, and can break through the limitations of traditional wiping head adaptability and safety by matching the attraction type wiping head with stable attraction function and rapid fault disconnection mechanism, which is of great significance to improve the overall precision, efficiency and scene adaptability of electromagnetic wiping technology. SUMMARY
[0003] In view of the deficiencies of the prior art, the technical problem to be solved by the application is to provide an electromagnetic wiping device based on ARM and FPGA cooperative control.
[0004] To achieve the above-mentioned purpose, the application provides the following technical scheme: An electromagnetic wiping device based on ARM and FPGA cooperative control, comprising a power supply and a suction type wiping head; the power supply comprises a rectifier circuit, a Buck circuit, an inverter circuit, a multi-channel data acquisition unit, a PWM driving unit, an ARM control unit, an FPGA high-speed processing unit and a transformer; the input end of the rectifier circuit is connected with a power frequency alternating current power supply, the output end of the rectifier circuit is connected with the input end of the Buck circuit, the output end of the Buck circuit is connected with the input end of the inverter circuit, the output end of the inverter circuit is connected with the primary side of the transformer, and the secondary side of the transformer is connected with the suction type wiping head; the acquisition end of the multi-channel data acquisition unit is respectively connected with the output end of the rectifier circuit, the output end of the inverter circuit and the surface of the IGBT of the inverter circuit, the output end of the multi-channel data acquisition unit is connected with the input end of the ARM control unit, the ARM control unit and the FPGA high-speed processing unit are in bidirectional communication, the PWM output interface of the FPGA high-speed processing unit is connected with the input end of the PWM driving unit, and the output end of the PWM driving unit is connected with the control end of the inverter circuit and the control end of the Buck circuit; The multi-channel data acquisition unit comprises a voltage sampling circuit, a current sampling circuit, an IGBT temperature sampling circuit, a leakage current sampling circuit and a switching value sampling circuit; The voltage sampling circuit comprises a Hall voltage sensor, a third resistor, a sixth resistor, a third capacitor, a seventh capacitor, a first operational amplifier, a second operational amplifier and a first clamping diode; the positive and negative electrodes of the Hall voltage sensor are connected with the positive and negative electrodes of a ±15V power supply respectively, the output end of the Hall voltage sensor and one end of the third resistor are connected with the non-inverting input end of the first operational amplifier, and the other end of the third resistor is grounded; the inverting input end of the first operational amplifier is connected with the output end, the positive electrode of the first operational amplifier is connected with the positive electrode of the ±15V power supply and grounded through a fourth capacitor; the negative electrode of the first operational amplifier is connected with the negative electrode of the ±15V power supply and grounded through the third capacitor; one end of the fourth resistor is connected with the output end of the first operational amplifier, the other end of the fourth resistor and one end of the fifth resistor are connected, the other end of the fifth resistor and one end of the fifth capacitor and the non-inverting input end of the second operational amplifier are connected, and the other end of the fifth capacitor is grounded; the output end of the second operational amplifier is respectively connected with the inverting input end, one end of the sixth capacitor and the sixth resistor, the other end of the sixth capacitor is connected with the other end of the fourth resistor, the other end of the sixth resistor is connected with one end of the seventh capacitor, and the other end of the seventh capacitor is grounded; the third pin of the first clamping diode is connected with the other end of the sixth resistor, the second pin is connected with a 3.3V power supply, and the first pin is grounded; The current sampling circuit comprises a Hall current sensor, a resistor No. 7, a capacitor No. 8, an operational amplifier No. 3, an operational amplifier No. 4, a stabilizing tube, a potentiometer, a filter chip, a clamp diode No. 2 and a clamp diode No. 3; the positive and negative poles of the Hall current sensor are connected with the positive and negative poles of a ±15V power supply respectively, the output end of the Hall current sensor is connected with one end of the resistor No. 7 and the non-inverting input end of the operational amplifier No. 3 respectively, and the other end of the resistor No. 7 is grounded; the output end and the inverting input end of the operational amplifier No. 3 are connected, the negative pole of the operational amplifier No. 3 is connected with the negative pole of the ±15V power supply and grounded through the capacitor No. 8, and the positive pole of the operational amplifier No. 3 is connected with the positive pole of the ±15V power supply and grounded through the capacitor No. 9; the output end and the inverting input end of the operational amplifier No. 4 are connected, and the non-inverting input end of the operational amplifier No. 4 is grounded; the analog signal input pin of the filter chip is connected with the output end of the operational amplifier No. 3, the function configuration pin of the filter chip is connected with the midpoint of the potentiometer, one end of the potentiometer, one end of the capacitor No. 10 and one end of the resistor No. 8 are connected with the cathode of the stabilizing tube, the other end of the potentiometer, the anode of the stabilizing tube and the other end of the capacitor No. 10 are grounded, and the other end of the resistor No. 8 is connected with the +15V power supply; the filter signal output pin of the filter chip is connected with one end of the resistor No. 9, the other end of the resistor No. 9 is connected with one end of the capacitor No. 11, and the other end of the capacitor No. 11 is grounded; the No. 3 pin of the clamp diode No. 2 is connected with the other end of the resistor No. 9, the No. 2 pin is connected with a 3.3V power supply, and the No. 1 pin is grounded; the protection state output pin of the filter chip is connected with one end of the resistor No. 10 and the capacitor No. 12, the other end of the resistor No. 10 is connected with a 3.3V power supply, and the other end of the capacitor No. 12 is grounded; the No. 3 pin of the clamp diode No. 3 is connected with the protection state output pin of the filter chip, the No. 2 pin is connected with a 3.3V power supply, and the No. 1 pin is grounded. The suction type wiping head comprises a fixed arm, a movable arm and an electromagnetic suction element; one end of the fixed arm is connected with a fixed end of the electromagnetic suction element, and one end of the movable arm is connected with a movable end of the electromagnetic suction element.
[0005] Further, the IGBT temperature sampling circuit comprises the eleventh resistor, the fourteenth resistor, the thirteenth capacitor, the seventeenth capacitor, the fifth operational amplifier, the sixth operational amplifier and the fourth clamping diode; one end of the eleventh resistor and the thirteenth capacitor and the non-inverting input terminal of the fifth operational amplifier are connected with the surface of the IGBT of the inverter circuit, the other end of the eleventh resistor and the thirteenth capacitor is grounded, and the output terminal and the inverting input terminal of the fifth operational amplifier are connected; the positive electrode of the fifth operational amplifier is connected with the positive electrode of the ±15V power supply and grounded through the fourteenth capacitor, and the negative electrode of the fifth operational amplifier is grounded; one end of the twelfth resistor is connected with the output terminal of the fifth operational amplifier, the other end of the twelfth resistor is connected with one end of the thirteenth resistor, the other end of the thirteenth resistor is connected with one end of the fifteenth capacitor and the non-inverting input terminal of the sixth operational amplifier respectively, and the other end of the fifteenth capacitor is grounded; the output terminal of the sixth operational amplifier is connected with the inverting input terminal, the sixteenth capacitor and one end of the fourteenth resistor respectively, the other end of the sixteenth capacitor is connected with the other end of the twelfth resistor, the other end of the fourteenth resistor is connected with one end of the seventeenth capacitor, and the other end of the seventeenth capacitor is grounded; the third pin of the fourth clamping diode is connected with the other end of the fourteenth resistor, the second pin is connected with the 3.3V power supply, and the first pin is grounded.
[0006] Further, the switch quantity sampling circuit comprises the twentieth resistor, the twenty-third resistor, the twenty-third capacitor, the twenty-fourth capacitor, the optocoupler isolator and the light emitting diode; one end of the twentieth resistor is connected with the switch quantity signal input terminal, the other end of the twentieth resistor is connected with one end of the twenty-third capacitor and one end of the twenty-first resistor respectively, the other end of the twenty-third capacitor and the other end of the twenty-first resistor is grounded; the first pin of the optocoupler isolator is connected with the other end of the twentieth resistor, the second pin is grounded, the fourth pin is connected with the 3.3V power supply and one end of the twenty-fourth capacitor respectively, the third pin is connected with the other end of the twenty-fourth capacitor, one end of the twenty-second resistor and one end of the twenty-third resistor respectively, the other end of the twenty-second resistor is grounded, the other end of the twenty-third resistor is connected with one end of the light emitting diode, and the other end of the light emitting diode is grounded.
[0007] Further, the PWM driving unit comprises the twenty-fourth resistor, the twenty-seventh resistor, the twenty-fifth capacitor, the twenty-sixth capacitor and the high-speed photoelectric coupler; one end of the twenty-fourth resistor is connected with the PWM driving signal output end of the FPGA high-speed processing unit, and the other end is respectively connected with one end of the twenty-fifth resistor, one end of the twenty-fifth capacitor and the cathode of the light-emitting diode of the high-speed photoelectric coupler; the other end of the twenty-fifth resistor, the other end of the twenty-fifth capacitor and the anode of the light-emitting diode of the high-speed photoelectric coupler are grounded; one end of the twenty-sixth resistor is connected with the open-collector output end of the isolated side of the high-speed photoelectric coupler, and the other end is respectively connected with the twenty-seventh resistor and one end of the twenty-sixth capacitor; the other ends of the twenty-seventh resistor and the twenty-sixth capacitor are connected with each switch tube in the Buck circuit and the inverter circuit.
[0008] Compared with the prior art, the beneficial effects of the present application are as follows: 1. The FPGA generates high-frequency and high-precision PWM driving signals, and cooperates with the ARM control to collect output signals in real time to form a closed-loop regulation, so that the output voltage or current can be stabilized in the target value effective range, effectively avoiding problems such as uneven wear of the galvanized layer on the surface of the steel wire, residual impurities and the like, and ensuring the uniformity and smoothness of the galvanized layer surface.
[0009] 2. The FPGA high-speed parallel processing advantage is utilized, when the ARM quickly completes the feedback signal collection, since the ARM and the FPGA are connected through the SPI bus, the collected feedback data can be directly transmitted to the FPGA, the FPGA does not need to participate in the collection process, and after receiving the data, the high-speed parallel processing is started immediately, which greatly shortens the collection and processing time, fully adapts to the real-time wiping demand of the high-speed galvanizing production line, and significantly improves the sensitivity and precision of the system closed-loop control. Through the cooperative control of the ARM and the FPGA, the PWM carrier frequency can be dynamically adjusted according to the specific process parameters; the ARM can be equipped with a touch screen and human-computer interaction function, which can display output parameters and fault information in real time, can store historical wiping records, is convenient for process tracing and parameter optimization, and greatly improves the practicability and scene adaptability of the equipment. Through the coordination of the ARM and the FPGA, the wiping strength and power output can be accurately controlled, the shortcomings of the traditional single processor in dynamic adjustment are solved, and the response time and precision are improved.
[0010] 3. The suction type wiping head is configured with a fault disconnecting mechanism, the electromagnetic suction member is used to ensure stable adhesion with the galvanized steel wire during wiping, and linkage protection with the ARM control unit is established: when over-temperature of IGBT, excessive leakage current, over-limit of output parameters and other faults are detected, the wiping head can quickly disconnect with the steel wire to avoid equipment damage or workpiece scrap caused by fault expansion, and the safety and reliability of device operation are significantly improved. BRIEF DESCRIPTION OF DRAWINGS
[0011] Figure 1 is a schematic diagram of the overall structure of the present application; Figure 2 is a schematic diagram of the structure of the rectifier circuit, Buck circuit and inverter circuit of the present application; Figure 3 is a schematic diagram of the structure of the voltage sampling circuit of the present application; Figure 4 is a schematic diagram of the structure of the current sampling circuit of the present application; Figure 5 is a schematic diagram of the structure of the IGBT temperature sampling circuit of the present application; Figure 6 is a schematic diagram of the structure of the leakage current sampling circuit of the present application; Figure 7 is a schematic diagram of the structure of the switch quantity sampling circuit of the present application Figure 8 is a schematic diagram of the structure of the PWM drive unit of the present application Figure 9 is a schematic diagram of the structure of the electromagnetic wiping head of the present application; In the figure, 1 is a fixed arm; 2 is a movable arm; 3 is an electromagnetic attraction member. DETAILED DESCRIPTION
[0012] Specific embodiments will be described below with reference to the accompanying drawings, which are provided to illustrate the technical solutions of the present application in detail and do not limit the protection scope of the present application.
[0013] The present application provides an electromagnetic wiping device based on ARM and FPGA cooperative control (see Figures 1-9 ), comprising a power supply and an electromagnetic wiping head; the power supply comprises a rectifier circuit, a Buck circuit, an inverter circuit, a multi-channel data acquisition unit, a PWM drive unit, an ARM control unit, an FPGA high-speed processing unit and a transformer; The input end of the rectifier circuit is connected with a power frequency alternating current power supply, the output end of the rectifier circuit is connected with the input end of the Buck circuit, the output end of the Buck circuit is connected with the input end of the inverter circuit, the output end of the inverter circuit is connected with the primary side of the transformer, and the secondary side of the transformer is connected with the suction type wiping head; the collection end of the multi-channel data collection unit is respectively connected with the output end of the rectifier circuit, the output end of the inverter circuit and the surface of the IGBT of the inverter circuit, the output end of the multi-channel data collection unit is connected with the input end of the ARM control unit, the multi-channel data collection unit collects the DC bus voltage, the DC bus current, the inverter circuit output voltage, the inverter circuit output current, the inverter circuit IGBT temperature and the power supply leakage current and transmits them to the ARM control unit; the ARM control unit and the FPGA high-speed processing unit communicate bidirectionally through the high-speed synchronous bus of the SPI interface; the PWM output interface of the FPGA high-speed processing unit is connected with the input end of the PWM driving unit, and the output end of the PWM driving unit is connected with the control end of the inverter circuit and the control end of the Buck circuit.
[0014] As Figure 1As shown, the rectifier circuit converts the power frequency alternating current into direct current, the Buck circuit filters the direct current output by the rectifier circuit to remove ripple and provides smooth direct current for the inverter circuit; the inverter circuit, under the control of the PWM drive unit, inverts the direct current into alternating current, which is subjected to voltage level conversion and electrical isolation by the transformer to adapt to the load demand and power the suction type wiping head. The voltage sampling circuit and the current sampling circuit of the multi-channel data acquisition unit are connected with the rectifier circuit, collect the direct current bus voltage and current and input them into the ARM control unit after A / D conversion, and compare them with the set value. If it is greater than the set value, a fault alarm is given to prevent input overcurrent or overvoltage; the voltage sampling circuit and the current sampling circuit of the multi-channel data acquisition unit are connected with the output side of the inverter circuit, collect the output voltage and current of the inverter circuit and transmit them to the ARM control unit for closed-loop control. The ARM control unit and the FPGA high-speed processing unit cooperate, the ARM control unit receives the data collected by the multi-channel data acquisition unit, performs data analysis and processing, generates PWM configuration instructions (including PWM duty cycle adjustment value, PWM carrier frequency set according to process requirements, modulation depth parameter matched with wiping intensity level, etc.) and transmits them to the FPGA high-speed processing unit, the FPGA high-speed processing unit generates a PWM drive signal, the PWM drive unit performs optical coupling isolation and power amplification on the PWM drive signal, part of which is used to drive the MOS tube on-off of the Buck circuit to realize the adjustment of the direct current output voltage, by adjusting the direct current output voltage, the size of the inverter circuit output voltage can be changed, and the size of the inverter circuit output current can be changed, the size of the eddy current on the galvanized layer surface also changes with the change of the inverter circuit output current, thereby realizing the change of the electromagnetic wiping force, and completing the control of the wiping thickness of the galvanized layer. The other part of the PWM drive signal drives the IGBT switch tube of the inverter circuit to act, and the three-phase alternating current generated by the inverter circuit after the transformer powers the suction type wiping head, that is, drives the suction type wiping head to act. The core functions of the transformer include two aspects: one is voltage level conversion, which converts the alternating current output by the inverter circuit into an appropriate voltage according to the load demand; the other is electrical isolation, which realizes the electrical isolation between the main circuit and the load, avoids the influence of load side fault on the main circuit, and at the same time guarantees the safety of equipment and operating personnel.
[0015] As Figure 2As shown, the rectifier circuit adopts a three-phase bridge rectifier circuit, comprising a first diode D1 to a sixth diode D6 and a first resistor R1; wherein the first diode D1 and the fourth diode D4 constitute a first bridge arm, the second diode D2 and the fifth diode D5 constitute a second bridge arm, and the third diode D3 and the sixth diode D6 constitute a third bridge arm; a first resistor R1 is connected in parallel with each diode, and a first resistor R1 is connected in parallel with the output side of the rectifier bridge; the resistor connected in parallel with the diode plays the role of voltage equalization, inhibits reverse recovery current and consumes reverse peak voltage, and can provide protection for the diode; the resistor connected in parallel with the rectifier bridge can consume the reactive power at the output end of the rectifier bridge, which helps to stabilize the output voltage.
[0016] The Buck circuit comprises a MOS transistor, a seventh diode D7, an inductor L1, a first capacitor C1 and a second resistor R2; wherein the drain (D) of the MOS transistor is connected with the output end of the rectifier circuit, the gate (G) of the MOS transistor is connected with the output end of the PWM driving unit, the source (S) of the MOS transistor is connected with the negative electrode of the seventh diode D7 and one end of the inductor L1 respectively, the anode of the seventh diode D7 is connected with one end of the first resistor R1 at the output side of the rectifier circuit, a resistor is connected in parallel with the seventh diode D7, the other end of the inductor L1 is connected with one end of the first capacitor C1, and the other end of the first capacitor C1 is connected with the anode of the seventh diode D7; one end of the second resistor R2 is connected with the other end of the inductor L1, and the other end of the second resistor R2 is connected with the anode of the seventh diode D7; the inductor L1 and the first capacitor C1 constitute an LC low-pass filter circuit, when the MOS transistor controls the on-off, the inductor L1 smoothes the current fluctuation by releasing energy, and the first capacitor C1 further filters the voltage ripple, so that the output DC is more stable, this process directly realizes the filtering of high-frequency noise and pulsation generated by switching action, and ensures that the ripple of the DC output to the inverter circuit is small.
[0017] The inverter circuit adopts a three-phase full-bridge inverter circuit, comprising a first IGBT switch Q1 to a sixth IGBT switch Q6 and a second capacitor C2; wherein the second capacitor C2 is connected in parallel at the input side of the inverter circuit, the first IGBT switch Q1 and the fourth IGBT switch Q4 constitute a first bridge arm, the third IGBT switch Q3 and the sixth IGBT switch Q6 constitute a bridge arm, the fifth IGBT switch Q5 and the second IGBT switch Q2 constitute a bridge arm, and the three bridge arms are connected with the primary side of the transformer respectively; a diode is connected in parallel with each IGBT switch. The inverter circuit adopts pulse width modulation technology, after the low-ripple smooth DC is input into the inverter circuit, the conduction and turn-off time of the IGBT switch is controlled through the PWM driving signal, so that the output pulse width changes according to the sine law, and a relatively smooth sine wave AC can be obtained.
[0018] The multi-channel data acquisition unit comprises a voltage sampling circuit, a current sampling circuit, an IGBT temperature sampling circuit, a leakage current sampling circuit and a switching value sampling circuit; the voltage sampling circuit acquires DC bus voltage and inverter circuit output voltage, the current sampling circuit acquires DC bus current and inverter circuit output current, the IGBT temperature sampling circuit acquires inverter circuit IGBT temperature, the leakage current sampling circuit acquires power supply leakage current, and the switching value sampling circuit acquires switching value control signals given by the ARM control unit.
[0019] As shown in Figure 3 , the voltage sampling circuit comprises a Hall voltage sensor (model: CHV-25P), a third resistor R3 to a sixth resistor R6, a third capacitor C3 to a seventh capacitor C7, a first operational amplifier U1A, a second operational amplifier U1B and a first clamping diode D8; wherein the positive and negative poles of the Hall voltage sensor are connected with the positive and negative poles of a ±15V power supply respectively, the output end of the Hall voltage sensor and one end of the third resistor R3 are connected with the non-inverting input end of the first operational amplifier U1A, and the other end of the third resistor R3 is grounded; the inverting input end of the first operational amplifier U1A is connected with the output end, the positive pole of the first operational amplifier U1A is connected with the positive pole of the ±15V power supply, and is grounded through a fourth capacitor C4 at the same time; the negative pole of the first operational amplifier U1A is connected with the negative pole of the ±15V power supply, and is grounded through a third capacitor C3 at the same time, and the third capacitor C3 and the fourth capacitor C4 realize filtering of the operational amplifier power supply; one end of a fourth resistor R4 is connected with the output end of the first operational amplifier U1A, the other end of the fourth resistor R4 is connected with one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected with one end of a fifth capacitor C5 and the non-inverting input end of the second operational amplifier U1B, and the other end of the fifth capacitor C5 is grounded; the output end of the second operational amplifier U1B is connected with the inverting input end, a sixth capacitor C6 and one end of a sixth resistor R6 respectively, the other end of the sixth capacitor C6 is connected with the other end of the fourth resistor R4, the other end of the sixth resistor R6 is connected with one end of a seventh capacitor C7, the other end of the seventh capacitor C7 is grounded, and the sixth resistor R6 and the seventh capacitor C7 constitute an RC filter circuit to filter the processed signal; the third pin of the first clamping diode D8 is connected with the other end of the sixth resistor R6, the second pin is connected with a 3.3V power supply, and the first pin is grounded. The first clamping diode D8 completes clamping protection of the output signal, so that the output is stable and the voltage signal is adapted to the subsequent circuit, and the output voltage signal is finally input to the ARM control unit.
[0020] As shown in Figure 4As shown, the current sampling circuit includes a Hall current sensor (model: CHB-25NP / SP8), a seventh resistor R7~a tenth resistor R10, an eighth capacitor C8~a twelfth capacitor C12, a third operational amplifier U2A, a fourth operational amplifier U2B, a voltage stabilizing tube DZ1, a potentiometer RP1, a filter chip M1, a second clamping diode D9 and a third clamping diode D10; wherein the positive and negative electrodes of the Hall current sensor are connected with the positive and negative electrodes of a ±15V power supply respectively, the output end of the Hall current sensor is connected with one end of the seventh resistor R7 and the non-inverting input end of the third operational amplifier U2A respectively, and the other end of the seventh resistor R7 is grounded; the output end and the inverting input end of the third operational amplifier U2A are connected, the negative electrode of the third operational amplifier U2A is connected with the negative electrode of the ±15V power supply, and is grounded through the eighth capacitor C8 at the same time; the positive electrode of the third operational amplifier U2A is connected with the positive electrode of the ±15V power supply, and is grounded through the ninth capacitor C9 at the same time; the output end and the inverting input end of the fourth operational amplifier U2B are connected, and the non-inverting input end of the fourth operational amplifier U2B is grounded; the analog signal input pin (namely AI pin) of the filter chip M1 is connected with the output end of the third operational amplifier U2A, the function configuration pin (namely SET pin) of the filter chip M1 is connected with the midpoint of the potentiometer RP1, one end of the potentiometer RP1 is connected with the cathode of the voltage stabilizing tube DZ1, one end of the tenth capacitor C10 and one end of the eighth resistor R8, the other end of the potentiometer RP1, the anode of the voltage stabilizing tube DZ1 and the other end of the tenth capacitor C10 are grounded, and the other end of the eighth resistor R8 is connected with the +15V power supply; the filter signal output pin (namely AO pin) of the filter chip M1 is connected with one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected with one end of the eleventh capacitor C11, the other end of the eleventh capacitor C11 is grounded, and the ninth resistor R9 and the eleventh capacitor C11 constitute an RC filter circuit to filter the processed signal; the three pin of the second clamping diode D9 is connected with the other end of the ninth resistor R9, the two pin is connected with a 3.3V power supply, and the one pin is grounded; the second clamping diode D9 completes the clamping protection of the output signal, so that the output is stable and the voltage signal is adapted to the subsequent circuit, and finally input to the ARM control unit. The protection state output pin (namely PROT_OUT pin) of the filter chip M1 is connected with one end of the tenth resistor R10 and the twelfth capacitor C12, the other end of the tenth resistor R10 is connected with a 3.3V power supply, and the other end of the twelfth capacitor C12 is grounded. The three pin of the third clamping diode D10 is connected with the protection state output pin (namely PROT_OUT pin) of the filter chip M1, the two pin is connected with a 3.3V power supply, and the one pin is grounded. The third clamping diode D10 completes the clamping protection of the output signal, so that the output is stable and the IDC_P signal is adapted to the subsequent circuit, and finally input to the FPGA high-speed processing unit.
[0021] As Figure 5As shown, the IGBT temperature sampling circuit includes the eleventh resistor R11 to the fourteenth resistor R14, the thirteenth capacitor C13 to the seventeenth capacitor C17, the fifth operational amplifier U3A, the sixth operational amplifier U3B, and the fourth clamping diode D11; one end of the eleventh resistor R11 and the thirteenth capacitor C13 and the non-inverting input terminal of the fifth operational amplifier U3A are connected to the surface of the IGBT of the inverter circuit, the other end of the eleventh resistor R11 and the thirteenth capacitor C13 are grounded, and the output terminal and the inverting input terminal of the fifth operational amplifier U3A are connected; the positive electrode of the fifth operational amplifier U3A is connected to the positive electrode of the ±15V power supply and grounded through the fourteenth capacitor C14, and the negative electrode of the fifth operational amplifier U3A is grounded; one end of the twelfth resistor R12 is connected to the output terminal of the fifth operational amplifier U3A, the other end of the twelfth resistor R12 is connected to one end of the thirteenth resistor R13, the other end of the thirteenth resistor R13 is respectively connected to one end of the fifteenth capacitor C15 and the non-inverting input terminal of the sixth operational amplifier U3B, and the other end of the fifteenth capacitor C15 is grounded; the output terminal of the sixth operational amplifier U3B is respectively connected to the inverting input terminal, the sixteenth capacitor C16, and one end of the fourteenth resistor R14, the other end of the sixteenth capacitor C16 is connected to the other end of the twelfth resistor R12, the other end of the fourteenth resistor R14 is connected to one end of the seventeenth capacitor C17, the other end of the seventeenth capacitor C17 is grounded, and the fourteenth resistor R14 and the seventeenth capacitor C17 constitute an RC filter circuit to filter the processed signal. The third pin of the fourth clamping diode D11 is connected to the other end of the fourteenth resistor R14, the second pin is connected to the 3.3V power supply, and the first pin is grounded. The fourth clamping diode D11 completes the clamping protection of the output signal, makes the output stable, and adapts the IGBT_T signal of the subsequent circuit, and finally inputs to the ARM control unit.
[0022] As shown in FIG. 6, the DC current sampling circuit includes the first resistor R1 to the eighth resistor R8, the first capacitor C1 to the eighth capacitor C8, the first operational amplifier U1A, the second operational amplifier U1B, and the third clamping diode D3. Figure 6 As shown in FIG. 7, the leakage current sampling circuit has a structure similar to the DC current sampling circuit, which will not be repeated here; the LeakCurr signal finally output by the leakage current sampling circuit is input to the ARM control unit, and the LeakCurr_P signal is input to the FPGA high-speed processing unit.
[0023] As shown in FIG. 8, the gate voltage sampling circuit includes the ninth resistor R9 to the twelfth resistor R12, the ninth capacitor C9 to the twelfth capacitor C12, the third operational amplifier U3A, the fourth operational amplifier U3B, and the fourth clamping diode D4. Figure 7As shown, the switch quantity sampling circuit includes twenty resistors R20~R23, twenty-third capacitor C23, twenty-fourth capacitor C24, optical coupling isolator J1 and light emitting diode LED; wherein one end of the twenty resistor R20 is connected with the switch quantity signal input end, the other end of the twenty resistor R20 is connected with one end of the twenty-third capacitor C23 and one end of the twenty-first resistor R21 respectively, the other end of the twenty-third capacitor C23 and the other end of the twenty-first resistor R21 are grounded, the twenty-first resistor R21 and the twenty-third capacitor C23 constitute an RC filter circuit; one pin of the optical coupling isolator J1 is connected with the other end of the twenty resistor R20, the second pin is grounded, the fourth pin is connected with 3.3V power supply and one end of the twenty-fourth capacitor C24 respectively, the third pin is connected with the other end of the twenty-fourth capacitor C24, one end of the twenty-second resistor R22 and one end of the twenty-third resistor R23 respectively, the other end of the twenty-second resistor R22 is grounded, the other end of the twenty-third resistor R23 is connected with one end of the light emitting diode LED, the other end of the light emitting diode LED is grounded; the twenty-third resistor R23 and the light emitting diode LED constitute a state indicating circuit, and the collected switch quantity signal is output to the ARM control unit.
[0024] As shown in the figure, Figure 8 The PWM driving unit includes twenty-fourth resistor R24~twenty-seventh resistor R27, twenty-fifth capacitor C25, twenty-sixth capacitor C26 and high-speed photoelectric coupler (model: HCPL-3120-500E); wherein one end of the twenty-fourth resistor R24 is connected with the PWM driving signal output end of the FPGA high-speed processing unit, the other end is connected with one end of the twenty-fifth resistor R25, one end of the twenty-fifth capacitor C25 and the cathode of the light emitting diode of the high-speed photoelectric coupler respectively, the other end of the twenty-fifth resistor R25, the other end of the twenty-fifth capacitor C25 and the anode of the light emitting diode of the high-speed photoelectric coupler are grounded; one end of the twenty-sixth resistor R26 is connected with the open-collector output end of the isolated side of the high-speed photoelectric coupler, the other end is connected with the twenty-seventh resistor R27 and one end of the twenty-sixth capacitor C26 respectively, the other end of the twenty-seventh resistor R27 and the twenty-sixth capacitor C26 is connected with each switch tube in the Buck circuit and the inverter circuit. The high-speed photoelectric coupler is used to electrically isolate the PWM driving signal of the control side from the power side, prevent the interference of the power circuit from affecting the control circuit, and amplify the weak PWM driving signal to control the on-off of the MOS tube in the Buck circuit and the IGBT switch tube in the inverter circuit.
[0025] The ARM control unit is built based on a Cortex-A series processor, integrates 1MB or more flash memory and 512KB or more SRAM, has multi-interface and multi-task processing capability, supports input of configuration instructions through a serial communication interface or a local man-machine interaction unit, can set target output voltage, target output current, PWM carrier frequency, wiping intensity level and various protection thresholds, and stores the configuration parameters in a non-volatile storage area, so that the parameters are not lost after power failure; meanwhile, the ARM control unit receives DC bus voltage, inverter output voltage, inverter output current, IGBT temperature and leakage current analog signals fed back by the multi-channel data sampling unit, first completes analog-digital conversion through the built-in 12-bit ADC, then performs operation processing on the converted digital signals by using a PI algorithm, calculates the trigger angle of the switching tube on-off in combination with the wiping intensity level and the load characteristics, and has man-machine interaction control function, and the GPIO interface is connected with the touch screen, so that the current running parameters and fault information can be displayed in real time.
[0026] The FPGA high-speed processing unit adopts a high-performance FPGA chip, has built-in special logic modules and high-speed signal processing units, integrates 3 independent PWM generation logic units and three-phase phase-locked loop units, can adjust the PWM duty cycle and carrier frequency in real time, so that the inverter output voltage / current ripple is less than or equal to 1%, and dynamically adjusts the PWM waveform modulation depth according to the wiping intensity level, so as to realize accurate matching of the wiping intensity and the PWM output power.
[0027] As shown in Figure 9 The suction type wiping head includes a fixed arm 1, a movable arm 2 and an electromagnetic suction member 3; one end of the fixed arm 1 is connected with a fixed end of the electromagnetic suction member 3, one end of the movable arm 2 is connected with a movable end of the electromagnetic suction member 3, the fixed arm 1 and the movable arm 3 are stably attached to the surface of the galvanized steel wire by the suction force generated by the electromagnetic suction member 3, and the contact reliability in the wiping process is ensured. The suction type wiping head and the ARM control unit establish a real-time linkage mechanism, when the ARM control unit receives abnormal signals such as IGBT over-temperature, leakage current exceeding the standard, output voltage / current exceeding the limit and the like fed back by the multi-channel data acquisition unit, or receives a fault checking instruction sent by the FPGA high-speed processing unit, the electromagnetic suction member 3 will be immediately powered off, the electromagnetic suction force disappears instantaneously, the movable arm 2 and the fixed arm 1 quickly separate, the suction type wiping head and the galvanized steel wire quickly separate, at the same time, the ARM control unit controls the FPGA high-speed processing unit to suspend the output of the PWM driving signal, cuts off the inverter circuit driving, and double protection avoids expansion of the fault, and ensures the safety of the equipment and the galvanized steel wire.
[0028] The unmentioned parts of the present application are applicable to the prior art.
Claims
1. An electromagnetic wiping device based on ARM and FPGA cooperative control, comprising a power supply and a suction type wiping head; characterized in that, The power supply comprises a rectifier circuit, a Buck circuit, an inverter circuit, a multi-channel data acquisition unit, a PWM driving unit, an ARM control unit, an FPGA high-speed processing unit and a transformer; An input end of the rectifier circuit is connected with a power frequency alternating current power supply, an output end of the rectifier circuit is connected with an input end of the Buck circuit, an output end of the Buck circuit is connected with an input end of the inverter circuit, an output end of the inverter circuit is connected with a primary side of the transformer, a secondary side of the transformer is connected with the suction type wiping head; the acquisition end of the multi-channel data acquisition unit is respectively connected with the output end of the rectifier circuit, the output end of the inverter circuit and the surface of the IGBT of the inverter circuit, the output end of the multi-channel data acquisition unit is connected with the input end of the ARM control unit, the ARM control unit and the FPGA high-speed processing unit are in bidirectional communication, the PWM output interface of the FPGA high-speed processing unit is connected with the input end of the PWM driving unit, and the output end of the PWM driving unit is connected with the control end of the inverter circuit and the control end of the Buck circuit; The multi-channel data acquisition unit comprises a voltage sampling circuit, a current sampling circuit, an IGBT temperature sampling circuit, a leakage current sampling circuit and a switching value sampling circuit; The voltage sampling circuit comprises a Hall voltage sensor, a third resistor, a sixth resistor, a third capacitor, a seventh capacitor, a first operational amplifier, a second operational amplifier and a first clamping diode; the positive and negative poles of the Hall voltage sensor are connected with the positive and negative poles of a ±15V power supply respectively, the output end of the Hall voltage sensor and one end of the third resistor are connected with the non-inverting input end of the first operational amplifier, and the other end of the third resistor is grounded; the inverting input end of the first operational amplifier is connected with the output end, the positive pole of the first operational amplifier is connected with the positive pole of the ±15V power supply and grounded through the fourth capacitor; the negative pole of the first operational amplifier is connected with the negative pole of the ±15V power supply and grounded through the third capacitor; one end of the fourth resistor is connected with the output end of the first operational amplifier, the other end of the fourth resistor and one end of the fifth resistor are connected, the other end of the fifth resistor and one end of the fifth capacitor and the non-inverting input end of the second operational amplifier are connected, and the other end of the fifth capacitor is grounded; the output end of the second operational amplifier is respectively connected with the inverting input end, one end of the sixth capacitor and the sixth resistor, the other end of the sixth capacitor is connected with the other end of the fourth resistor, the other end of the sixth resistor is connected with one end of the seventh capacitor, and the other end of the seventh capacitor is grounded; the third pin of the first clamping diode is connected with the other end of the sixth resistor, the second pin is connected with a 3.3V power supply, and the first pin is grounded. The current sampling circuit comprises a Hall current sensor, a resistor No. 7, a capacitor No. 8, an operational amplifier No. 3, an operational amplifier No. 4, a stabilizing tube, a potentiometer, a filter chip, a clamp diode No. 2 and a clamp diode No. 3; the positive and negative poles of the Hall current sensor are connected with the positive and negative poles of a ±15V power supply respectively, the output end of the Hall current sensor is connected with one end of the resistor No. 7 and the non-inverting input end of the operational amplifier No. 3 respectively, and the other end of the resistor No. 7 is grounded; the output end and the inverting input end of the operational amplifier No. 3 are connected, the negative pole of the operational amplifier No. 3 is connected with the negative pole of the ±15V power supply and grounded through the capacitor No. 8, and the positive pole of the operational amplifier No. 3 is connected with the positive pole of the ±15V power supply and grounded through the capacitor No. 9; the output end and the inverting input end of the operational amplifier No. 4 are connected, and the non-inverting input end of the operational amplifier No. 4 is grounded; the analog signal input pin of the filter chip is connected with the output end of the operational amplifier No. 3, the function configuration pin of the filter chip is connected with the midpoint of the potentiometer, one end of the potentiometer, one end of the capacitor No. 10 and one end of the resistor No. 8 are connected with the cathode of the stabilizing tube, the other end of the potentiometer, the anode of the stabilizing tube and the other end of the capacitor No. 10 are grounded, and the other end of the resistor No. 8 is connected with the +15V power supply; the filter signal output pin of the filter chip is connected with one end of the resistor No. 9, the other end of the resistor No. 9 is connected with one end of the capacitor No. 11, and the other end of the capacitor No. 11 is grounded; the No. 3 pin of the clamp diode No. 2 is connected with the other end of the resistor No. 9, the No. 2 pin is connected with a 3.3V power supply, and the No. 1 pin is grounded; the protection state output pin of the filter chip is connected with one end of the resistor No. 10 and the capacitor No. 12, the other end of the resistor No. 10 is connected with a 3.3V power supply, and the other end of the capacitor No. 12 is grounded; the No. 3 pin of the clamp diode No. 3 is connected with the protection state output pin of the filter chip, the No. 2 pin is connected with a 3.3V power supply, and the No. 1 pin is grounded. The suction type wiping head comprises a fixed arm, a movable arm and an electromagnetic suction member; one end of the fixed arm is connected with a fixed end of the electromagnetic suction member, and one end of the movable arm is connected with a movable end of the electromagnetic suction member.
2. The electromagnetic wiping device based on ARM and FPGA cooperative control according to claim 1, characterized in that, The IGBT temperature sampling circuit comprises the No. 11 resistor, the No. 14 resistor, the No. 13 capacitor, the No. 17 capacitor, the No. 5 operational amplifier, the No. 6 operational amplifier and the No. 4 clamping diode; one end of the No. 11 resistor and the No. 13 capacitor and the non-inverting input terminal of the No. 5 operational amplifier are connected with the surface of the IGBT of the inverter circuit, the other end of the No. 11 resistor and the No. 13 capacitor is grounded, and the output terminal and the inverting input terminal of the No. 5 operational amplifier are connected; the positive electrode of the No. 5 operational amplifier is connected with the positive electrode of the ± 15V power supply and grounded through the No. 14 capacitor, and the negative electrode of the No. 5 operational amplifier is grounded; one end of the No. 12 resistor is connected with the output terminal of the No. 5 operational amplifier, the other end of the No. 12 resistor is connected with one end of the No. 13 resistor, the other end of the No. 13 resistor is connected with one end of the No. 15 capacitor and the non-inverting input terminal of the No. 6 operational amplifier respectively, and the other end of the No. 15 capacitor is grounded; the output terminal of the No. 6 operational amplifier is connected with the inverting input terminal, the No. 16 capacitor and one end of the No. 14 resistor respectively, the other end of the No. 16 capacitor is connected with the other end of the No. 12 resistor, the other end of the No. 14 resistor is connected with one end of the No. 17 capacitor, and the other end of the No. 17 capacitor is grounded; the No. 3 pin of the No. 4 clamping diode is connected with the other end of the No. 14 resistor, the No. 2 pin is connected with the 3.3V power supply, and the No. 1 pin is grounded.
3. The electromagnetic wiping device based on ARM and FPGA cooperative control according to claim 1, characterized in that, The switch quantity sampling circuit comprises the No. 20 resistor to the No. 23 resistor, the No. 23 capacitor, the No. 24 capacitor, the optical coupling isolator and the light emitting diode; one end of the No. 20 resistor is connected with the switch quantity signal input terminal, the other end of the No. 20 resistor is connected with one end of the No. 23 capacitor and one end of the No. 21 resistor respectively, the other end of the No. 23 capacitor and the other end of the No. 21 resistor are grounded; the No. 1 pin of the optical coupling isolator is connected with the other end of the No. 20 resistor, the No. 2 pin is grounded, the No. 4 pin is connected with the 3.3V power supply and one end of the No. 24 capacitor respectively, the No. 3 pin is connected with the other end of the No. 24 capacitor, one end of the No. 22 resistor and one end of the No. 23 resistor respectively, the other end of the No. 22 resistor is grounded, the other end of the No. 23 resistor is connected with one end of the light emitting diode, and the other end of the light emitting diode is grounded.
4. The electromagnetic wiping device based on ARM and FPGA cooperative control according to any one of claims 1-3, characterized in that, The PWM driving unit comprises the No. 24 resistor to the No. 27 resistor, the No. 25 capacitor, the No. 26 capacitor and the high-speed photoelectric coupler; one end of the No. 24 resistor is connected with the PWM driving signal output terminal of the FPGA high-speed processing unit, the other end is connected with one end of the No. 25 resistor, one end of the No. 25 capacitor and the light emitting diode cathode of the high-speed photoelectric coupler respectively, the other end of the No. 25 resistor, the other end of the No. 25 capacitor and the light emitting diode anode of the high-speed photoelectric coupler are grounded; one end of the No. 26 resistor is connected with the open-collector output terminal of the isolated side of the high-speed photoelectric coupler, the other end is connected with the No. 27 resistor and one end of the No. 26 capacitor respectively, the other end of the No. 27 resistor and the No. 26 capacitor is connected with each switch tube in the Buck circuit and the inverter circuit.