A signal detection circuit

Abstract

The application discloses a signal detection circuit. The signal detection circuit comprises a power supply voltage stabilizing circuit, a Zener reference voltage source circuit, an in-phase signal detection circuit, an anti-phase signal detection circuit, a window synthesis circuit, a frequency divider circuit and a latch output circuit. The in-phase signal detection circuit and the anti-phase signal detection circuit are used to freely adjust the window voltage. The window synthesis circuit is matched with the in-phase signal detection circuit and the anti-phase signal detection circuit to calculate N (2≤N≤100) high-level pulses in a signal period and latch the high-level, so that the detection of the sinusoidal wave bidirectional signal and the pulsating direct current signal is realized, and the interference of external noise is effectively avoided. Therefore, the signal detection circuit is more suitable for the accurate and effective detection requirement of the sinusoidal wave signal or the pulsating direct current signal.

Description

Technical Field

[0001] This invention relates to signal detection circuits, and more particularly to a signal detection circuit. Background Technology

[0002] In engineering practice, technicians often need to perform high-precision detection and digital processing of signals at the millivolt or even microvolt level. Low-frequency small-signal detection processors are indispensable in both consumer and industrial signal systems, and are widely used in industrial control and measurement systems. Current low-frequency small-signal detection circuits typically employ high-precision operational amplifiers (often used in conjunction with high-precision reference sources), resulting in high manufacturing costs and increasing the actual cost of use in consumer applications. Furthermore, high-precision operational amplifiers and reference sources often overemphasize the detection accuracy of small signals, constantly pursuing higher signal detection sensitivity while neglecting the interference from high-frequency noise signals. For example, in industrial control systems, engineers continuously strive for high accuracy in detecting residual leakage signals from AC power supplies, but cannot perfectly shield against high-frequency noise interference such as walkie-talkie electromagnetic waves. Additionally, different application areas have significant differences in the amplitude and frequency of low-frequency small-signal detection. For engineering designers, this necessitates selecting different high-precision operational amplifiers based on the required amplitude and frequency, increasing design costs. Summary of the Invention

[0003] To address the aforementioned problems, this application provides a signal detection circuit.

[0004] This invention provides the following technical solution: a signal detection circuit, comprising a power supply regulator circuit, a Zener reference voltage source circuit, an in-phase signal detection circuit, an out-of-phase signal detection circuit, a window synthesis circuit, a frequency divider circuit, and a latch output circuit. The power supply regulator circuit supplies power to the Zener reference voltage source circuit, the in-phase signal detection circuit, the out-of-phase signal detection circuit, and the window synthesis circuit. The output of the Zener reference voltage source circuit serves as the reference for the in-phase signal detection circuit and the out-of-phase signal detection circuit. The drive outputs of the in-phase signal detection circuit and the out-of-phase signal detection circuit serve as the inputs of the window synthesis circuit. The output of the window synthesis circuit serves as the input of the frequency divider circuit. The output of the frequency divider circuit serves as the input of the latch output circuit. The output of the latch output circuit serves as the drive output of the signal detection circuit.

[0005] Furthermore, the Zener reference voltage source circuit includes a first resistor with one end connected to the power supply regulator circuit, the other end of the first resistor connected to the base of the first transistor and the cathode of the controllable precision voltage regulator, the collector of the first transistor connected to the power supply regulator circuit, the anode of the controllable precision voltage regulator connected to one end of the second resistor and grounded, the other end of the second resistor connected to the emitter of the first transistor, and the emitter serving as the output terminal of the Zener reference voltage source circuit.

[0006] Furthermore, the controllable precision voltage regulator adopts TL431.

[0007] Furthermore, the in-phase detection circuit includes a first window voltage adjustment module connected to the power supply regulator circuit via a first constant current source. The first window voltage adjustment module is connected to one end of the third resistor and one end of the fourth resistor respectively. The other end of the third resistor is connected to the collector of the second transistor. The base of the second transistor is connected to one end of the fifth resistor and one end of the first capacitor. The other end of the fifth resistor serves as the input terminal of the in-phase detection circuit.

[0008] The other end of the fourth resistor is connected to the collector of the third transistor, the base of the third transistor is connected to one end of the sixth resistor and one end of the second capacitor, and the other end of the sixth resistor serves as the reference input of the in-phase detection circuit.

[0009] The other end of the first capacitor is connected to the other end of the second capacitor, and grounded through the second constant current source.

[0010] Furthermore, the first window voltage adjustment module includes two paths connected to one end of the third resistor and one end of the fourth resistor, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusion zone and an adjustment resistor connected in series.

[0011] Furthermore, the out-of-phase signal detection circuit includes a second window voltage adjustment module connected to the power supply regulator circuit via a third constant current source. The second window voltage adjustment module is connected to one end of the seventh resistor and one end of the eighth resistor, respectively. The other end of the seventh resistor is connected to the collector of the fourth transistor. The base of the fourth transistor is connected to one end of the ninth resistor and one end of the third capacitor. The other end of the ninth resistor serves as the reference input terminal of the out-of-phase signal detection circuit.

[0012] The other end of the eighth resistor is connected to the collector of the fifth transistor, the base of the fifth transistor is connected to one end of the tenth resistor and one end of the fourth capacitor, and the other end of the tenth resistor serves as the input terminal of the out-of-phase signal detection circuit.

[0013] The other end of the third capacitor is connected to the other end of the fourth capacitor, and grounded through the fourth constant current source.

[0014] Furthermore, the second window voltage adjustment module includes two paths connected to one end of the seventh resistor and one end of the eighth resistor, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusion zone and an adjustment resistor connected in series.

[0015] Furthermore, the window synthesis circuit includes a first diode and a second diode. The anode of the first diode is connected between the first window voltage adjustment module and the fourth resistor, and the anode of the second diode is connected between the second window voltage adjustment module and the eighth resistor. The cathodes of the first and second diodes are connected and connected to one end of the eleventh resistor. The other end of the eleventh resistor is connected to one end of the twelfth resistor and the base of the sixth transistor. The collector of the sixth transistor is connected to one end of the thirteenth resistor, and the other end of the thirteenth resistor is connected to the power supply regulator circuit. The emitter of the sixth transistor is connected to the other end of the twelfth resistor and grounded. The collector of the sixth transistor serves as the output terminal of the window synthesis circuit.

[0016] Furthermore, the frequency divider circuit includes at least four D flip-flops connected in series. Each D flip-flop includes at least a D terminal, a CLK terminal, and a Q terminal. The output terminal of the window synthesis circuit is connected to the D terminal of the first D flip-flop. The CLK terminal of the first D flip-flop is connected to the Q terminal of the first D flip-flop and then to the D terminal of the second D flip-flop. The CLK terminal of the second D flip-flop is connected to the Q terminal of the second D flip-flop and then to the D terminal of the third D flip-flop. The CLK terminal of the third D flip-flop is connected to the Q terminal of the third D flip-flop and then to the D terminal of the fourth D flip-flop. The CLK terminal and Q terminal of the fourth D flip-flop serve as the output terminals of the frequency divider circuit.

[0017] Furthermore, the latch output circuit includes a latch, the output terminal of the frequency divider circuit is connected to the input terminal of the latch, and the output terminal of the latch serves as the drive output terminal of the signal detection circuit.

[0018] In the in-phase signal detection circuit, the second transistor, the fifth resistor, and the first capacitor are integrated input transistors with built-in high-frequency cutoff loops; the third transistor, the sixth resistor, and the second capacitor are integrated input transistors with built-in high-frequency cutoff loops.

[0019] In the out-of-phase signal detection circuit, the fourth transistor, the ninth resistor, and the third capacitor are integrated input transistors with built-in high-frequency cutoff loops; the fifth transistor, the tenth resistor, and the fourth capacitor are integrated input transistors with built-in high-frequency cutoff loops.

[0020] The input transistor with a built-in high-frequency cutoff ring includes a substrate, an epitaxial layer, and an insulating layer arranged sequentially from bottom to top. A buried layer is provided between the substrate and the epitaxial layer. The epitaxial layer has a cylindrical first doped region. An emitter region is provided at the upper part of the first doped region. A capacitor dielectric is provided at the upper part of the emitter region. The first doped region and the capacitor dielectric are led out through a first metal to serve as the base. The emitter region is led out through a second metal to serve as the emitter.

[0021] The upper part of the epitaxial layer also has a second doped region disposed outside the first doped region, and a third doped region is disposed between the first doped region and the second doped region; the second doped region is led out through a third metal.

[0022] The epitaxial layer also has a diffusion region on the right side, which connects the buried layer and the insulating layer. The upper part of the diffusion region has a fourth doped region, which is led out through a fourth metal.

[0023] Furthermore, the first doped region is cylindrical, the emitter region is cylindrical, the capacitor dielectric is cylindrical, the second doped region is cylindrical, and the third doped region is cylindrical. The first doped region, the emitter region, the capacitor dielectric, the second doped region, and the third doped region are arranged concentrically.

[0024] Furthermore, the substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer, the buried layer is an N-type buried layer, the first doped region is a P-type doped region, the emitter region is an N+ emitter region, the second doped region is a P-type doped region, the diffusion region is an N+ diffusion region, and the fourth doped region is a P- doped region.

[0025] Furthermore, the substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, the buried layer is a P-type buried layer, the first doped region is an N-type doped region, the emitter region is a P+ emitter region, the second doped region is an N-type doped region, the diffusion region is a P+ diffusion region, and the fourth doped region is an N- doped region.

[0026] The beneficial effects of this invention are as follows:

[0027] (1) The in-phase signal detection circuit and the out-of-phase signal detection circuit have freely adjustable window voltages;

[0028] (2) The window synthesis circuit, in conjunction with the in-phase signal detection circuit and the out-of-phase signal detection circuit, calculates and latches N (2≤N≤100) high-level pulses within one signal cycle. This effectively avoids interference from external noise while detecting sinusoidal bidirectional signals and pulsating DC signals. This makes the signal detection circuit more suitable for the precise and effective detection requirements of sinusoidal signals or pulsating DC signals. Attached Figure Description

[0029] Figure 1This is a circuit diagram of a signal detection circuit according to the present invention;

[0030] Figure 2 This is a circuit diagram of the first window voltage adjustment module and the second window voltage adjustment module of the present invention.

[0031] Figure 3 This is a schematic diagram of the D flip-flop of the present invention;

[0032] Figure 4 This is a circuit diagram of the gate circuit in the D flip-flop of the present invention;

[0033] Figure 5 This is a schematic diagram of the structure of the input transistor with the built-in high-frequency cutoff ring of the present invention;

[0034] Figure 6 This is the equivalent circuit diagram of the input transistor with the built-in high-frequency cutoff ring of the present invention.

[0035] Figure 7 This is a waveform diagram of the signal detection circuit of the present invention detecting a sine wave signal;

[0036] Among them, substrate 1, epitaxial layer 2, insulating layer 3, buried layer 4, first doped region 5, emitter region 6, capacitor dielectric 7, first metal 8, second metal 9, second doped region 10, third doped region 11, third metal 12, diffusion region 13, fourth doped region 14, and fourth metal 15. Detailed Implementation

[0037] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0038] This invention achieves perfect shielding of high-frequency noise by combining a power supply regulator circuit, a Zener reference voltage source circuit, an in-phase signal detection circuit, an out-of-phase signal detection circuit, a window synthesis circuit, a frequency divider circuit, and a latch output circuit. Furthermore, addressing the issue of significant differences in amplitude and frequency between low-frequency small signal detection, it eliminates the need to select different high-precision operational amplifiers based on varying amplitudes and frequencies; ordinary-precision operational amplifiers (for the in-phase and out-of-phase signal detection circuits) are sufficient, reducing design costs. This invention also provides a signal detection circuit with a built-in high-frequency cutoff loop, allowing for flexible design of signal detection at different frequencies and amplitudes.

[0039] The embodiments of the present invention will be further described below with reference to several examples.

[0040] Example 1

[0041] like Figure 1 A signal detection circuit includes a power supply regulator circuit S, a Zener reference voltage source circuit A, an in-phase signal detection circuit B, an out-of-phase signal detection circuit C, a window synthesis circuit D, a window synthesis circuit E, and a latch output circuit F. The power supply regulator circuit supplies power to the Zener reference voltage source circuit A, the in-phase signal detection circuit B, the out-of-phase signal detection circuit C, and the window synthesis circuit D. The output of the Zener reference voltage source circuit A serves as the reference for the in-phase signal detection circuit B and the out-of-phase signal detection circuit C. The drive outputs of the in-phase signal detection circuit B and the out-of-phase signal detection circuit C serve as the inputs to the window synthesis circuit D. The output of the window synthesis circuit D serves as the input to the window synthesis circuit E. The output of the window synthesis circuit E serves as the input to the latch output circuit F. The output of the latch output circuit F serves as the drive output of the signal detection circuit.

[0042] The Zener reference voltage source circuit A includes a first resistor R1 connected at one end to a power supply regulator circuit, the other end of the first resistor R1 connected to the base of a first transistor Q1 and the cathode of a controllable precision voltage regulator TL, the collector of the first transistor Q1 connected to the power supply regulator circuit, the anode of the controllable precision voltage regulator TL connected to one end of a second resistor R2 and grounded, the other end of the second resistor R2 connected to the emitter of the first transistor Q1, and the emitter serving as the output terminal of the Zener reference voltage source circuit A.

[0043] The specific model of the controllable precision voltage regulator TL is TL431.

[0044] The in-phase detection circuit B includes a first window voltage adjustment module connected to the power supply regulator circuit via a first constant current source S1. The first window voltage adjustment module is connected to one end of the third resistor R3 and one end of the fourth resistor R4. The other end of the third resistor R3 is connected to the collector of the second transistor Q2. The base of the second transistor Q2 is connected to one end of the fifth resistor R5 and one end of the first capacitor C1. The other end of the fifth resistor R5 serves as the input terminal of the in-phase detection circuit.

[0045] The other end of the fourth resistor R4 is connected to the collector of the third transistor Q3. The base of the third transistor Q3 is connected to one end of the sixth resistor R6 and one end of the second capacitor C2. The other end of the sixth resistor R6 serves as the reference input of the in-phase detection circuit B.

[0046] The other end of the first capacitor C1 is connected to the other end of the second capacitor C2, and is grounded through the second constant current source S2.

[0047] like Figure 2 The first window voltage adjustment module includes two paths connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusible area and an adjustment resistor connected in series.

[0048] like Figure 2 The metal fuse mechanism of the window comparator window shown is further explained below:

[0049] On the input side, there are narrow metal regions 1A, 2A, and 3A designated for high-current fusing. On the reference side, there are similar narrow metal regions 1B, 2B, and 3B designated for high-current fusing. When neither fusing regions 1A, 2A, 3A nor 1B, 2B, 3B are completely fused, the window voltage is 0V. That is, the window voltage is the input voltage minus the reference voltage. For an operational amplifier detecting a positive signal, if a positive window voltage is required, one, two, or all of fusing regions 1A, 2A, or 3A should be fused. The resistance values ​​corresponding to the metal regions below each fused region are not identical. Therefore, adjusting the fusing of regions 1A, 2A, and 3A individually can achieve [the desired effect]. 3 -1 refers to 7 window voltages. The three metal fusing areas 1B, 2B, and 3B on the reference side, together with the metal fusing areas 1A, 2A, and 3A, are used for precise fine-tuning. That is, 1A, 2A, and 3A are used to adjust the window voltage range, while the metal fusing areas 1B, 2B, and 3B are used for precision adjustment. Similarly, for operational amplifiers that detect negative phase signals, if a negative window voltage is required, one, two, or all of the fusing areas 1A, 2A, or 3A should be fused. The resistance value corresponding to each fused metal area is not exactly the same. Therefore, fusing adjustment of 1A, 2A, and 3A alone can achieve 23-1, i.e., 7 window voltages. The three metal fusing areas 1B, 2B, and 3B on the reference side, together with the metal fusing areas 1A, 2A, and 3A, are used for precise fine-tuning. That is, 1A, 2A, and 3A are used to adjust the window voltage range, while the metal fusing areas 1B, 2B, and 3B are used for precision adjustment.

[0050] The out-of-phase signal detection circuit C includes a second window voltage adjustment module connected to the power supply regulator circuit via a third constant current source S3. The second window voltage adjustment module is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8. The other end of the seventh resistor R7 is connected to the collector of the fourth transistor Q4. The base of the fourth transistor Q4 is connected to one end of the ninth resistor R9 and one end of the third capacitor C3. The other end of the ninth resistor R9 serves as the reference input terminal of the out-of-phase signal detection circuit C.

[0051] The other end of the eighth resistor R8 is connected to the collector of the fifth transistor Q3. The base of the fifth transistor Q3 is connected to one end of the tenth resistor R10 and one end of the fourth capacitor C4. The other end of the tenth resistor R10 serves as the input terminal of the out-of-phase signal detection circuit C.

[0052] The other end of the third capacitor C3 is connected to the other end of the fourth capacitor C4, and is grounded through the fourth constant current source S4.

[0053] like Figure 2 The second window voltage adjustment module includes two paths connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusible area and an adjustment resistor connected in series.

[0054] The window synthesis circuit D includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected between the first window voltage adjustment module and the fourth resistor R4, and the anode of the second diode D2 is connected between the second window voltage adjustment module and the eighth resistor R8. The cathodes of the first diode D1 and the second diode D2 are connected and connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12 and the base of the sixth transistor Q6. The collector of the sixth transistor Q6 is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the power supply regulator circuit. The emitter of the sixth transistor Q6 is connected to the other end of the twelfth resistor R12 and grounded. The collector of the sixth transistor Q6 serves as the output terminal of the window synthesis circuit D.

[0055] The window synthesis circuit E includes at least four D flip-flops connected in series. Each D flip-flop includes at least a D terminal, a CLK terminal, and a Q terminal. The output of the window synthesis circuit is connected to the D terminal of the first D flip-flop. The CLK terminal of the first D flip-flop is connected to the Q terminal of the first D flip-flop and then to the D terminal of the second D flip-flop. The CLK terminal of the second D flip-flop is connected to the Q terminal of the second D flip-flop and then to the D terminal of the third D flip-flop. The CLK terminal of the third D flip-flop is connected to the Q terminal of the third D flip-flop and then to the D terminal of the fourth D flip-flop. The CLK terminal and Q terminal of the fourth D flip-flop serve as the output of the frequency divider circuit.

[0056] for Figure 3 The D flip-flop shown and Figure 4 The gate circuit implementation shown is a traditional manufacturing method, achieved through integrated injection logic.

[0057] The latch output circuit F includes a latch. The output of the window synthesis circuit E is connected to the input of the latch, and the output of the latch serves as the drive output of the signal detection circuit.

[0058] Example 2

[0059] like Figure 1A signal detection circuit includes a power supply regulator circuit S, a Zener reference voltage source circuit A, an in-phase signal detection circuit B, an out-of-phase signal detection circuit C, a window synthesis circuit D, a window synthesis circuit E, and a latch output circuit F. The power supply regulator circuit supplies power to the Zener reference voltage source circuit A, the in-phase signal detection circuit B, the out-of-phase signal detection circuit C, and the window synthesis circuit D. The output of the Zener reference voltage source circuit A serves as the reference for the in-phase signal detection circuit B and the out-of-phase signal detection circuit C. The drive outputs of the in-phase signal detection circuit B and the out-of-phase signal detection circuit C serve as the inputs to the window synthesis circuit D. The output of the window synthesis circuit D serves as the input to the window synthesis circuit E. The output of the window synthesis circuit E serves as the input to the latch output circuit F. The output of the latch output circuit F serves as the drive output of the signal detection circuit.

[0060] The Zener reference voltage source circuit A includes a first resistor R1 connected at one end to a power supply regulator circuit, the other end of the first resistor R1 connected to the base of a first transistor Q1 and the cathode of a controllable precision voltage regulator TL, the collector of the first transistor Q1 connected to the power supply regulator circuit, the anode of the controllable precision voltage regulator TL connected to one end of a second resistor R2 and grounded, the other end of the second resistor R2 connected to the emitter of the first transistor Q1, and the emitter serving as the output terminal of the Zener reference voltage source circuit A.

[0061] The specific model of the controllable precision voltage regulator TL is TL431.

[0062] The in-phase detection circuit B includes a first window voltage adjustment module connected to the power supply regulator circuit via a first constant current source S1. The first window voltage adjustment module is connected to one end of the third resistor R3 and one end of the fourth resistor R4. The other end of the third resistor R3 is connected to the collector of the second transistor Q2. The base of the second transistor Q2 is connected to one end of the fifth resistor R5 and one end of the first capacitor C1. The other end of the fifth resistor R5 serves as the input terminal of the in-phase detection circuit.

[0063] The other end of the fourth resistor R4 is connected to the collector of the third transistor Q3. The base of the third transistor Q3 is connected to one end of the sixth resistor R6 and one end of the second capacitor C2. The other end of the sixth resistor R6 serves as the reference input of the in-phase detection circuit B.

[0064] The other end of the first capacitor C1 is connected to the other end of the second capacitor C2, and is grounded through the second constant current source S2.

[0065] like Figure 2 The first window voltage adjustment module includes two paths connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusible area and an adjustment resistor connected in series.

[0066] The out-of-phase signal detection circuit C includes a second window voltage adjustment module connected to the power supply regulator circuit via a third constant current source S3. The second window voltage adjustment module is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8. The other end of the seventh resistor R7 is connected to the collector of the fourth transistor Q4. The base of the fourth transistor Q4 is connected to one end of the ninth resistor R9 and one end of the third capacitor C3. The other end of the ninth resistor R9 serves as the reference input terminal of the out-of-phase signal detection circuit C.

[0067] The other end of the eighth resistor R8 is connected to the collector of the fifth transistor Q3. The base of the fifth transistor Q3 is connected to one end of the tenth resistor R10 and one end of the fourth capacitor C4. The other end of the tenth resistor R10 serves as the input terminal of the out-of-phase signal detection circuit C.

[0068] The other end of the third capacitor C3 is connected to the other end of the fourth capacitor C4, and is grounded through the fourth constant current source S4.

[0069] like Figure 2 The second window voltage adjustment module includes two paths connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusible area and an adjustment resistor connected in series.

[0070] like Figure 2 As shown, three metal fuse points are symmetrically arranged at the operational amplifier terminals of the signal detection circuit. These six metal fuse points allow the window voltage to be set according to the designer's actual requirements. The metal fuse mechanism of the window comparator is further explained below:

[0071] On the input side, there are narrow metal fusing points 1A, 2A, and 3A for high-current fusing. On the reference side, there are also narrow metal fusing points 1B, 2B, and 3B for high-current fusing. When metal fusing points 1A, 2A, 3A and 1B, 2B, 3B do not fuse, the window voltage is 0V. That is, the window voltage is the input voltage minus the reference voltage. For an operational amplifier detecting a positive signal, if a positive window voltage is required, one, two, or all of the metal fusing points 1A, 2A, or 3A should be fused. The resistance value corresponding to each metal fusing point is not exactly the same. Therefore, adjusting the fuses of 1A, 2A, and 3A individually can achieve 2 3-1 refers to 7 window voltages. The three metal fuse points 1B, 2B, and 3B on the reference side, together with the metal fuse points 1A, 2A, and 3A, are used for precise fine-tuning. That is, 1A, 2A, and 3A are used to adjust the window voltage range, while the metal fuse points 1B, 2B, and 3B are used for precision adjustment. Similarly, for operational amplifiers that detect negative phase signals, if a negative window voltage is required, one, two, or all of the metal fuse points 1A, 2A, or 3A should be melted. The resistance value of the resistor corresponding to each metal fuse point is not exactly the same. Therefore, by individually melting and adjusting 1A, 2A, and 3A, 23-1 can achieve 7 window voltages. The three metal fuse points 1B, 2B, and 3B on the reference side, together with the metal fuse points 1A, 2A, and 3A, are used for precise fine-tuning. That is, 1A, 2A, and 3A are used to adjust the window voltage range, while the metal fuse points 1B, 2B, and 3B are used for precision adjustment.

[0072] The window synthesis circuit D includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected between the first window voltage adjustment module and the fourth resistor R4, and the anode of the second diode D2 is connected between the second window voltage adjustment module and the eighth resistor R8. The cathodes of the first diode D1 and the second diode D2 are connected and connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12 and the base of the sixth transistor Q6. The collector of the sixth transistor Q6 is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the power supply regulator circuit. The emitter of the sixth transistor Q6 is connected to the other end of the twelfth resistor R12 and grounded. The collector of the sixth transistor Q6 serves as the output terminal of the window synthesis circuit D.

[0073] The window comparator is composed of an in-phase signal detection circuit B, an out-of-phase signal detection circuit C, and a window combining circuit D. It can achieve the following: when the input + > 2.5V, the output is a high voltage signal because diode D1 in the window combiner is in the forward-biased state; similarly, when 2.5V > input -, the output is still a high voltage signal because diode D2 in the window combiner is in the forward-biased state. However, when the input + < 2.5V or the input - > 2.5V, both diodes D1 and D2 in the window combiner are in the reverse-biased cutoff state, resulting in a low voltage signal at the output.

[0074] The window synthesis circuit E includes at least four D flip-flops connected in series. Each D flip-flop includes at least a D terminal, a CLK terminal, and a Q terminal. The output of the window synthesis circuit is connected to the CLK terminal of the first D flip-flop. The D terminal of the first D flip-flop is connected to the Q terminal of the first D flip-flop and then to the CLK terminal of the second D flip-flop. The D terminal of the second D flip-flop is connected to the Q terminal of the second D flip-flop and then to the CLK terminal of the third D flip-flop. The D terminal of the third D flip-flop is connected to the Q terminal of the third D flip-flop and then to the CLK terminal of the fourth D flip-flop. The D terminal and Q terminal of the fourth D flip-flop serve as the output of the frequency divider circuit.

[0075] Multiple identical D flip-flops are triggered by six different gate circuits, such as... Figure 3 As shown. For Figure 3 The D flip-flop shown and Figure 4 The gate circuits in the D flip-flop shown are implemented using integrated injection logic technology in bipolar integrated circuit manufacturing, which is a traditional manufacturing method.

[0076] The latch output circuit F includes a latch. The output of the window synthesis circuit E is connected to the input of the latch, and the output of the latch serves as the drive output of the signal detection circuit.

[0077] In this embodiment, the second transistor, the fifth resistor, and the first capacitor are integrated input transistors with built-in high-frequency cutoff loops; the third transistor, the sixth resistor, and the second capacitor are integrated input transistors with built-in high-frequency cutoff loops; the fourth transistor, the ninth resistor, and the third capacitor are integrated input transistors with built-in high-frequency cutoff loops; and the fifth transistor, the tenth resistor, and the fourth capacitor are integrated input transistors with built-in high-frequency cutoff loops.

[0078] The output signal of the window synthesis circuit E passes through a frequency divider composed of multiple identical D flip-flops. Combined with the cutoff frequency of the high-frequency cutoff loop, it completes N window voltage detections within one or more complete cycles of a sine wave signal or multiple complete cycles of a pulsating DC signal and outputs a high-voltage level signal.

[0079] like Figure 5 The input transistor with a built-in high-frequency cutoff ring includes a substrate 1, an epitaxial layer 2, and an insulating layer 3 arranged sequentially from bottom to top. A buried layer 4 is provided between the substrate 1 and the epitaxial layer 2. The epitaxial layer 2 has a cylindrical first doped region 5. The upper part of the first doped region 5 has a cylindrical emitter region 6. A cylindrical capacitor dielectric 7 is provided on the upper part of the emitter region 6. The first doped region 5 and the capacitor dielectric 7 are led out through a first metal 8 as the base. The emitter region 6 is led out through a second metal 9 as the emitter.

[0080] The upper part of the epitaxial layer 2 also has a cylindrical second doped region 10 disposed outside the first doped region 5, and a cylindrical third doped region 11 is disposed between the first doped region 5 and the second doped region 10; the second doped region 10 is led out through the third metal 12.

[0081] The epitaxial layer 2 also has a diffusion region 13 on the right side, which connects the buried layer 4 and the insulating layer 3. The upper part of the diffusion region 13 has a fourth doped region 14, which is led out through a fourth metal 15.

[0082] The first doped region, emitter region, capacitor dielectric, second doped region, and third doped region are arranged concentrically.

[0083] Specifically, it includes a P-type substrate 1, an N-type epitaxial layer 2, and an insulating layer 3 arranged sequentially from bottom to top. An N-type buried layer 4 is located between the P-type substrate 1 and the N-type epitaxial layer 2. The N-type epitaxial layer 2 has a cylindrical first P-type region 5. The upper part of the first P-type region 5 has a cylindrical N+ emitter region 6. A cylindrical capacitor dielectric 7 is disposed on the upper part of the N+ emitter region 6. The first P-type region 5 and the capacitor dielectric 7 are led out through a first metal 8 as the base. The N+ emitter region 6 is led out through a second metal 9 as the emitter.

[0084] The N-type epitaxial layer 2 also has a cylindrical second P-type region 10 disposed outside the first P-type region 5, and a cylindrical first P-region 11 is disposed between the first P-type region 5 and the second P-type region 10; the second P-type region 10 is led out through the third metal 12.

[0085] The right side of the N-type epitaxial layer 2 also has an N+ diffusion region 13, which connects the N-type buried layer 4 and the insulating layer 3. The upper part of the N+ diffusion region 13 has a third P-type region 14, which is led out through the fourth metal 15.

[0086] The first P-type region 5, the N+ emitter region 6, the capacitor dielectric 7, the first P- region 11, and the second P-type region 10 are arranged concentrically.

[0087] In some embodiments, the P-type doping of the input transistor with the built-in high-frequency cutoff ring can be N-type doping, and the N-type doping can be P-type doping.

[0088] Figure 6 This is the equivalent circuit of the input transistor with a built-in high-frequency cutoff loop.

[0089] The frequency divider circuit, in conjunction with the high-frequency cutoff loop in the signal detection circuit, calculates and latches N (2≤N≤100) high-level pulses within one signal cycle. This effectively avoids interference from external noise while simultaneously detecting bidirectional sinusoidal signals and pulsating DC signals. This makes the signal detection circuit more suitable for the precise and effective detection requirements of sinusoidal or pulsating DC signals.

[0090] The signal input is the detected signal, and the input + terminal and the reference terminal are respectively connected to the transistor Q1 with the built-in high-frequency cutoff loop. Figure 2 The B1 terminal shown is connected to the transistor Q2 with the built-in high-frequency cutoff ring as described above. Figure 2 As shown, end B1 passes through... Figure 3 After the window voltage comparator controlled by the metal fuse mechanism shown, if the input + voltage minus the reference voltage is greater than or equal to the window voltage, the transistor Q2 with the built-in high-frequency cutoff loop will... Figure 2 The C terminal outputs a high voltage, as shown. Figure 1 In the window synthesizer shown, diode D1 is turned on. After signal amplification and inversion transistor Q5, a low-voltage signal is finally output to the CLK terminal of the frequency divider. A certain area of ​​electrical charge is placed around or to one side of the emitter of the NPN transistor, which serves as the signal input terminal. If the input + voltage minus the reference voltage is less than or equal to the window voltage, the transistor Q2 with the built-in high-frequency cutoff ring... Figure 2 The C terminal outputs a low voltage, as shown. Figure 1 In the window synthesizer shown, diode D1 is cut off. After signal amplification and inversion transistor Q5 in the window synthesizer, a high voltage signal is finally output to the CLK terminal of the frequency divider.

[0091] In the signal input—the detected signal, the input terminal and the reference terminal are respectively connected to the transistor with the built-in high-frequency cutoff loop, as shown below. Figure 2 The B1 terminal shown is connected to the transistor Q3 with the built-in high-frequency cutoff ring as described above. Figure 2 As shown, end B1 passes through... Figure 3 After the window voltage comparator controlled by the metal fuse mechanism shown, if the input voltage minus the reference voltage is greater than or equal to the window voltage, the transistor with the built-in high-frequency cutoff loop will... Figure 2 The C terminal outputs a low voltage, as shown. Figure 1 In the window synthesizer shown, the second diode D2 is cut off. After signal amplification and inversion transistor Q5 in the window synthesizer, a high-voltage signal is finally output to the CLK terminal of the frequency divider. If the input voltage minus the reference voltage is less than or equal to the window voltage, the transistor with the built-in high-frequency cutoff loop will... Figure 6 The fourth metal terminal 15, as shown, outputs a high voltage, such as Figure 6In the window synthesizer shown, diode D2 is turned on. After signal amplification and inversion transistor Q5 in the window synthesizer, a low voltage signal is finally output to the CLK terminal of the frequency divider.

[0092] As described above, after N high-level events occur within one cycle, and then... Figure 1 After the frequency division shown, a final high level is provided and latched through the driver output port. This ensures that if there are no N high-level inversions within one cycle of the detected signal, the driver output cannot latch the signal after N frequency division. For example, a waveform diagram for detecting a sine wave signal is shown below. Figure 7 As shown.

[0093] about Figure 6 The working principle of the input transistor (NPN type) with a built-in high-frequency cutoff loop shown is further explained below:

[0094] As a signal input terminal Figure 1 The NPN transistors Q1, Q2, Q3, and Q4 shown are all transistor structures with built-in high-frequency cutoff rings, such as... Figure 2 As shown. That is, as Figure 1 The NPN transistors Q1, Q2, Q3, and Q4 shown have a capacitor region of a certain area surrounding or on one side of their emitters. The dielectric of the capacitor can be silicon dioxide, silicon nitride, or a composite material of both, and is connected to the base of the NPN transistor via a metal layer. Figure 5 The first metal 8 shown achieves electrical connection, while the base region of the NPN transistor, which serves as the input terminal, is as follows: Figure 5 The first metal 8 shown is used as a signal input terminal as follows: Figure 5 The third metal 12 shown are connected via a P-resistor region. This P-resistor, together with a capacitor of a certain area disposed around or on one side of the emitter of the NPN transistor, which serves as the signal input terminal, forms a high-frequency cutoff loop. Figure 5 As shown. The cutoff frequency of this high-frequency cutoff loop follows the formula f T =1 / 2πRC, optional. Designers can set different resistance and capacitance values ​​to achieve different cutoff frequency requirements depending on the application of the product.

[0095] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A signal detection circuit, characterized in that, The circuit includes a power supply regulator circuit, a Zener reference voltage source circuit, an in-phase signal detection circuit, an out-of-phase signal detection circuit, a window synthesis circuit, a frequency divider circuit, and a latch output circuit. The power supply regulator circuit supplies power to the Zener reference voltage source circuit, the in-phase signal detection circuit, the out-of-phase signal detection circuit, and the window synthesis circuit. The output of the Zener reference voltage source circuit serves as the reference for the in-phase signal detection circuit and the out-of-phase signal detection circuit. The drive outputs of the in-phase signal detection circuit and the out-of-phase signal detection circuit serve as the inputs to the window synthesis circuit. The output of the window synthesis circuit serves as the input to the frequency divider circuit. The output of the frequency divider circuit serves as the input to the latch output circuit. The output of the latch output circuit serves as the drive output of the signal detection circuit. The in-phase signal detection circuit includes a first window voltage adjustment module connected to a power supply regulator circuit via a first constant current source. The first window voltage adjustment module is connected to one end of a third resistor and one end of a fourth resistor. The other end of the third resistor is connected to the collector of a second transistor. The base of the second transistor is connected to one end of a fifth resistor and one end of a first capacitor. The other end of the fifth resistor serves as the input terminal of the in-phase signal detection circuit. The other end of the fourth resistor is connected to the collector of the third transistor. The base of the third transistor is connected to one end of a sixth resistor and one end of a second capacitor. The other end of the sixth resistor serves as the reference input terminal of the in-phase signal detection circuit. The other end of the first capacitor is connected to the other end of the second capacitor and grounded via a second constant current source. In the in-phase signal detection circuit, the second transistor, the fifth resistor, and the first capacitor are integrated input transistors with built-in high-frequency cutoff loops. An input transistor with a built-in high-frequency cutoff ring includes a substrate, an epitaxial layer, and an insulating layer arranged sequentially from bottom to top. A buried layer is located between the substrate and the epitaxial layer. The epitaxial layer has a cylindrical first doped region. An emitter region is located at the upper part of the first doped region, and a capacitor dielectric is located at the upper part of the emitter region. The first doped region and the capacitor dielectric are led out through a first metal to serve as the base. The emitter region is led out through a second metal to serve as the emitter. The upper part of the epitaxial layer also has a second doped region located outside the first doped region. A third doped region is located between the first and second doped regions. The second doped region is led out through a third metal. The right side of the epitaxial layer also has a diffusion region that connects the buried layer and the insulating layer. The upper part of the diffusion region has a fourth doped region, which is led out through a fourth metal.

2. The signal detection circuit according to claim 1, characterized in that, The Zener reference voltage source circuit includes a first resistor connected at one end to a power supply regulator circuit, the other end of the first resistor connected to the base of a first transistor and the cathode of a controllable precision voltage regulator, the collector of the first transistor connected to the power supply regulator circuit, the anode of the controllable precision voltage regulator connected to one end of a second resistor and grounded, the other end of the second resistor connected to the emitter of the first transistor, and the emitter serving as the output terminal of the Zener reference voltage source circuit.

3. The signal detection circuit according to claim 1, characterized in that, The first window voltage adjustment module includes two paths connected to one end of the third resistor and one end of the fourth resistor, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusion zone and an adjustment resistor connected in series.

4. The signal detection circuit according to claim 1, characterized in that, The out-of-phase signal detection circuit includes a second window voltage adjustment module connected to a power supply regulator circuit via a third constant current source. The second window voltage adjustment module is connected to one end of a seventh resistor and one end of an eighth resistor. The other end of the seventh resistor is connected to the collector of a fourth transistor. The base of the fourth transistor is connected to one end of a ninth resistor and one end of a third capacitor. The other end of the ninth resistor serves as the reference input terminal of the out-of-phase signal detection circuit. The other end of the eighth resistor is connected to the collector of a fifth transistor. The base of the fifth transistor is connected to one end of a tenth resistor and one end of a fourth capacitor. The other end of the tenth resistor serves as the input terminal of the out-of-phase signal detection circuit. The other end of the third capacitor is connected to the other end of the fourth capacitor and grounded via a fourth constant current source. In the out-of-phase signal detection circuit, the fourth transistor, the ninth resistor, and the third capacitor are integrated input transistors with built-in high-frequency cutoff loops; the fifth transistor, the tenth resistor, and the fourth capacitor are integrated input transistors with built-in high-frequency cutoff loops.

5. The signal detection circuit according to claim 4, characterized in that, The second window voltage adjustment module includes two paths connected to one end of the seventh resistor and one end of the eighth resistor, respectively. Each path consists of three sets of adjustment modules connected in parallel. Each adjustment module consists of a metal fusion zone and an adjustment resistor connected in series.

6. The signal detection circuit according to claim 1, characterized in that, The window synthesis circuit includes a first diode and a second diode. The anode of the first diode is connected between the first window voltage adjustment module and the fourth resistor, and the anode of the second diode is connected between the second window voltage adjustment module and the eighth resistor. The cathodes of the first and second diodes are connected and connected to one end of the eleventh resistor. The other end of the eleventh resistor is connected to one end of the twelfth resistor and the base of the sixth transistor. The collector of the sixth transistor is connected to one end of the thirteenth resistor, and the other end of the thirteenth resistor is connected to the power supply regulator circuit. The emitter of the sixth transistor is connected to the other end of the twelfth resistor and grounded. The collector of the sixth transistor serves as the output terminal of the window synthesis circuit.

7. The signal detection circuit according to claim 1, characterized in that, The frequency divider circuit includes at least four D flip-flops connected in series. Each D flip-flop includes at least a D terminal, a CLK terminal, and a Q terminal. The output terminal of the window synthesis circuit is connected to the D terminal of the first D flip-flop. The CLK terminal of the first D flip-flop is connected to the Q terminal of the first D flip-flop and then to the D terminal of the second D flip-flop. The CLK terminal of the second D flip-flop is connected to the Q terminal of the second D flip-flop and then to the D terminal of the third D flip-flop. The CLK terminal of the third D flip-flop is connected to the Q terminal of the third D flip-flop and then to the D terminal of the fourth D flip-flop. The CLK terminal and Q terminal of the fourth D flip-flop serve as the output terminals of the frequency divider circuit.

8. The signal detection circuit according to claim 1, characterized in that, The latch output circuit includes a latch, the output of the frequency divider circuit is connected to the input of the latch, and the output of the latch serves as the drive output of the signal detection circuit.

9. The signal detection circuit according to claim 1, characterized in that, The first doped region is cylindrical, the emitter region is cylindrical, the capacitor dielectric is cylindrical, the second doped region is cylindrical, and the third doped region is cylindrical. The first doped region, emitter region, capacitor dielectric, second doped region, and third doped region are arranged concentrically.

10. The signal detection circuit according to claim 1, characterized in that, The substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer, the buried layer is an N-type buried layer, the first doped region is a P-type doped region, the emitter region is an N+ emitter region, the second doped region is a P-type doped region, the diffusion region is an N+ diffusion region, and the fourth doped region is a P- doped region.

11. The signal detection circuit according to claim 1, characterized in that, The substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, the buried layer is a P-type buried layer, the first doped region is an N-type doped region, the emitter region is a P+ emitter region, the second doped region is an N-type doped region, the diffusion region is a P+ diffusion region, and the fourth doped region is an N- doped region.

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