Chip I / O port detection method and device, electronic equipment and storage medium

Abstract

The invention relates to the field of chip detection, and provides a chip I / O port detection method and device, electronic equipment and a storage medium, and the method comprises the steps: configuring an I / O port to be in a general input / output mode; writing the first value into the first register; controlling a voltage control sub-module in the second driving module to output a second level signal; reading a second value of a second register connected with the second driving module, and determining a first detection result according to the second value; writing the third value into the first register; controlling a voltage control sub-module in the second driving module to output a first level signal; reading a fourth value of a second register connected with the second driving module, and determining a second detection result according to the fourth value; and determining whether the I / O port is normal according to the first detection result and the second detection result. According to the method, the I / O state can be judged by configuring the numerical value of the register, the chip does not need to be taken down for testing, the I / O port on the chip can be directly and quickly tested through software, and the testing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing, and more specifically to a chip I / O port testing method, apparatus, electronic device, and storage medium. Background Technology

[0002] Chip damage can occur during factory production, with I / O port damage being a common occurrence, such as an I / O port being opened by static electricity.

[0003] However, currently testing I / O ports requires removing the chip for testing, such as removing the chip and placing it in a socket for testing on a Design Verification I / O Test (DVT) board, which is very cumbersome and time-consuming. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application provides a chip I / O port testing method, apparatus, electronic device, and storage medium, which facilitates direct testing of chip I / O ports using software methods.

[0005] To address the above problems, the present invention provides the following technical solution: In a first aspect, embodiments of this application provide a chip I / O port detection method, the method comprising: Configure the I / O ports to general purpose input / output mode; Write a first value into the first register so that the first driver module connected to the first register outputs a first level signal to the second driver module; Control the voltage control submodule in the second drive module to output a second-level signal; Read the second value of the second register connected to the second driver module, and determine the first detection result based on the second value; Write a third value into the first register so that the first driver module connected to the first register outputs a second level signal to the second driver module; Control the voltage control submodule in the second drive module to output a first level signal; Read the fourth value of the second register connected to the second driver module, and determine the second detection result based on the fourth value; Determine whether the I / O port is normal based on the first detection result and the second detection result.

[0006] In some implementations, determining the first detection result based on the second value includes: When the second value is the same as the first value, the first detection result is determined to be passed; If the second value is different from the first value, the first detection result is determined to be unsuccessful.

[0007] In some implementations, determining the second detection result based on the fourth value includes: When the fourth value is the same as the third value, the second detection result is determined to be passed; When the fourth value is different from the third value, the second detection result is determined to be a failure.

[0008] In some implementations, determining whether the I / O port is functioning correctly based on the first detection result and the second detection result includes: If at least one of the first detection result and the second detection result is passed, the I / O port is determined to be normal; If both the first and second test results are negative, the I / O port is determined to be damaged.

[0009] In some embodiments, the second driving module includes a sensing resistor, a first end of which is connected to the voltage control submodule, and a second end of which is connected to the I / O pin and the first driving module; When the detection resistor is damaged, causing the circuit to open, the value of the second register is controlled by the level signal output by the voltage control submodule; When the detection resistor is normal and the I / O pin does not receive external voltage, the value of the second register is controlled by the level signal output by the first drive module to the second drive module; When the detection resistor is normal and the I / O pin receives an external voltage, the value of the second register is controlled by the external voltage.

[0010] In some embodiments, controlling the voltage control submodule in the second drive module to output a second-level signal includes: The first switch in the voltage control submodule is turned on and the second switch is turned off, so that the second register is connected to the first voltage source; The control of the voltage control submodule in the second drive module to output a first level signal includes: The first switch in the voltage control submodule is turned off and the second switch is turned on, so that the second register is connected to the second voltage source.

[0011] In some implementations, the configured I / O port is in general-purpose input / output mode, including: Configure the Nth I / O port as a general-purpose input / output port; where the initial state of N is 1; The method further includes: If the first detection result and the second detection result determine that the Nth I / O port is normal, set N=N+1, and return to the execution step to configure the Nth I / O port as a general input / output mode; When the Nth I / O port is determined to be damaged based on the first detection result and the second detection result, the information of the Nth I / O port is recorded, N=N+1, and the execution step is returned to configure the Nth I / O port as a general input / output mode.

[0012] Secondly, embodiments of this application provide a chip I / O port detection device, the device comprising: Configuration unit, used to configure I / O ports as general purpose input / output mode; The first writing unit is used to write a first value into the first register, so that the first driving module connected to the first register outputs a first level signal to the second driving module. The first control unit is used to control the voltage control submodule in the second drive module to output a second level signal; The first reading unit is used to read the second value of the second register connected to the second driving module and determine the first detection result based on the second value. The second writing unit is used to write a third value into the first register, so that the first driving module connected to the first register outputs a second level signal to the second driving module. The second control unit is used to control the voltage control submodule in the second drive module to output a first level signal; The second reading unit is used to read the fourth value of the second register connected to the second driving module, and determine the second detection result based on the fourth value; The determining unit is used to determine whether the I / O port is normal based on the first detection result and the second detection result.

[0013] Thirdly, embodiments of this application provide an electronic device, the electronic device comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform a chip I / O port detection method as described in the first aspect.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing an executable program, which is executed by a processor to implement the chip I / O port detection method of the first aspect.

[0015] This application provides a chip I / O port detection method, apparatus, electronic device, and storage medium. The method includes: configuring the I / O port to a general-purpose input / output (GPIO) mode; writing a first value to a first register to cause a first driver module connected to the first register to output a first-level signal to a second driver module; controlling a voltage control submodule in the second driver module to output a second-level signal; reading a second value from a second register connected to the second driver module and determining a first detection result based on the second value; writing a third value to the first register to cause the first driver module connected to the first register to output a second-level signal to the second driver module; controlling a voltage control submodule in the second driver module to output a first-level signal; reading a fourth value from the second register connected to the second driver module and determining a second detection result based on the fourth value; and determining whether the I / O port is normal based on the first detection result and the second detection result. This application configures the I / O port to GPIO mode. By configuring the value of the first register and the output level of the voltage control submodule, the state of the I / O port can be determined by reading the value of the second register. This eliminates the need to remove the chip for testing and allows for rapid testing of the I / O ports on the chip directly through software, reducing testing time and costs. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an I / O port bit circuit provided in an embodiment of this application.

[0017] Figure 2 This is a schematic diagram illustrating an application scenario of a chip I / O port detection method provided in this application.

[0018] Figure 3 This is a flowchart illustrating a chip I / O port detection method provided in an embodiment of this application.

[0019] Figure 4 This is a schematic diagram of the structure of a chip I / O port detection device provided in an embodiment of this application.

[0020] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0021] Figure 6 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] For ease of explanation, the embodiments of this application use a scaler chip as an example.

[0025] During the factory production process, scaler chips may be damaged. One of the more common situations is I / O damage (caused by static electricity to create an open circuit).

[0026] The conventional detection method includes the following three steps: 1. Remove the scaler chip and place it in the socket for testing on the DVT board. The diode characteristics of the I / O port need to be measured. 2. Configure the I / O port to GPIO mode and input direction using software, connect a controllable level to the I / O pin as an input, and test the function of the input data register (second register) in the I / O port.

[0027] 3. Configure the I / O port to GPIO mode and output direction through software, write data to the output data register (first register), and make the I / O pin output a specific waveform to test its output function.

[0028] The above measurement process requires tools such as sockets, DVT boards, programming boards, logic analyzers, and DuPont wires for testing, which is complicated and inefficient. Furthermore, only one GPIO port can be tested at a time, and testing all GPIO ports of a chip is very time-consuming.

[0029] Please see Figure 1 , Figure 1 This is a schematic diagram of an I / O port bit circuit provided in an embodiment of this application. For example... Figure 1 As shown, the I / O port bit circuit 1 includes: a first register 10, a first driver module 20, a second driver module 30, a second register 40, and an I / O pin 50.

[0030] In some implementations, the second driving module 30 includes a detection resistor R1. The inventors of this application, through analysis of a large number of chips with damaged I / O, discovered that when a chip's I / O is damaged, the detection resistor R1 will inevitably be damaged first, forming an open circuit, i.e., the second register 40 will fail. Only when a large static electricity is introduced will the NMOS transistor and / or PMOS transistor at the first driving module 20 be damaged, causing the first register 10 to fail. The chip I / O port detection method in this application is also based on this principle.

[0031] In some implementations, the first register 10 can be written with 0 or 1.

[0032] In some implementations, when the first drive module 20 writes 0 to the first register, the NMOS is turned on and the PMOS is turned off, outputting a low-level signal to the second drive module 30; when the first drive module 20 writes 1 to the first register, the PMOS is turned on and the NMOS is turned off, outputting a high-level signal to the second drive module 30.

[0033] In some embodiments, the second drive module 30 includes a voltage control submodule 31, which includes a first switch K1 and a second switch K2.

[0034] When the first switch K1 is turned on and the second switch K2 is turned off, the second register 40 is connected to the first voltage source, which is used to provide a low-level signal.

[0035] When the first switch K1 is turned off and the second switch K2 is turned on, the second register 40 is connected to the second voltage source, which is used to provide a high-level signal.

[0036] In some implementations, the second register 40 corresponds to a switching threshold. When the voltage input to the second register 40 is less than the switching threshold, the value of the second register 40 is 0, and when the voltage input to the second register 40 is greater than the switching threshold, the value of the second register 40 is 1.

[0037] In some implementations, in order to achieve the detection purpose, the level signal output by the first driving module 20 to the second driving module 30 is opposite to the level signal output by the voltage control submodule 31.

[0038] In some implementations, when the detection resistor R1 is normal and the I / O pin does not receive external voltage, the second register 40 simultaneously receives opposite level signals output by the first driving module 20 and the voltage control submodule 31, but the value of the second register 40 is controlled by the level signal output by the first driving module 20 to the second driving module 30.

[0039] For example, when the detection resistor R1 is normal and the I / O pin does not receive external voltage, if the first driving module 20 outputs a high-level signal to the second driving module 30 and the voltage control submodule 31 outputs a low-level signal, the value of the second register 40 is controlled to be 1 by the high-level signal output by the first driving module 20; if the first driving module 20 outputs a low-level signal to the second driving module 30 and the voltage control submodule 31 outputs a high-level signal, the value of the second register 40 is controlled to be 0 by the low-level signal output by the first driving module 20.

[0040] Furthermore, multiplexed I / O refers to a physical I / O port that can perform different functions depending on different configurations or operating modes. This means that the same I / O port can be used for multiple purposes, such as being used as a general-purpose input / output (GPIO) port, or configured as a serial peripheral interface (SPI), an inter-integrated circuit (I2C) bus, or a communication interface for other peripherals.

[0041] In some implementations, due to limited internal space and numerous peripherals that need to be connected in electronic devices, chip designs often reuse I / O ports as much as possible to reduce the number of pins. When the I / O port being tested is a reused I / O port, there may be strong pull-up or strong pull-down at the I / O pin.

[0042] A strong pull-up can be understood as a high-level signal being input at the I / O pin. When the sensing resistor R1 is normal, this high-level signal will always make the voltage received by the second register 40 higher than the switching threshold, so that the value written to the first register 10 cannot affect the value of the second register 40. That is, when the sensing resistor R1 is normal, the strong pull-up will lock the value of the second register 40 to 1.

[0043] A strong pull-down can be understood as a low-level signal being input at the I / O pin. When the sensing resistor R1 is normal, this low-level signal will keep the voltage received by the second register 40 below the switching threshold, so that the value written to the first register 10 cannot affect the value of the second register 40. That is, when the sensing resistor R1 is normal, the strong pull-down will lock the value of the second register 40 to 0.

[0044] It is understandable that if the chip is removed for testing, there will be no strong pull-up or strong pull-down. Therefore, how to overcome the effects of strong pull-up and strong pull-down without removing the chip for testing is a technical problem that needs to be further solved.

[0045] In some implementations, the I / O port bit circuit 1 further includes a bit set / clear register 60, which is used to control the value of a single bit in the first register 10.

[0046] Please see Figure 2 , Figure 2 This is a schematic diagram illustrating an application scenario of the chip I / O port detection method provided in this application. For example... Figure 2 As shown, the application scenario 100 includes: electronic device 110, programming board 120, handheld device 130, and mobile terminal 140.

[0047] In some implementations, electronic device 110 is connected to a programming board 120 via USB. The programming board 120 is connected to a handle 130 with pins via DuPont wires in a specific wiring sequence. The pins of the handle 130 contact the programming points on the mobile terminal 140 in a specific wiring sequence. After the connection is completed, electronic device 110 reads and writes the registers of the chip in the mobile terminal 140 via the SWD protocol and executes the chip I / O port detection method.

[0048] In some implementations, firmware that can be programmed into the chip can be designed directly. The electronic device 110 programs the firmware into the chip via the SWD protocol, allowing the chip to execute the I / O port detection method described above through the firmware. The electronic device 110 is only used to obtain the detection results.

[0049] Optionally, the mobile terminal 140 is a mobile phone, and the chip is a scaler chip in the mobile phone screen.

[0050] Please see Figure 3 , Figure 3 This is a flowchart illustrating a chip I / O port detection method provided in an embodiment of this application. Figure 3 As shown, the detection method 200 includes steps 210 to 280.

[0051] Step 210: Configure the I / O port to general purpose input / output mode.

[0052] In some implementations, the I / O port includes GPIO mode, multiplexed open-drain output mode, and multiplexed push-pull output mode.

[0053] Step 220: Write a first value into the first register so that the first driver module connected to the first register outputs a first level signal to the second driver module.

[0054] In some implementations, a first value is written to a first register via a bit set / clear register. Bit set / clear registers are a common type of register in computer hardware, especially in embedded systems and microcontrollers. They allow users to set or clear specific bits individually without affecting other bits in the register.

[0055] Furthermore, registers typically include multiple bits that can be independently set to 0 or 1. For example, registers may include 8-bit registers, 16-bit registers, 32-bit registers, etc. Therefore, in some implementations, step 220 includes the following steps.

[0056] Write a first value to a specific location in the first register so that the first driving module connected to the first register outputs a first level signal to the second driving module.

[0057] Specifically, the number of digits for a particular position can be selected as needed, and this application does not impose any restrictions.

[0058] In some implementations, writing a 1 to a specific position in the first register causes the first driver module connected to the first register to output a high-level signal to the second driver module; writing a 0 to a specific position in the first register causes the first driver module connected to the first register to output a low-level signal to the second driver module.

[0059] Step 230: Control the voltage control submodule in the second drive module to output a second level signal.

[0060] In some implementations, the first level signal is the opposite of the second level signal.

[0061] In some implementations, when the I / O port is in GPIO mode, it includes pull-down input mode and pull-up input mode.

[0062] Specifically, the pull-down input mode means that when there is no external signal input, the input level is kept low by an internal pull-down resistor.

[0063] Specifically, the pull-up input mode means that when there is no external signal input, the input level is made high by the internal pull-up resistor.

[0064] In some implementations, controlling the voltage control submodule in the second driver module to output a second level signal is to make the I / O port be in either pull-down input mode or pull-up input mode in GPIO mode. Whether it is pull-down input mode or pull-up input mode needs to be determined by the first level signal.

[0065] When the first level signal is high, the control voltage control submodule outputs the second level signal to put the I / O port into pull-down input mode; when the first level signal is low, the control voltage control submodule outputs the second level signal to put the I / O port into pull-up input mode.

[0066] Step 240: Read the second value of the second register connected to the second driver module, and determine the first detection result based on the second value.

[0067] In some embodiments, the second driving module includes a sensing resistor, the first end of which is connected to the voltage control submodule, and the second end of which is connected to an I / O pin and the first driving module.

[0068] When the detection resistor is damaged, causing the circuit to open, the value of the second register is controlled by the level signal output by the voltage control submodule; for example, if the voltage control submodule outputs a low level signal, the value of the second register is 0; if the voltage control submodule outputs a high level signal, the value of the second register is 1.

[0069] In some implementations, when the detection resistor is normal and the I / O pin does not receive external voltage, the value of the second register is controlled by the level signal output by the first driving module to the second driving module; for example, if the first driving module outputs a low level signal, the value of the second register is 0; if the first driving module outputs a high level signal, the value of the second register is 1.

[0070] In some implementations, when the detection resistor is normal and the I / O pin receives an external voltage, the value of the second register is controlled by the external voltage; if the external voltage is a high-level signal, i.e., there is a strong pull-up, the value of the second register is always 1; if the external voltage is a low-level signal, i.e., there is a strong pull-down, the value of the second register is always 0.

[0071] In some implementations, step 240 includes the following steps.

[0072] (1) When the second value is the same as the first value, the first detection result is determined to be passed.

[0073] (2) When the second value is different from the first value, the first detection result is determined to be unsuccessful.

[0074] For ease of explanation, the following parts of this application will be used as examples with the first value being 1 and the third value being 0 by default.

[0075] In some implementations, the first detection result is that the second register can still be controlled by the first register, or the second register is being controlled by an external strong pull-up voltage; the first detection result is that the second register cannot be controlled by the first register, but at this time the second register may be controlled by an external strong pull-down voltage.

[0076] Therefore, if the first test result is passed, it can be determined that the I / O port is in normal condition. However, if the first test result is failed, the I / O port status cannot be determined and needs to be further determined in conjunction with the second test result.

[0077] Step 250: Write a third value into the first register so that the first driver module connected to the first register outputs a second level signal to the second driver module.

[0078] In some implementations, step 250 includes the following steps.

[0079] Write a third value to a specific position in the first register so that the first driver module connected to the first register outputs a second level signal to the second driver module.

[0080] For further details, please refer to the above sections of the instruction manual, which will not be repeated here.

[0081] Step 260: Control the voltage control submodule in the second drive module to output a first level signal.

[0082] In some implementations, step 230 includes the following steps.

[0083] (1) Control the first switch in the voltage control submodule to turn on and the second switch to turn off, so that the second register is connected to the first voltage source.

[0084] Based on step (1), step 260 includes the following steps.

[0085] (2) Control the first switch in the voltage control submodule to turn off and the second switch to turn on, so that the second register is connected to the second voltage source.

[0086] In some implementations, controlling the voltage control submodule in the second driver module to output a first-level signal is to put the I / O port into either pull-down or pull-up input mode in GPIO mode. Whether it is pull-down or pull-up input mode needs to be determined by the second-level signal.

[0087] When the second level signal is a low level signal, controlling the voltage control submodule in the second driver module to output the first level signal means putting the I / O port into pull-up input mode; when the second level signal is a high level signal, controlling the voltage control submodule in the second driver module to output the first level signal means putting the I / O port into pull-down input mode.

[0088] Step 270: Read the fourth value of the second register connected to the second driver module, and determine the second detection result based on the fourth value.

[0089] In some implementations, step 270 includes the following steps.

[0090] (1) When the fourth value is the same as the third value, the second detection result is determined to be passed.

[0091] (2) When the fourth value is different from the third value, the second detection result is determined to be unsuccessful.

[0092] In some implementations, the second detection result is that the second register can still be controlled by the first register, or the second register is being controlled by an external strong pull-down voltage; the second detection result is that the second register cannot be controlled by the first register, but at this time the second register may be controlled by an external strong pull-up voltage.

[0093] Therefore, if the second test result is passed, it can be determined that the I / O port is in normal condition. However, the I / O port status cannot be determined solely based on the second test result being failed. It is necessary to combine the first test result for further determination.

[0094] Step 280: Determine whether the I / O port is normal based on the first detection result and the second detection result.

[0095] In some implementations, step 280 includes the following steps.

[0096] (1) When at least one of the first detection result and the second detection result is passed, the I / O port is determined to be normal.

[0097] (2) When both the first test result and the second test result are unsuccessful, the I / O port is determined to be damaged.

[0098] Taking a high-level signal as the first level signal and a low-level signal as an example, when both the first and second detection results are failed, the failure of the first detection result means that the resistor may be damaged, causing an open circuit or there is a strong external pull-down. The failure of the second detection result means that the resistor may be damaged, causing an open circuit or there is a strong external pull-up. Therefore, when both the first and second detection results are failed, the only possibility is that the resistor is damaged, causing an open circuit. At this time, it can be determined that the I / O port is damaged.

[0099] Because when the detection resistor is damaged, the value of the second register is only controlled by the level signal output by the voltage control submodule. In this application, the level signal output by the first drive module is reversed with the level signal output by the voltage control submodule, and the detection results of the high-level signal and low-level signal output by the first drive module are detected respectively. The influence of external strong pull-up and strong pull-down on I / O port detection is eliminated by combining the two detection results. Thus, even if the chip is not removed and the chip is still connected to the external device, the chip's I / O port can still be detected, saving detection time and detection cost.

[0100] In some implementations, the chip includes multiple I / O ports, so each I / O port needs to be detected. Based on this, step 210 includes the following steps.

[0101] (1) Configure the Nth I / O port as a general input / output mode; where the initial state of N is 1.

[0102] Based on step (1) above, the method also includes the following steps.

[0103] (2) Write a first value into the first register in the I / O port bit circuit of the Nth I / O port, so that the first driving module connected to the first register outputs a first level signal to the second driving module; (3) Control the voltage control submodule in the second drive module to output a second level signal; (4) Read the second value of the second register connected to the second driver module, and determine the first detection result based on the second value; (5) Write a third value into the first register in the I / O port bit circuit of the Nth I / O port, so that the first driving module connected to the first register outputs a second level signal to the second driving module; (6) Control the voltage control submodule in the second drive module to output a first level signal; (7) Read the fourth value of the second register connected to the second driving module, and determine the second detection result based on the fourth value; (8) Determine whether the Nth I / O port is normal based on the first detection result and the second detection result.

[0104] (9) If the first detection result and the second detection result determine that the Nth I / O port is normal, make N=N+1, and return to the execution step to configure the Nth I / O port as a general input / output mode.

[0105] (10) When the Nth I / O port is determined to be damaged based on the first detection result and the second detection result, the information of the Nth I / O port is recorded, N=N+1, and the execution step is returned to configure the Nth I / O port as a general input / output mode.

[0106] In some implementations, step (9) includes the following steps.

[0107] If the Nth I / O port is determined to be normal based on the first detection result and the second detection result, determine whether N is equal to Nmax. If N is not equal to Nmax, set N=N+1 and return to the execution step to configure the Nth I / O port as a general input / output mode; if N is equal to Nmax, end the process.

[0108] In some implementations, step (10) includes the following steps.

[0109] When the Nth I / O port is determined to be damaged based on the first detection result and the second detection result, the information of the Nth I / O port is recorded, and it is determined whether N is equal to Nmax. If N is not equal to Nmax, N=N+1, and the process returns to the execution step to configure the Nth I / O port as a general input / output mode; if N is equal to Nmax, the process ends.

[0110] In some implementations, the value of Nmax is equal to the number of all I / O ports in the chip that need to be detected.

[0111] Using the above method, all I / O ports in the chip can be tested through software without disassembling the chip, saving testing time and costs.

[0112] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a chip I / O port detection device provided in an embodiment of this application. Figure 4 As shown, the chip I / O port detection device 300 includes: a configuration unit 310, a first writing unit 320, a first control unit 330, a first reading unit 340, a second writing unit 350, a second control unit 360, a second reading unit 370, and a determination unit 380.

[0113] Configuration unit 310 is used to configure the I / O port as a general-purpose input / output mode; The first writing unit 320 is used to write a first value into a first register so that the first driving module connected to the first register outputs a first level signal to the second driving module. The first control unit 330 is used to control the voltage control submodule in the second drive module to output a second level signal; The first reading unit 340 is used to read the second value of the second register connected to the second driving module and determine the first detection result based on the second value. The second writing unit 350 is used to write a third value into the first register so that the first driving module connected to the first register outputs a second level signal to the second driving module. The second control unit 360 is used to control the voltage control submodule in the second drive module to output a first level signal; The second reading unit 370 is used to read the fourth value of the second register connected to the second driving module, and determine the second detection result based on the fourth value; The determining unit 380 is used to determine whether the I / O port is normal based on the first detection result and the second detection result.

[0114] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example... Figure 5 As shown, the electronic device 400 includes: one or more processors 410 and a memory 420. Figure 5 Take a processor 410 as an example.

[0115] In some implementations, the processor 410 and the memory 420 may be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0116] In some implementations, the processor 410 is configured to: configure the I / O port as a general-purpose input / output (GPIO) mode; write a first value to a first register to cause a first driver module connected to the first register to output a first-level signal to a second driver module; control a voltage control submodule in the second driver module to output a second-level signal; read a second value from a second register connected to the second driver module and determine a first detection result based on the second value; write a third value to the first register to cause the first driver module connected to the first register to output a second-level signal to the second driver module; control a voltage control submodule in the second driver module to output a first-level signal; read a fourth value from a second register connected to the second driver module and determine a second detection result based on the fourth value; and determine whether the I / O port is functioning correctly based on the first detection result and the second detection result.

[0117] In some implementations, memory 420 serves as a non-volatile computer-readable storage medium, used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules of the detection method in the embodiments of this application. Processor 410 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions, and modules stored in memory 420, thereby implementing the chip I / O port detection method of the above-described method embodiments.

[0118] In some embodiments, memory 420 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; and the data storage area may store data created based on the use of the electronic device. Furthermore, memory 420 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 420 may optionally include memory remotely located relative to processor 410, and these remote memories may be connected to the controller via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0119] In some implementations, one or more modules are stored in memory 420. When executed by one or more processors 410, they perform the chip I / O port detection method in any of the above method embodiments, for example, performing the method described above. Figure 3 Steps 210 to 280 in the method.

[0120] Please refer to Figure 6 , Figure 6This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. The computer-readable storage medium 500 stores program code 510, which can be called by a processor to execute the chip I / O port detection method described in the above method embodiments.

[0121] The computer-readable storage medium 500 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium 500 has storage space for program code that performs any of the method steps of the control method described above. This program code can be read from or written to one or more computer program products. The program code may, for example, be compressed in a suitable form.

[0122] This application provides a chip I / O port detection method, apparatus, electronic device, and storage medium. The method includes: configuring the I / O port to a general-purpose input / output (GPIO) mode; writing a first value to a first register to cause a first driver module connected to the first register to output a first-level signal to a second driver module; controlling a voltage control submodule in the second driver module to output a second-level signal; reading a second value from a second register connected to the second driver module and determining a first detection result based on the second value; writing a third value to the first register to cause the first driver module connected to the first register to output a second-level signal to the second driver module; controlling the voltage control submodule in the second driver module to output the first-level signal; reading a fourth value from the second register connected to the second driver module and determining a second detection result based on the fourth value; and determining whether the I / O port is normal based on the first detection result and the second detection result. This application configures the I / O port to GPIO mode. By configuring the value of the first register and the output level of the voltage control submodule, the state of the I / O port can be determined by reading the value of the second register. This eliminates the need to remove the chip for testing and allows for rapid testing of the I / O ports on the chip directly through software, reducing testing time and costs.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip I / O port detection method, characterized in that, The method comprises: configuring an I / O port as a general input and output mode; writing a first value into a first register to make a first driving module connected to the first register output a first level signal to a second driving module; controlling a voltage control submodule in the second driving module to output a second level signal; reading a second value of a second register connected to the second driving module, and determining a first detection result according to the second value; writing a third value into the first register to make the first driving module connected to the first register output a second level signal to the second driving module; controlling the voltage control submodule in the second driving module to output a first level signal; reading a fourth value of the second register connected to the second driving module, and determining a second detection result according to the fourth value; determining whether the I / O port is normal according to the first detection result and the second detection result.

2. The method of claim 1, wherein, The method comprises: when the second value is the same as the first value, determining that the first detection result is passed; when the second value is different from the first value, determining that the first detection result is failed.

3. The method of claim 2, wherein, The method comprises: when the fourth value is the same as the third value, determining that the second detection result is passed; when the fourth value is different from the third value, determining that the second detection result is failed.

4. The method of claim 3, wherein, The method comprises: when at least one of the first detection result and the second detection result is passed, determining that the I / O port is normal; when both the first detection result and the second detection result are failed, determining that the I / O port is damaged.

5. The method of claim 1, wherein, The second driving module comprises a detection resistor, a first end of the detection resistor is connected to the voltage control submodule, and a second end of the detection resistor is connected to an I / O pin and the first driving module; when the detection resistor is damaged to cause an open circuit, the value of the second register is controlled by the level signal output by the voltage control submodule; when the detection resistor is normal and the I / O pin does not receive an external voltage, the value of the second register is controlled by the level signal output by the first driving module to the second driving module; when the detection resistor is normal and the I / O pin receives an external voltage, the value of the second register is controlled by the external voltage.

6. The method of claim 1, wherein, The method comprises: controlling a first switch in the voltage control submodule to be turned on and a second switch to be turned off, so that the second register is connected to a first voltage source; The method comprises: controlling the first switch in the voltage control submodule to be turned off and the second switch to be turned on, so that the second register is connected to a second voltage source.

7. The method according to any one of claims 1 to 6, characterized in that, The method comprises: configuring the Nth I / O port as a general input / output mode; wherein the initial state of N is 1; The method further comprises: when it is determined according to the first detection result and the second detection result that the Nth I / O port is normal, setting N=N+1, and returning to the step of configuring the Nth I / O port as a general input / output mode; when it is determined according to the first detection result and the second detection result that the Nth I / O port is damaged, recording information of the Nth I / O port, setting N=N+1, and returning to the step of configuring the Nth I / O port as a general input / output mode.

8. A chip I / O port detection apparatus, characterized by comprising: The device comprises: a configuration unit configured to configure an I / O port as a general input / output mode; a first writing unit configured to write a first value into a first register, so that a first driving module connected to the first register outputs a first level signal to a second driving module; a first control unit configured to control a voltage control submodule in the second driving module to output a second level signal; a first reading unit configured to read a second value of a second register connected to the second driving module, and determine a first detection result according to the second value; a second writing unit configured to write a third value into the first register, so that the first driving module connected to the first register outputs a second level signal to the second driving module; a second control unit configured to control the voltage control submodule in the second driving module to output a first level signal; a second reading unit configured to read a fourth value of the second register connected to the second driving module, and determine a second detection result according to the fourth value; a determination unit configured to determine whether the I / O port is normal according to the first detection result and the second detection result.

9. An electronic device, comprising: The electronic device comprises: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the chip I / O port detection method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores an executable program, and the executable program is executed by the processor to implement the chip I / O port detection method according to any one of claims 1-7.

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