Integrated circuit for battery pack and open line detection system and method

Abstract

The invention discloses an integrated circuit, an open line detection system and a method. The integrated circuit comprises a first terminal for receiving power supply voltage, a first battery terminal coupled to the negative electrode of a first battery through a first connecting line, second to (n + 1) th battery terminals sequentially coupled to the positive electrodes of first to n batteries through second to (n + 1) th connecting lines, and a second terminal coupled to a reference ground, the first switch is coupled between the first battery terminal and the second terminal, the second switch to the (n + 1) th switch are respectively coupled in parallel with the first battery to the nth battery, and the (n + 2) th switch is coupled between the first terminal and the (n + 1) th battery terminal. In response to an open line detection mode, the first to (n + 2) th switches are sequentially turned on in a preset order, and the sampling unit samples voltages across the switches that have been turned on within the interval of sequential turn-on. And the logic storage unit determines the opening condition of the n + 1 connecting lines based on the voltage obtained by current sampling and the voltage obtained by previous sampling.

Description

TECHNICAL FIELD

[0001] The present application relates to an electronic circuit, in particular, to an integrated circuit for a battery pack, an open line detection system and a method for line connection detection between the battery pack and the integrated circuit. BACKGROUND

[0002] A high voltage battery pack usually includes a large number of single cells connected in series to achieve a required voltage level. Each single cell needs to be connected with a battery management integrated circuit to achieve functions such as battery balancing, voltage sampling, etc.

[0003] Since there are multiple line connections between the high voltage battery pack and the battery management integrated circuit, it is necessary to detect whether the connection of the multiple lines between each single cell in the high voltage battery pack and the battery management integrated circuit is reliable, i.e., whether a line is in an open line state. SUMMARY

[0004] To solve one or more problems in the prior art, the purpose of the present application is to provide an integrated circuit for a battery pack, an open line detection system and a method for detecting the line state connected with No. 1 to No. n batteries in the battery pack.

[0005] According to one embodiment of the present application, an integrated circuit for a battery pack is provided. The integrated circuit includes: a first terminal connected to receive a supply voltage; a first battery terminal coupled to a negative electrode of a No. 1 battery in a battery pack via a first connection line; second to (n+1)th battery terminals coupled to positive electrodes of No. 1 to No. n batteries connected in series in the battery pack via second to (n+1)th connection lines, respectively; a second terminal connected to be coupled to a reference ground; a first switch coupled between the first battery terminal and the second terminal; second to (n+1)th switches coupled in parallel with the No. 1 to No. n batteries, respectively; an (n+2)th switch coupled between the first terminal and the (n+1)th battery terminal; a sampling unit, in response to an open line detection mode, the first to (n+2)th switches are sequentially turned on in a preset order, and the voltage across the switch that has performed the on operation in the interval of the sequential on is sampled; and a logic storage unit, based on the voltage across the switch obtained by the current sampling and the voltage across the switch obtained by the previous sampling, determines the open line condition of the n+1 connection lines.

[0006] According to another embodiment of the present application, an open line detection system for detecting the line state connected with No. 1 to No. n batteries in a battery pack is also provided. The open line detection system includes the integrated circuit as described above and a system controller. The system controller communicates with the integrated circuit and receives an open line state alarm.

[0007] According to still another embodiment of the present application, a method for detecting the connection line state of an integrated circuit and a battery pack is also provided. The method includes connecting a first terminal of the integrated circuit to receive a supply voltage; coupling a first battery terminal of the integrated circuit to a negative pole of a first battery through a first connection line; coupling second to nth+1 battery terminals of the integrated circuit to positive poles of first to nth batteries, respectively, through second to nth+1 connection lines; coupling a second terminal of the integrated circuit to a reference ground; coupling a first switch between the first battery terminal and the second terminal of the integrated circuit; coupling second to nth+1 switches in parallel with the first to nth batteries, respectively; coupling an nth+2 switch between the first terminal and the nth+1 battery terminal of the integrated circuit; in response to an open line detection mode, sequentially turning on the first to nth+2 switches in a preset order, sampling a voltage across a switch that has been turned on in an interval between sequential turn-on; and determining an open line state of the n+1 connection lines based on the voltage across the switch sampled currently and the voltage across the switch sampled previously. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 a circuit schematic diagram of an open line detection system according to an embodiment of the present application;

[0009] Figure 2 a circuit diagram of an open line detection system according to another embodiment of the present application;

[0010] Figure 3 a flowchart of a method for detecting a connection line state of an integrated circuit and a battery pack according to an embodiment of the present application;

[0011] Figure 4 a circuit diagram of an open line detection system according to an embodiment of the present application;

[0012] Figure 5 a circuit diagram of an open line detection system according to an embodiment of the present application; Figure 4 a working waveform diagram of the open line detection system shown. DETAILED DESCRIPTION

[0013] Specific embodiments of the present application will now be described in detail with reference to the drawings. As stated above, the embodiments described herein are only given by way of example and are not used to limit the present application. For a thorough understanding of the present application, numerous specific details are set forth in the following description. However, it should be apparent to one of ordinary skill in the art that the present application can be practiced without the specific details set forth in the following description. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring aspects of the present application.

[0014] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0015] Figure 1 This is a circuit block diagram of an open-wire detection system according to an embodiment of the present invention. Figure 1 As shown, the open-circuit detection system includes a battery pack 101, an integrated circuit 103, and a system controller 104. The battery pack 101 has a plurality of individual cells connected in series between the positive terminal and the negative terminal of the battery pack.

[0016] exist Figure 1 In the illustrated embodiment, the battery pack 101 includes n batteries connected in series: battery 1, battery 2, ..., battery n, where n is an integer greater than or equal to 2. When the battery pack 101 operates as a high-voltage battery pack, n can be an integer greater than 30.

[0017] exist Figure 1 In the illustrated embodiment, integrated circuit 103 has multiple terminals, a switch group 110, a sampling unit 120, a logic storage unit 130, and an interface circuit 140. The multiple terminals include a first terminal Vin, a second terminal GND, and first to (n+1)th battery terminals C1 to Cn+1. The first terminal Vin is configured to receive the supply voltage of integrated circuit 103. The second terminal GND is configured to be coupled to the reference ground of integrated circuit 103. The first battery terminal C1 is coupled to the negative terminal of battery number 1 in battery pack 101 via a first connection line Line 1. The second to (n+1)th battery terminals C2 to Cn+1 are sequentially coupled to the positive terminals of batteries number 1 to n in battery pack 101 via second to (n+1) connection lines (Line 2 to Line n+1).

[0018] Continue asFigure 1 As shown, switch group 110 includes n+2 switches S1 to Sn+2, configured to perform an open-line detection function. The first switch S1 is coupled between the first battery terminal C1 and the second terminal GND. The (n+2)th switch (Sn+2) is coupled between the first terminal Vin and the (n+1)th battery terminal Cn+1. The second to (n+1)th switches (S2 to Sn+1) are connected in parallel with batteries 1 to n, respectively. In a further embodiment, the second to (n+1)th switches (S2 to Sn+1) are n-1 equalization switches in integrated circuit 103 for battery equalization, ensuring that the voltages of the individual cells in battery pack 101 are substantially equal.

[0019] The sampling unit 120 is connected to each individual battery cell in the battery pack 101 via n battery terminals C1 to Cn+1, and is used to collect the voltage information of each individual battery cell. Specifically, in response to the open-line detection mode, the first to the (n+2)th switches (S1 to Sn+2) in the switch group 110 are turned on sequentially in a preset order, and the voltage across the switches that have been turned on is sampled during the interval between the sequential turn-on operations. In one embodiment, the sampling unit 120 samples the voltage across the switches that have been turned on after a preset delay TD.

[0020] In response to the open-line detection requirement, logic storage unit 130 provides open-line detection control signal 32 to control the n+2 switches in switch group 110 to be turned on sequentially in a preset order. Logic storage unit 130 determines the open-line status of n+1 connecting lines (Line 1 to Line n+1) based on the voltage across the switch obtained by the current sampling and the voltage across the switch obtained by the previous sampling.

[0021] In one embodiment, if the difference between the voltage across the switch obtained by the current sampling and the voltage across the switch obtained by the previous sampling is greater than a threshold voltage Vth, the connection line of the corresponding switch is indicated as open.

[0022] exist Figure 1 In the illustrated embodiment, integrated circuit 103 further includes a digital-to-analog converter (ADC). The ADC is configured to convert the voltage across the currently sampled switch into a digital voltage signal 31 and transmit it to logic memory unit 130 in a time-division multiplexing manner.

[0023] In one embodiment, the logic storage unit 130 is further configured to store a digital signal of the voltage across the switch previously sampled. In another embodiment, the logic storage unit 130 is further configured to store a status bit to indicate the status of the n+1 connection lines.

[0024] like Figure 1As shown, the logic storage unit 130 is coupled to the system controller 104 via the interface circuit 140. The system controller 104 communicates with the integrated circuit 103 to receive voltage information stored in the logic storage unit 130 and line status information of n connection lines (Line 1 to Line n+1) via the interface circuit 140, and provides corresponding open line status alarms.

[0025] In one embodiment, the system controller 104 is further configured to receive and monitor the voltage of each individual battery cell from the logic storage unit 130, determine the state of each individual battery cell in the entire battery pack 101, and automatically provide equalization control signals to n-1 equalization switches (switches S2 to Sn+1 from the 2nd to the (n+1th)th) to meet equalization requirements. This controls the transfer of energy from the individual battery cell with the highest voltage in the battery pack 101 to other batteries in the battery pack 101, or controls the transfer of energy from other batteries in the battery pack 101 to the individual battery cell with the lowest voltage in the battery pack 101, until the voltages of all individual batteries are equalized. When an equalization switch is turned on, equalization begins; when the equalization switch is turned off, equalization stops. In another embodiment, the logic storage unit 130 can determine the state of each individual battery cell in the entire battery pack 101 based on its voltage, and automatically provide equalization control signals to n-1 equalization switches (switches S2 to Sn+1 from the 2nd to the (n+1th)th)th) equalization requirements.

[0026] In one embodiment, an isolation circuit is also coupled between the system controller 104 and the integrated circuit 103. This isolation circuit may include an optocoupler, a transformer, a capacitive isolation device, or any other suitable electrical isolation device.

[0027] Figure 2 This is a circuit block diagram of an open-wire detection system according to another embodiment of the present invention. Figure 1 Compared to the open wire detection system shown, Figure 2 The open-circuit detection system shown further includes a connection circuit 102.

[0028] like Figure 2 As shown, the connection circuit 102 includes n+2 RC circuits with identical or similar structures. Each RC circuit includes a resistor 20 and a capacitor 21. Each RC circuit is connected to the first terminal Vin, one of the first to n+1th battery terminals C1 to Cn+2, and is connected to the positive or negative terminal of the battery in the battery pack 101.

[0029] exist Figure 2 In the illustrated embodiment, the connection circuit 102 further includes diodes D1 and D2. For example... Figure 2As shown, the anode of diode D1 is coupled to the (n+1)th battery terminal Cn+1, and the cathode of diode D1 is coupled to the first terminal Vin. When diode D1 is forward biased, the connection line Line Vin, which indicates the connection to the first terminal Vin, is in an open state. Figure 2 As shown, the anode of diode D2 is coupled to the second terminal GND, and the cathode is coupled to the first battery terminal C1. When diode D2 is forward biased, the line Line GND connected to the second terminal GND is in an open state.

[0030] Furthermore, in Figure 2 In the illustrated embodiment, switch group 110 includes a first switch S1 to a (n+2)th switch Sn+2. Switch group 110 is configured to execute a corresponding open-line detection function in response to an open-line detection control signal 32 provided by logic storage unit 130A, controlling the first switch S1 to the (n+2)th switch Sn+2 to be turned on sequentially in a preset order. Sampling unit 120 samples the voltage across the switches that have been turned on among the first switches S1 to the (n+2)th switch Sn+2 during the intervals between their sequential turn-on.

[0031] Switch group 111 includes second switches S2 to (n+1)th switches Sn+1 as n-1 equalization switches. Switch group 111 is configured to perform corresponding equalization control in response to equalization control signal 35 provided by logic storage unit 130A. In one embodiment, when the open-line detection mode is not enabled and the equalization requirement of battery pack 101 occurs, the n-1 equalization switches in switch group 111 cooperate with the energy conversion unit (not shown) of integrated circuit 103A to perform battery equalization function. This energy conversion unit can perform boost or buck functions.

[0032] According to an embodiment of the present invention, a method for detecting the line status of a connection line connecting an integrated circuit to batteries 1 to n in a battery pack is disclosed. The method includes the following steps: connecting a first terminal of the integrated circuit to receive a supply voltage; coupling the first battery terminal of the integrated circuit to the negative terminal of battery 1 via a first connection line; sequentially coupling the second to (n+1)th battery terminals of the integrated circuit to the positive terminals of batteries 1 to n via the second to (n+1)th connection lines respectively; coupling the second terminal of the integrated circuit to a reference ground; coupling a first switch between the first battery terminal and the second terminal of the integrated circuit; coupling the second to (n+1)th switches in parallel with batteries 1 to n respectively; coupling the (n+2)th switch between the first terminal and the (n+1)th battery terminal of the integrated circuit; responding to an open-line detection mode, sequentially turning on the first to (n+2)th switches in a preset order, sampling the voltage across the switches that have already performed a conducting operation during the interval between sequential turning on; and determining the open-line status of the (n+1)th connection line based on the currently sampled voltage across the switch and the previously sampled voltage across the switch.

[0033] Specifically, Figure 3 This is a flowchart of a method 300 for detecting the circuit status of an integrated circuit connected to a battery pack according to an embodiment of the present invention. Method 300 includes steps 301 to 312. The following is in conjunction with… Figure 2 To describe Figure 3 The example shown.

[0034] In step 301, in response to the open-line detection mode, the integrated circuit begins to perform open-line detection on the n+1 connection lines (Line1 to Line n+1) connected to the battery pack. The battery pack includes batteries numbered 1 to n connected in series.

[0035] In step 302, the open-line detection starts from i=1, that is, the first connection line Line 1 is detected. Then, in step 303, the first switch S1, coupled between the first battery terminal C1 and the second terminal GND of the integrated circuit, is turned on to... Figure 2 The voltage across the capacitor 21, which is connected in parallel with the first switch S1, is discharged through the first switch S1. In one embodiment, the capacitor 21 may be a parasitic capacitance connected in parallel with the first switch S1.

[0036] In step 304, a preset delay TD occurs after the first switch S1 is turned off. During this preset delay TD, if the first connection line Line 1 is not disconnected, battery 1 will recharge capacitor 21.

[0037] In step 305, the sampling unit samples the voltage VS1 across the first switch S1 at a preset delay TD.

[0038] In step 306, i = i + 1, that is, the first connecting line Line 1 and the second connecting line Line 2 are detected. Then, in step 307, the switch Si is turned on.

[0039] In step 308, a preset delay TD is performed after the i-th switch Si is turned off. In step 309, the sampling unit samples the voltages VS1 to VSi across the first switch S1 to the i-th switch Si during the preset delay TD, that is, samples the voltages across all switches that have performed conduction operation.

[0040] In step 310, if the difference between the voltage across the switch obtained by the current sampling and the voltage across the switch obtained by the previous sampling exceeds the threshold voltage Vth, then proceed to step 311 and mark the connection line of the corresponding switch as open (for example, marked as OPW).

[0041] If the difference between the voltage across the switch obtained by the current sampling and the voltage across the switch obtained by the previous sampling does not exceed the threshold voltage Vth, then proceed to step 312 and repeat steps 306 to 310 until all n+2 switches have performed conduction in a preset sequence. Finally, the entire open-circuit detection process ends.

[0042] Figure 4 This is a circuit diagram of a wire break detection system according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the open-circuit detection system includes a battery pack 101A, a connection circuit 102A, and an integrated circuit 103A. The battery pack 101A includes ten batteries connected in series: battery number 1, battery number 2, ..., battery number 10. It should be noted that... Figure 4 The number of individual cells in the battery pack shown is merely exemplary and not intended to limit the invention. In other embodiments, the battery pack may include dozens of individual cells, such as 32, connected in series.

[0043] exist Figure 4 In the illustrated embodiment, integrated circuit 103A has multiple terminals, a switch group 110A, a sampling unit 120, and a logic storage unit 130. The multiple terminals include a first terminal Vin, a second terminal GND, and first to eleventh battery terminals C1 to C11.

[0044] like Figure 4As shown, the first terminal Vin is configured to receive the supply voltage of integrated circuit 103A. The second terminal GND is configured to be coupled to the reference ground of integrated circuit 103A. The first battery terminal C1 is coupled to the negative terminal of battery No. 1 in battery pack 101A via the first connection line Line1. The second to eleventh battery terminals C2 to C11 are respectively coupled to the positive terminals of batteries No. 1 to No. 10 in battery pack 101A via the second to eleventh connection lines (Line 2 to Line 11). The connection circuit 102A includes 12 RC circuits, diode D1, and diode D2, and the connection method is as follows. Figure 4 As shown.

[0045] Continue as Figure 4 As shown, switch group 110A includes 12 switches S1 to S12, configured to perform an open-circuit detection function. The first switch S1 is coupled between the first battery terminal C1 and the second terminal GND. The 12th switch S12 is coupled between the first terminal Vin and the 11th battery terminal C11. The second to 11th switches (S2 to S11) are respectively connected in parallel with batteries numbered 1 to n. In a further embodiment, the second to 11th switches (S2 to S11) constitute switch group 111A, configured as 10 equalization switches in integrated circuit 103A for battery equalization, so that the voltages of the individual cells in battery pack 101A are substantially equal.

[0046] The sampling unit 120 is connected to each individual battery cell in the battery pack 101A via 11 battery terminals C1 to C11, and is used to collect voltage information of each individual battery cell. Specifically, in response to the open-line detection mode, the first to the 12th switches (S1 to S12) in the switch group 110A are turned on sequentially in a preset order, and the voltage across the switches that have been turned on is sampled during the interval between the sequential turn-on operations. In one embodiment, the sampling unit 120 samples the voltage across the switches that have been turned on after a preset delay TD.

[0047] In response to the open-line detection mode, logic storage unit 130A provides an open-line detection control signal 32 to control the 12 switches in switch group 110A to be turned on sequentially in a preset order. Logic storage unit 130A determines the open-line status of the 11 connection lines (Line 1 to Line 11) based on the voltage across the currently sampled switch and the voltage across the previously sampled switch. In one embodiment, if the difference between the voltage across the currently sampled switch and the voltage across the previously sampled switch is greater than a threshold voltage Vth, the connection line of the corresponding switch is indicated as open.

[0048] Figure 5 According to an embodiment of the present invention Figure 4The diagram shows the operating waveforms of the open-circuit detection system. Figure 5 As shown, the 12 switches S1 to S12 of switch group 110A are sequentially turned on. During the intervals between sequential turns, the voltage across the switches that have already performed the turning operation is sampled. After each switch turns on, the sampling unit samples the voltage across the switches that have performed the turning operation after a preset delay TD. For example, after switch S7 turns on, voltages VS1 to VS7 are sampled.

[0049] Continue as Figure 5 The diagram shows the voltages VS1 to VS12 across 12 switches S1 to S12. The currently sampled voltage across a switch is compared with the previously sampled voltage. If the difference between the currently sampled voltage and the previously sampled voltage is greater than a threshold voltage Vth, the corresponding switch's connection is indicated as open. In one embodiment, the threshold voltage Vth is a value close to 0.

[0050] exist Figure 4 and Figure 5 In the illustrated embodiment, according to the open-wire detection system and method of the present invention, the open-wire states of connecting lines Line 1 to Line 3, Line 5 to Line 7, and Line 9 to Line 11 are detected and marked respectively. Figure 5 middle.

[0051] In the specification or claims, related terms such as "first" and "second" may simply distinguish one entity or action from another, without necessarily implying any relationship or order between these entities or actions. Numerical orders such as "first," "second," and "third" merely refer to different individuals among a plurality and do not imply any order or sequence, unless specifically defined by the language of the claims.

[0052] The order of the text in any claim does not imply that the processing steps must be performed in a provisional or logical order according to such an order, unless specifically specified in the language of the claim. Without departing from the scope of the invention, these processing steps may be interchanged in any order, provided that such interchange does not contradict the language of the claim and does not result in logical absurdity.

[0053] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. An integrated circuit for a battery pack, comprising: a first terminal connected to receive a supply voltage; a first battery terminal coupled to a negative terminal of a first battery in a battery pack via a first connecting line; second to nth+1 battery terminals coupled to positive terminals of second to nth batteries in the battery pack via second to nth+1 connecting lines, respectively; a second terminal connected to be coupled to a reference ground; a first switch coupled between the first battery terminal and the second terminal; second to nth+1 switches coupled in parallel with the first to nth batteries, respectively; an nth+2 switch coupled between the first terminal and the nth+1 battery terminal; a sampling unit, in response to an open line detection mode, the first to nth+2 switches are sequentially turned on in a preset order, the sampling unit samples a voltage across a switch that has been turned on in a time interval between sequential turn-on of the first to nth+2 switches; and a logic storage unit, based on a current sampled voltage across the switch and a previous sampled voltage across the switch, determines an open line condition of the n+1 connecting lines.

2. The integrated circuit of claim 1, wherein in response to a battery equalization mode, the second to nth+1 switches are configured as n-1 equalization switches for equalizing the battery pack.

3. The integrated circuit of claim 1, wherein after each switch is turned on, the sampling unit samples the voltage across the switch that has been turned on after a preset delay.

4. The integrated circuit of claim 1, wherein: if a difference between the current sampled voltage across the switch and the previous sampled voltage across the switch is greater than a threshold voltage, the corresponding connecting line of the switch is indicated as an open line condition.

5. The integrated circuit of claim 1, further comprising an analog-to-digital conversion circuit configured to convert the current sampled voltage across the switch into a voltage digital signal and transmit the voltage digital signal to the logic storage unit.

6. The integrated circuit of claim 5, wherein the logic storage unit is configured to store the previous sampled voltage across the switch.

7. The integrated circuit of claim 5, wherein the logic storage unit is further configured to store a status bit to indicate a status of the n+1 connecting lines.

8. An open line detection system for detecting a status of n+1 connecting lines connected to first to nth batteries in a battery pack, the open line detection system comprising: the integrated circuit of any one of claims 1 to 7; and a system controller in communication with the integrated circuit to receive an open line status alarm.

9. The open line detection system of claim 8, further comprising: a connection circuit comprising n+2 RC circuits, each RC circuit connected to the first terminal and one of the first to nth+1 battery terminals.

10. A method for detecting a status of connecting lines of an integrated circuit connected to first to nth batteries in a battery pack, the method comprising: connecting a first terminal of the integrated circuit to receive a supply voltage; coupling a first battery terminal of the integrated circuit to a negative terminal of a first battery via a first connecting line; ​ ​ coupling the second to the n+1th battery terminals of the integrated circuit to the anodes of the first to the nth batteries via the second to the n+1th connecting lines in sequence respectively; coupling the second terminal of the integrated circuit to the reference ground; coupling the first switch between the first battery terminal and the second terminal of the integrated circuit; coupling the second to the n+1th switches in parallel to the first to the n-th batteries respectively; coupling the n+2th switch between the first terminal and the n+1th battery terminal of the integrated circuit; in response to the open line detection mode, sequentially turning on the first to the n+2th switches in a preset order, and sampling the voltage across the switch which has been turned on in the interval of sequential turning on; and based on the voltage across the switch obtained by the current sampling and the voltage across the switch obtained by the previous sampling, determining the open line condition of the n+1 connecting lines.

11. The method of claim 10, wherein in response to the battery equalization mode, the second to the n+1th switches are configured as n-1 equalization switches for equalizing the battery pack.

12. The method of claim 10, wherein: after each switch is turned on, sampling the voltage across the switch which has been turned on after a preset delay.

13. The method of claim 10, wherein: if the difference between the voltage across the switch obtained by the current sampling and the voltage across the switch obtained by the previous sampling is greater than a threshold voltage, the connecting line of the corresponding switch is indicated as the open line state.

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