Circuit test system

Abstract

The invention provides a circuit test system, comprising: a first test circuit comprising a first output terminal coupled to a first scan control terminal of a first target circuit, the first test circuit being configured to receive a test mode signal and a scan enable signal, generating a first control signal according to the test mode signal and the scan enable signal; wherein the first target circuit operates in one of a normal mode, a scan shift mode and a scan capture mode according to the first control signal.

Description

Technical Field

[0001] This invention relates to circuit testing systems, and more particularly to circuit testing systems that allow the scanning actions of different target circuits to be tested to be controlled separately. Background Technology

[0002] With the development of technology, circuit structures are becoming increasingly complex. In order to test each component in a circuit more accurately, a scan chain is usually used to perform scan testing. However, under this mechanism, the scan control terminals of many circuits under test are connected together and receive the same scan enable signal. This makes it impossible to flexibly control the scan of the circuit under test, which reduces the controllability of the circuit and leads to a decrease in test coverage. Summary of the Invention

[0003] Therefore, one objective of this invention is to provide a circuit testing system that allows target circuits to be scanned and tested separately.

[0004] An embodiment of the present invention discloses a circuit testing system, comprising: a first test circuit, including a first output terminal, the first output terminal being coupled to a first scan control terminal of a first target circuit, the first test circuit being used to receive a test mode signal and a scan enable signal, and to generate a first control signal according to the test mode signal and the scan enable signal; wherein the first target circuit operates in one of a normal mode, a scan shift mode and a scan capture mode according to the first control signal.

[0005] According to the foregoing embodiments, the scanning control terminals of different target circuits can be controlled separately, allowing different target circuits to operate in the required modes. This can improve the problem in the prior art where the target circuit can only exist in the scanning shift mode or the scanning capture mode at the same time, resulting in poor controllability. Attached Figure Description

[0006] Figure 1 This is a block diagram of a circuit testing system according to an embodiment of the present invention.

[0007] Figure 2 An embodiment of the present invention is shown. Figure 1 The circuit diagram shown is a detailed circuit diagram of the circuit testing system.

[0008] Figure 3 This is a block diagram of a circuit testing system according to an embodiment of the present invention.

[0009] Figure 4 An embodiment of the present invention is shown. Figure 3 The circuit diagram shown is a detailed circuit diagram of the circuit testing system.

[0010] Figure 5 According to an embodiment of the present invention, when Figure 4 The diagram illustrates the operation of the first, second, and third registers in the scan shift mode.

[0011] Figure 6 An application according to an embodiment of the present invention is shown. Figures 1 to 5 The method and circuit diagram of the electrical architecture.

[0012] Figure 7 This is a flowchart illustrating a circuit testing method according to an embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures:

[0014] 100, 300: Circuit testing system; 401, 601: ICG circuit; 403: Compressor

[0015] 600: Circuit; 603: Logic Combination; TAC_1: First Target Circuit

[0016] T_C1: First scan control terminal; TS_1: First test circuit; T_O1: First output terminal

[0017] TAC_2: Second target circuit; T_C2: Second scan control terminal; TS_2: Second test circuit.

[0018] T_O2: Second output terminal; T_O3: Third output terminal; MUX_1: First multiplexer

[0019] OR_1: First OR gate MUX_2: Second multiplexer OR_2: Second OR gate

[0020] Re_1: First register; Re_2: Second register; Re_3: Third register Detailed Implementation

[0021] The present invention will be described below through several embodiments. Please note that the terms "first," "second," and similar descriptions in the following description are only used to define different elements, parameters, data, signals, or steps, and are not intended to limit their order. For example, the first device and the second device may be devices with the same structure but different from each other.

[0022] Figure 1 A block diagram of a circuit testing system according to an embodiment of the present invention is shown. Figure 1As shown, the circuit testing system 100 includes a first test circuit TS_1. The first test circuit TS_1 includes a first output terminal T_O1. The first output terminal T_O1 is coupled to a first scan control terminal T_C1 of a first target circuit TAC_1. The first test circuit TS_1 receives a test mode signal TM and a scan enable signal SE, and generates a first control signal SC_1 based on the test mode signal TM and the scan enable signal SE. The first target circuit TAC_1 operates in one of three modes: a normal mode, a scan shift mode, and a scan capture mode, based on the first control signal SC_1. The test mode signal TM determines whether to enable the test mode, and the scan enable signal SE determines whether to use the scan shift mode or the scan capture mode in the test mode.

[0023] In one embodiment, the first target circuit TAC_1 performs its functions normally in normal mode. For example, if the first target circuit TAC_1 is a register, it performs a temporary storage function normally in normal mode; if it is a clock signal circuit, it performs a clock signal generation function normally in normal mode. In one embodiment, the first target circuit TAC_1 includes at least one test terminal. In scan-shift mode, the test terminal of the first target circuit TAC_1 receives a test pattern. In scan-capture mode, the test terminals of the first target circuit TAC_1 do not receive a test pattern but can receive other test signals. That is, in scan-capture mode, all test terminals of the first target circuit TAC_1 can receive any required test signal according to the test requirements, thereby improving circuit controllability and facilitating the capture of circuit defects. Detailed explanations regarding improved circuit controllability will be provided in the following embodiments.

[0024] Figure 1 The first test circuit TS_1 can be implemented by various circuits. Figure 2 An embodiment of the present invention is shown. Figure 1 The circuit diagram shown is a detailed circuit diagram of the circuit test system. Figure 2 In the embodiment, the first target circuit TAC_1 can represent all D flip-flops on the scan chain in the entire IC. For ease of explanation, it is described as a first register Re_1, which can be a D flip-flop. Figure 2 As shown, the D flip-flop includes an SE terminal (i.e., the aforementioned first scan control terminal T_C1) for receiving the first control signal SC_1. Furthermore, in Figure 2In one embodiment, the first test circuit TS_1 includes a first multiplexer MUX_1 and a first OR gate OR_1. The first multiplexer MUX_1 has the aforementioned first output terminal T_O1, and one of its first input terminals (input terminal labeled 0) receives a scan enable signal SE, and one of its selection input terminals receives a test mode signal. The output of the first OR gate OR_1 is coupled to a second input terminal (input terminal labeled 1) of the first multiplexer MUX_1. The first input terminal of the first OR gate OR_1 receives a first controllable value, and the second input terminal of the first OR gate OR_1 receives the scan enable signal SE. The first controllable value can be set to a desired value during the test. In one embodiment, the first controllable value is generated by a second register Re_2, which can also be implemented by a D flip-flop.

[0025] exist Figure 2 In this embodiment, if both the test mode signal TM and the scan enable signal SE are 0 (first logic value), the first target circuit TAC_1 operates in normal mode. If both the test mode signal TM and the scan enable signal SE are 1 (second logic value), the first target circuit TAC_1 operates in scan shift mode. If the test mode signal TM is 1 and the scan enable signal SE is 0, the first target circuit TAC_1 operates in scan capture mode, and whether its test terminal is activated can be determined by a first controllable value. In another embodiment, the values ​​of the first logic value and the second logic value can be interchanged, i.e., the first logic value is 1 and the second logic value is 0. In this case, the architecture of the test circuit can be adjusted accordingly, for example, by adding an inverter.

[0026] The circuit testing system provided by this invention is not limited to including only one test circuit. Figure 3 A block diagram of a circuit testing system according to an embodiment of the present invention is shown. Figure 3 As shown, the circuit test system 300, in addition to Figure 1 In addition to the first test circuit TS_1 shown, a second test circuit TS_2 is also included. The second test circuit TS_2 includes a second output terminal T_O2 coupled to a second target circuit TAC_2. The second output terminal T_O2 is coupled to a second scan control terminal of the second target circuit TAC_2. The second test circuit TS_2 receives a test mode signal TM and a scan enable signal SE, and generates a second control signal SC_2 based on the test mode signal TM and the scan enable signal SE. The second target circuit TAC_2 operates in one of the aforementioned normal mode, scan shift mode, and scan capture mode according to the second control signal SC_2. In one embodiment, the second target circuit TAC_2 may represent all the ICG (integrated clock gating) circuits in the entire IC.

[0027] Figure 3The first test circuit TS_1 and the second test circuit TS_2 can be implemented by various circuits. Figure 4 An embodiment of the present invention is shown. Figure 3 The circuit diagram shown is a detailed circuit diagram of the circuit test system. Figure 4 In the embodiment, the first target circuit TAC_1 is defined as follows: Figure 1 The first target circuit is TAC_1, but it is described using a first register Re_1, which can be implemented by a D flip-flop. For example... Figure 4 As shown, the D flip-flop includes an SE terminal (i.e., the aforementioned first scan control terminal T_C1) for receiving the first control signal SC_1. Furthermore, in Figure 4 In one embodiment, the first test circuit TS_1 includes a first multiplexer MUX_1 and a first OR gate OR_1. The first multiplexer MUX_1 has the aforementioned first output terminal T_O1, and one of its first input terminals (input terminal labeled 0) receives a scan enable signal SE, and one of its selection input terminals receives a test mode signal. The output of the first OR gate OR_1 is coupled to a second input terminal (input terminal labeled 1) of the first multiplexer MUX_1. The first input terminal of the first OR gate OR_1 receives a first controllable value, and the second input terminal of the first OR gate OR_1 receives the scan enable signal SE. The first controllable value can be set to a desired value during the test. In one embodiment, the first controllable value is generated by a second register Re_2, which can also be implemented by a D flip-flop.

[0028] exist Figure 4 In the embodiment, the meaning of the second target circuit TAC_2 is as follows: Figure 3 The second target circuit, TAC_2, is used, but it will be described using an ICG circuit 401. The ICG circuit 401 may include the E terminal, TE terminal, CLK terminal, and Q terminal as shown in the figure. The E terminal serves as the enable terminal, and the TE terminal is the aforementioned second scan control terminal TC_2, used to put the ICG circuit 401 into one of three modes: normal mode, scan shift mode, and scan capture mode. The CLK terminal is used to receive an external clock signal. The Q terminal is the output terminal of the ICG circuit 401.

[0029] In addition, Figure 4In one embodiment, the second test circuit TS_2 includes a second multiplexer MUX_2 and a second OR gate OR_2. The second multiplexer MUX_2 has the aforementioned second output terminal T_O2, and one of its first input terminals (input terminal labeled 0) receives a scan enable signal SE, and one of its selection input terminals receives a test mode signal. The output of the second OR gate OR_2 is coupled to a second input terminal (input terminal labeled 1) of the second multiplexer MUX_2. A first input terminal of the second OR gate OR_2 receives a second controllable value, and a second input terminal of the second OR gate OR_2 receives the scan enable signal SE. The second controllable value can be set to a desired value during the test. In one embodiment, the second controllable value is generated by a third register Re_3, which can also be implemented by a D flip-flop.

[0030] exist Figure 4 In this embodiment, if both the test mode signal TM and the scan enable signal SE are 0 (first logic value), the first register Re_1 and the ICG circuit 401 operate in normal mode. If both the test mode signal TM and the scan enable signal SE are 1 (second logic value), the first register Re_1 and the ICG circuit 401 operate in scan shift mode. If the test mode signal TM is 1 and the scan enable signal SE is 0, the first register Re_1 and the ICG circuit 401 operate in scan capture mode, and their test terminals can be activated by the first controllable value and the second controllable value, respectively. In another embodiment, the values ​​of the first logic value and the second logic value can be interchanged, i.e., the first logic value is 1 and the second logic value is 0. In this case, the architecture of the test circuit can be adjusted accordingly, for example, by adding an inverter. Figure 3 and Figure 4 The architecture allows for the free setting of the first and second controllable values, and since the scan control terminals of different target circuits are not connected to each other, the scan control terminals of different target circuits can be controlled separately, allowing different target circuits to operate in the required mode.

[0031] Please note that the circuit testing system provided by this invention is not limited to including two target circuits, nor is it limited to using the aforementioned test circuit architecture to test the target circuits. Figure 4 As shown, the test system 300 also includes a third output terminal T_O3, which receives the scan enable signal SE and transmits the scan enable signal SE to a circuit. Figure 4 In this embodiment, the circuit is a compressor 403, but it can be any circuit that needs to operate in scan shift mode or scan capture mode, such as an OCC (on-chip clock) circuit.

[0032] The aforementioned target circuit may be part of a scan chain. For example, in one embodiment, the first register Re_1, the second register Re_2, and the third register Re_3 belong to the same scan chain. Figure 5 It shows when Figure 4 The diagram illustrates the actions of registers Re_1, Re_2, and Re_3 in the scan-shift mode. Please also note that... Figure 5 In the example, for ease of explanation, Figure 4 Some components are not shown. For example... Figure 5 As shown, in scan-shift mode, the SI terminal (i.e., the aforementioned test terminal) of the third register Re_3 receives the test pattern and then transmits it to the SI terminal of the second register Re_2 via its Q terminal. The SI terminal of the second register Re_2 receives the output of the third register Re_3 and then transmits it to the SI terminal of the first register Re_1 via its Q terminal. In other words, in scan-shift mode, the operations of the first register Re_1, the second register Re_2, and the third register Re_3 are similar to those of registers in an existing scan chain. That is, the first register Re_1, the second register Re_2, and the third register Re_3 are cascaded; the test pattern TP is received by the third register Re_3 and transmitted step-by-step to the first register Re_1 and the second register Re_2. However, the second register Re_2 and the third register Re_3 can also... Figure 4 The architecture of the first test circuit TS_1 and the second test circuit TS_2 in the above embodiment is used to provide the first controllable value and the second controllable value.

[0033] In one embodiment, Figure 5 The first register Re_1, the second register Re_2, and the third register Re_3 each include a clock signal input, which can be used to receive a clock signal CLK. This clock signal CLK can be generated by... Figure 4 The ICG circuit 401 in the middle provides this. That is, Figure 4 The ICG circuit 401 can be used to provide clock signals to the first register Re_1, the second register Re_2 and the third register Re_3, but it can also be used as the target circuit to be tested.

[0034] Figure 6 An embodiment of the present invention is shown, using Figures 1 to 5 The method and circuit diagram of the electrical architecture circuit 600. For example... Figure 6 As shown, circuit 600 includes an ICG circuit 601, a logic combination 603, a first register Re_1, and a second register Re_2. Logic combination 603 may include various required circuit elements. The SE terminals of the first register Re_1 and the second register Re_2 are coupled... Figure 4The first output terminal T_O1 is connected to the TE terminal of the ICG circuit 601. Figure 4 The second output terminal T_O2 is used. If the D terminal of the first register Re_1 is to be tested, a capture clock signal CLK will be generated. The signal output through the first output terminal T_O1 will put the first register Re_1 into scan capture mode (SE is 0), and will also enable the E terminal of the ICG circuit 601 to be 1, allowing the first register Re_1 to receive the captured clock signal. Alternatively, if the E terminal of the ICG circuit 601 is not 1, the signal output through the second output terminal T_O2 can enable the TE terminal of the ICG circuit 601 to be 1, thus allowing the first register Re_1 to receive the captured clock signal.

[0035] To test the E terminal of the ICG circuit 601, the D and Q terminals of the first register Re_1 need to have opposite values. This generates a capture clock signal CLK, which, through the signal output from the first output terminal T_O1, sets the first register Re_1 to scan capture mode (SE = 0), and through the signal output from the second output terminal T_O2, sets the TE terminal of the ICG circuit 601 to 0. However, in some complex circuit architectures, the D and Q terminals of the first register Re_1 cannot be controlled to have opposite values. This patented technology can use the signal output from the first output terminal T_O1 to set the SE terminal of the first register Re_1 to 1, thus making the SI and Q terminals of the first register Re_1 have opposite values ​​to address the deficiency in the E terminal of the ICG circuit 601. This results in better signal controllability during path switching.

[0036] However, in existing testing methods, the SE terminals of the first register Re_1 and the second register Re_2, as well as the TE terminal of the ICG circuit 601, all receive the same scan enable signal SE. In this situation, to test the D terminal of the first register Re_1, it is necessary to set the first register Re_1 to scan capture mode (SE = 0) and the E terminal of the ICG circuit 601 to 1; it is not possible to test by setting the TE terminal of the ICG circuit 601 to 1. To test for defects in the E terminal of the ICG circuit 601, the D and Q terminals of the first register Re_1 need to have opposite values ​​to generate a capture clock signal CLK, and the first register Re_1 needs to be in scan capture mode (SE = 0), and the TE terminal of the ICG circuit 601 will also be 0. However, the approach of making it impossible to detect defects in the E terminal of the ICG circuit 601 when the D and Q terminals of Re_1 can only be controlled to have the same value lacks the circuit controllability of this invention.

[0037] According to the foregoing embodiments, a circuit testing method can be obtained. Figure 7 A flowchart of a circuit testing method according to an embodiment of the present invention is shown, which includes the following steps:

[0038] Step 701

[0039] With a first test circuit (e.g.) Figure 1 TS_1) receives a test mode signal (e.g. Figure 1 (TM) and a scan enable signal (e.g. Figure 1 The SE) is used to generate a first control signal SC_1 based on the test mode signal and the scan enable signal.

[0040] Step 703

[0041] With a first target circuit (e.g.) Figure 1 The first scan control terminal of TAC_1 receives a first control signal and operates in one of a normal mode, a scan shift mode and a scan capture mode according to the first control signal.

[0042] In one embodiment, the first target circuit is a first register, and Figure 7 The circuit testing method may further include: receiving the test mode signal and the scan enable signal with a second test circuit, and generating a second control signal based on the test mode signal and the scan enable signal; using an ICG circuit (e.g., Figure 4 401) receives the second control signal and operates in one of the normal mode, the scan shift mode and the scan capture mode according to the second control signal.

[0043] According to the foregoing embodiments, the scanning control terminals of different target circuits can be controlled separately, allowing different target circuits to operate in the required modes. This can improve the problem in the prior art where the target circuit can only exist in the scanning shift mode or the scanning capture mode at the same time, resulting in poor circuit controllability.

[0044] The above are merely preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A circuit test system, comprising: a first test circuit including a first output coupled to a first scan control terminal of a first target circuit, the first test circuit configured to receive a test mode signal and a scan enable signal and generate a first control signal based on the test mode signal and the scan enable signal; wherein the first target circuit operates in one of a normal mode, a scan shift mode, and a scan capture mode based on the first control signal.

2. The circuit test system of claim 1, wherein: the first target circuit includes at least one test terminal, the first target circuit normally performs its intended function in the normal mode; the test terminal of the first target circuit receives a test pattern in the scan shift mode; the test terminal of the first target circuit does not receive the test pattern but can receive other test signals in the scan capture mode.

3. The circuit testing system of claim 2, wherein, the first target circuit operates in the normal mode if both the test mode signal and the scan enable signal are a first logic value, the first target circuit operates in the scan shift mode if both the test mode signal and the scan enable signal are a second logic value, the first target circuit operates in the scan capture mode if the test mode signal is the second logic value and the scan enable signal is the first logic value.

4. The circuit test system of claim 1, wherein: the first test circuit includes: a first multiplexer having the first output, a first input of the first multiplexer receiving the scan enable signal, a select input of the first multiplexer receiving the test mode signal; and a first OR gate having an output coupled to a second input of the first multiplexer, a first input of the first OR gate receiving a first controllable value, a second input of the first OR gate receiving the scan enable signal.

5. The circuit testing system of claim 1, wherein, the first target circuit is a first register, the circuit test system further comprising: a second test circuit including a second output coupled to a second scan control terminal of a clock signal gating circuit, the second test circuit configured to receive the test mode signal and the scan enable signal and generate a second control signal based on the test mode signal and the scan enable signal; wherein the clock signal gating circuit operates in one of the normal mode, the scan shift mode, and the scan capture mode based on the second control signal.

6. The circuit testing system of claim 5, wherein, a third output receiving the scan enable signal and passing the scan enable signal to a circuit.

7. The circuit testing system of claim 1, wherein, further comprising: a second test circuit coupled to a second output terminal of a second target circuit, the second output terminal coupled to a second scan control terminal of the second target circuit, the second test circuit configured to receive the test mode signal and the scan enable signal and generate a second control signal based on the test mode signal and the scan enable signal; wherein the second target circuit operates in one of the normal mode, the scan shift mode and the scan capture mode based on the second control signal; wherein the first test circuit comprises: a first multiplexer having the first output terminal, a first input terminal of the first multiplexer configured to receive the scan enable signal, a select input terminal of the first multiplexer configured to receive the test mode signal; and a first OR gate having an output coupled to a second input terminal of the first multiplexer, a first input terminal of the first OR gate configured to receive a first controllable value, a second input terminal of the first OR gate configured to receive the scan enable signal; wherein the second test circuit comprises: a second multiplexer having the second output terminal, a first input terminal of the second multiplexer configured to receive the scan enable signal, a select input terminal of the second multiplexer configured to receive the test mode signal; and a second OR gate having an output coupled to a second input terminal of the second multiplexer, a first input terminal of the second OR gate configured to receive a second controllable value, a second input terminal of the second OR gate configured to receive the scan enable signal.

8. The circuit testing system of claim 7, wherein, the first target circuit is a first register, the first controllable value is generated by a second register, and the second controllable value is generated by a third register.

9. The circuit testing system of claim 8, wherein, wherein when the first register, the second register and the third register operate in the scan shift mode, the first register, the second register and the third register are connected in series, the test pattern is received by the third register and sequentially transmitted to the first register and the second register.

10. A circuit test method, comprising: receiving a test mode signal and a scan enable signal with a first test circuit and generating a first control signal based on the test mode signal and the scan enable signal; receiving the first control signal with a first scan control terminal of a first target circuit and operating in one of a normal mode, a scan shift mode and a scan capture mode based on the first control signal.

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