Electro-optic modulation structure and silicon-based modulator thereof

Abstract

The application provides an electro-optical modulation structure and a silicon-based modulator thereof, comprising a symmetric coplanar waveguide electrode structure layer, a bottom metal layer and a PN junction modulation layer; the bottom metal layer is arranged between the symmetric coplanar waveguide electrode structure layer and the PN junction modulation layer, the symmetric coplanar waveguide electrode structure layer is electrically connected with the bottom metal layer, and the bottom metal layer is electrically connected with the PN junction modulation layer; the symmetric coplanar waveguide electrode structure layer is used for receiving a target differential electric signal, and the target differential electric signal is transmitted to the PN junction modulation layer through the bottom metal layer; the bottom metal layer is used for forming a parasitic capacitance in series with an equivalent capacitance of the PN junction modulation layer with the symmetric coplanar waveguide electrode structure layer or the PN junction modulation layer, so as to reduce transmission loss of the target differential electric signal; and the PN junction modulation layer is used for adjusting a waveguide refractive index based on the target differential electric signal, wherein the adjusted waveguide refractive index is used for phase modulation of a required modulated optical signal.

Description

Technical Field

[0001] This application relates to the field of silicon photonics design technology, and more specifically, to an electro-optic modulation structure and its silicon-based modulator. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence, big data models, and high-performance computing, data center traffic transmission has increased dramatically, placing higher demands on the transmission bandwidth of switches. Pluggable optical modules are small, hot-swappable optical transceivers installed in switch ports. Electro-optic modulators are an important component of optical transceivers, primarily used to convert electrical signals into optical signals.

[0003] Compared to traditional photonic integrated circuits, silicon-based optoelectronics shows great potential for large-scale optoelectronic integration: optical interconnects have advantages such as high bandwidth, low latency and low power consumption, and are compatible with mature complementary metal-oxide-semiconductor (CMOS) processes with low cost, large scale, high integration and high reliability.

[0004] On silicon-based platforms, the most common modulator is the Mach-Zehnder modulator (MZM) using a symmetrical coplanar waveguide electrode structure (GSGSG). However, the commonly used GGSG MZM has a large capacitance due to its doped PN (or PIN) junction modulation structure. This causes the electrical signal to attenuate significantly when it is transmitted along the transmission line, resulting in a low bandwidth at the final output of the MZM, which cannot meet the requirements of high-speed signals. Summary of the Invention

[0005] The purpose of this application is to provide an electro-optic modulation structure and its silicon-based modulator to solve the problem that the current Mach-Zehnder modulator of the symmetrical coplanar waveguide electrode structure (GSGSG) has a large capacitance, which causes the electrical signal to attenuate significantly when it is transmitted along the transmission line, resulting in a low bandwidth of the final output of the MZM and failing to meet the requirements of high-speed signals.

[0006] In a first aspect, this application provides an electro-optic modulation structure, including a symmetrical coplanar waveguide electrode structure layer, a bottom metal layer, and a PN junction modulation layer; the bottom metal layer is disposed between the symmetrical coplanar waveguide electrode structure layer and the PN junction modulation layer, the symmetrical coplanar waveguide electrode structure layer and the bottom metal layer are electrically connected, and the bottom metal layer and the PN junction modulation layer are electrically connected; the symmetrical coplanar waveguide electrode structure layer is used to receive a target differential electrical signal and transmit the target differential electrical signal to the PN junction modulation layer through the bottom metal layer; the bottom metal layer is used to form an augmented capacitance with the symmetrical coplanar waveguide electrode structure layer or the PN junction modulation layer, which is connected in series with the equivalent capacitance of the PN junction modulation layer, so as to reduce the transmission loss of the target differential electrical signal; the PN junction modulation layer is used to adjust the waveguide refractive index based on the target differential electrical signal, wherein the adjusted waveguide refractive index is used to perform phase modulation on the optical signal to be modulated.

[0007] The electro-optic modulation structure designed above uses a bottom metal layer between the symmetrical coplanar waveguide electrode structure layer and the PN junction modulation layer. The symmetrical coplanar waveguide electrode structure layer receives the target differential electrical signal input from the outside, and the signal is transmitted to the PN junction modulation layer through the conductive path of the bottom metal layer. Secondly, the bottom metal layer is not completely conductively connected, but forms a specific capacitance structure (increased capacitance) with the symmetrical coplanar waveguide electrode structure layer or the PN junction modulation layer. This increased capacitance is in series with the equivalent capacitance of the PN junction modulation layer itself. Therefore, the total equivalent capacitance value after series connection will be less than the equivalent capacitance of a single PN junction. Since capacitive loss is positively correlated with capacitance value, reducing the total capacitance can effectively reduce capacitive attenuation during electrical signal transmission, thereby increasing the electrical signal transmission rate. This allows the PN junction modulation layer to change its waveguide refractive index based on the differential electrical signal, thereby achieving phase modulation of the input optical signal. This solves the problem of insufficient bandwidth in the existing GGSSG structure MZM and improves the bandwidth of the phase-modulated optical signal.

[0008] In an optional embodiment of the first aspect, the bottom metal layer includes a metal block array formed by a plurality of parallel metal blocks; each metal block in the metal block array is electrically connected to the PN junction modulation layer; some metal blocks in the metal block array are electrically connected to the symmetrical coplanar waveguide electrode structure layer, and the remaining metal blocks are insulated from the symmetrical coplanar waveguide electrode structure layer to form an augmenting capacitance; or, each metal block in the metal block array is electrically connected to the symmetrical coplanar waveguide electrode structure layer; some metal blocks in the metal block array are electrically connected to the PN junction modulation layer, and the remaining metal blocks are insulated from the PN junction modulation layer to form an augmenting capacitance.

[0009] In the above-described implementation, this solution designs a metal block array that uses selective electrical connections. By adjusting the number, size, and spacing of the insulating metal blocks, the capacitance value of the augmented capacitor can be precisely adjusted, thereby adapting to the bandwidth requirements of different high-speed signals. At the same time, the parallel arrangement of multiple metal blocks ensures that the augmented capacitor is evenly distributed between the symmetrical coplanar waveguide electrode structure layer and the PN junction modulation layer, avoiding signal distortion caused by local capacitance concentration and improving transmission stability. In addition, the metal block array structure allows for flexible adjustment of metal block parameters according to process precision without modifying the overall structure, exhibiting strong process scalability.

[0010] In an optional embodiment of the first aspect, the symmetrical coplanar waveguide electrode structure layer includes a first ground electrode, a first signal electrode, a second ground electrode, a second signal electrode, and a third ground electrode arranged in parallel; the first signal electrode is disposed between the first ground electrode and the second ground electrode, and the second signal electrode is disposed between the second ground electrode and the third ground electrode, wherein the first signal electrode and the first ground electrode are symmetrically disposed with respect to the second ground electrode; the bottom metal layer includes a plurality of first signal metal blocks, a plurality of second signal metal blocks, and a plurality of ground metal blocks; the PN junction modulation layer includes a first interference arm, a second interference arm, and a common area; the plurality of first signal metal blocks are disposed between the first signal electrode and the first interference arm, the plurality of second signal metal blocks are disposed between the second signal electrode and the second interference arm, and the plurality of ground metal blocks are disposed between the second ground electrode and the common area.

[0011] In the above implementation scheme, the design of the symmetrical coplanar waveguide electrode structure layer, the bottom metal layer and the PN junction modulation layer is one-to-one, so that the positive and negative ends of the differential electrical signal are precisely applied to the first and second interference arms respectively. The amplitude and phase of the signals received by the two arms are completely symmetrical, avoiding modulation distortion caused by signal asymmetry and improving linearity. The signal transmission path is the shortest and most accurate, reducing the transmission distance and leakage of the electrical signal, and further reducing transmission loss. The symmetrical design of the GGSSG electrode structure and the two interference arms can effectively shield external electromagnetic interference, while reducing crosstalk between the two arms and improving anti-interference capability.

[0012] In an optional embodiment of the first aspect, each first signal metal block is electrically connected to a first signal electrode; a portion of the plurality of first signal metal blocks is electrically connected to a first interference arm, while the remaining portion of the first signal metal blocks is insulated from the first interference arm; each second signal metal block is electrically connected to a second signal electrode, a portion of the plurality of second signal metal blocks is electrically connected to a second interference arm, while the remaining portion of the second signal metal blocks is insulated from the second interference arm; each grounding metal block is electrically connected to a second grounding electrode and a common area; wherein the remaining portion of the first signal metal blocks and the remaining portion of the second signal metal blocks are metal blocks positioned opposite each other.

[0013] In the above implementation, the signal metal block being fully connected to the electrode layer ensures complete coverage of the electrical signal, while the partial connection to the interference arms enables precise signal transmission. The accumulating capacitance formed by the isolation portion is directly connected in series on the signal path, eliminating the need for additional layout and minimizing signal loss. The design of the isolation metal blocks with opposite positions allows for precise control of the accumulating capacitance values ​​of the two interference arms to be equal, ensuring the symmetry of the phase adjustment of the two arms and improving modulation accuracy. The full connection design between the signal metal block and the electrode layer reduces the number of electrical connection points, lowers the probability of contact failure, and improves structural reliability.

[0014] In an optional embodiment of the first aspect, each first signal metal block is electrically connected to a first interference arm; a portion of the plurality of first signal metal blocks are electrically connected to a first signal electrode, while the remaining portion of the first signal metal blocks are insulated from the first signal electrode; each second signal metal block is electrically connected to a second interference arm; a portion of the plurality of second signal metal blocks are electrically connected to a second signal electrode, while the remaining portion of the second signal metal blocks are insulated from the second signal electrode; each grounding metal block is electrically connected to a second grounding electrode and a common area; wherein the remaining portion of the first signal metal blocks and the remaining portion of the second signal metal blocks are metal blocks positioned opposite each other.

[0015] In the above implementation, the signal metal block fully connected to the interferometer arm can make the electrical signal uniformly distributed on the surface of the interferometer arm, avoiding excessively strong or weak local signals and improving the efficiency of the electric field in regulating the refractive index (high electric field utilization). The augmented capacitance is formed between the signal metal block and the electrode layer, close to the interferometer arm region. The capacitance change can directly affect the electro-optic response of the interferometer arm and improve the modulation sensitivity. The uniform electric field distribution avoids semiconductor material aging caused by local electric field concentration and extends the device life.

[0016] In an optional embodiment of the first aspect, each first signal metal block is electrically connected to a first signal electrode and a first interference arm, and each second signal metal block is electrically connected to a second signal electrode and a second interference arm; each grounding metal block is electrically connected to a second grounding electrode; some of the grounding metal blocks are electrically connected to a common area, and the remaining grounding metal blocks are insulated from the common area; or, each grounding metal block is electrically connected to a common area, some of the grounding metal blocks are electrically connected to a second grounding electrode, and the remaining grounding metal blocks are isolated from the second grounding electrode.

[0017] In the above implementation, the fully connected design of the signal metal block ensures lossless transmission of differential electrical signals. The induced capacitance is formed only through the grounding metal block and does not affect the signal transmission path. It can significantly reduce the total capacitance and increase the bandwidth while ensuring signal integrity. The partial connection design of the grounding metal block can anchor the common area potential and avoid potential fluctuations from affecting the electro-optic characteristics of the two interference arms, ensuring the consistency of modulation effect under different working conditions.

[0018] In an optional embodiment of the first aspect, the symmetrical coplanar waveguide electrode structure layer further includes a bias electrode, and the bottom metal layer further includes a bias metal block; the bias electrode is electrically connected to the common area through the bias metal block.

[0019] In the above implementation scheme, the bias electrode designed in this scheme applies a DC bias voltage to the common region through a bias metal block, which can precisely adjust the depletion layer width of the PN junction, so that the PN junction works in the region where the electro-optic effect is most sensitive, thereby improving the efficiency of electrical signal in regulating the optical phase.

[0020] In an alternative embodiment of the first aspect, each first signal metal block is electrically connected to a first signal electrode and a first interference arm; each second signal metal block is electrically connected to a second signal electrode and a second interference arm; each grounding metal block is electrically connected to a second grounding electrode; and all grounding metal blocks in the plurality of grounding metal blocks are insulated from the common area.

[0021] In the above implementation, the grounding metal block is completely isolated from the common area, and the potential of the common area is controlled only by the bias electrode, avoiding interference from the potential fluctuation of the grounding electrode to the operating point, achieving high-precision adjustment of the operating point, and thus improving the modulation sensitivity; the full isolation design makes the amplification capacitance evenly distributed between the grounding metal block and the common area, and the total capacitance value is stable, ensuring that the modulator bandwidth remains stable under different operating conditions; the independent bias control and grounding shielding design can effectively resist external electromagnetic interference and internal crosstalk, and the anti-interference capability is significantly enhanced.

[0022] In an alternative embodiment of the first aspect, each first signal metal block is electrically connected to a first signal electrode and a first interference arm; each second signal metal block is electrically connected to a second signal electrode and a second interference arm; each grounding metal block is electrically connected to a common area; and all grounding metal blocks in the plurality of grounding metal blocks are insulated from the second grounding electrode.

[0023] In the above implementation scheme, the grounding metal block is fully connected to the common area to initially anchor the potential of the common area. The bias electrode applies a fine-tuning voltage to achieve stable and precise adjustment of the potential, ensuring the consistency of the modulation effect. The grounding metal block is completely isolated from the electrode layer, and the augmentation capacitor and the grounding path are independent of each other, avoiding signal leakage from the grounding path from affecting the performance of the augmentation capacitor and further reducing signal loss.

[0024] In an optional embodiment of the first aspect, the first interference arm is composed of a first N-type heavily doped region, a first N-type moderately doped region, a first N-type lightly doped region, a first P-type lightly doped region, a first P-type moderately doped region, and a P-type heavily doped region; the second interference arm is composed of a P-type heavily doped region, a second P-type moderately doped region, a second P-type lightly doped region, a second N-type lightly doped region, a second N-type moderately doped region, and a second N-type heavily doped region; wherein, the P-type heavily doped region is a common region; the first N-type heavily doped region is used for electrical connection with a plurality of first signal metal blocks, and the second N-type heavily doped region is used for electrical connection with a plurality of second signal metal blocks.

[0025] In the above implementation, this scheme optimizes the electric field distribution and capacitance characteristics based on gradient doping: the first interferometer arm adopts a gradient doping structure of "first N-type heavily doped region → first N-type medium doped region → first N-type lightly doped region → first P-type lightly doped region → first P-type medium doped region → P-type heavily doped region (common region)" to form a continuous PN junction transition region; the second interferometer arm N2 adopts a symmetrical gradient doping structure of "P-type heavily doped region (common region) → second P-type medium doped region → second P-type lightly doped region → second N-type lightly doped region → second N-type medium doped region → second N-type heavily doped region", making the electro-optic characteristics of the two interferometer arms completely symmetrical. The gradient doping design can increase the depletion layer area of ​​the PN junction, reduce the capacitance density per unit area, and thus reduce the equivalent capacitance of the PN junction; at the same time, the uniform electric field distribution can improve the efficiency of the electrical signal in regulating the refractive index, further reducing the electrical signal transmission loss. In addition, the first and second N-type heavily doped regions are electrically connected to the first and second signal metal blocks, respectively, to ensure that the electrical signal can be efficiently injected into the interferometer arm.

[0026] In an optional embodiment of the first aspect, the symmetrical coplanar waveguide electrode structure layer and the bottom metal layer are electrically connected through metal vias, and the bottom metal layer and the PN junction modulation layer are electrically connected through metal contact holes.

[0027] In the above implementation scheme, the symmetrical coplanar waveguide electrode structure layer and the bottom metal layer are connected by metal vias. The vertical low impedance connection is achieved through the metal vias. Compared with the planar connection, the transmission distance is shorter, the contact resistance is lower, and the electrical signal loss is significantly reduced. The bottom metal layer and the PN junction modulation layer are connected by metal contact holes. The metal contact holes penetrate into the PN junction doped region to form a good ohmic contact, avoiding signal attenuation and heat generation caused by excessive contact resistance, and improving connection stability and device reliability.

[0028] In a second aspect, this application provides a silicon-based modulator, including a substrate layer, an insulating layer, a cladding layer, and an electro-optic modulation structure according to any optional embodiment of the first aspect. The insulating layer is disposed on the substrate layer, the cladding layer is disposed on the insulating layer, and the electro-optic modulation structure is disposed within the cladding layer. The cladding layer is used to cover the electro-optic modulation structure and is used for light confinement and isolation.

[0029] The silicon-based modulator designed above, because it includes the electro-optic modulation structure described above to achieve phase modulation of the optical signal, can solve the problem of insufficient bandwidth of the existing GGSSG structure MZM and improve the bandwidth of the output signal of the silicon-based modulator.

[0030] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a first structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0033] Figure 2 Equivalent circuit diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0034] Figure 3 Schematic diagrams of the second and third types of electro-optic modulation structures provided in embodiments of this application;

[0035] Figure 4 This is a fourth structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0036] Figure 5 This is a fifth structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0037] Figure 6 This is a sixth structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0038] Figure 7 This is a seventh structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0039] Figure 8 This is an eighth structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0040] Figure 9 This is a ninth structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0041] Figure 10 This is a tenth structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0042] Figure 11 This is an eleventh structural schematic diagram of the electro-optic modulation structure provided in the embodiments of this application;

[0043] Figure 12 This is a schematic diagram of the structure of a silicon-based modulator provided in an embodiment of this application.

[0044] Icons: 1-Substrate; 2-Insulating layer; 3-Cladding; 4-Electro-optic modulation structure; 10-Symmetrical coplanar waveguide electrode structure layer; 20-Bottom metal layer; 30-PN junction modulation layer; G1-First ground electrode; G2-Second ground electrode; G3-Third ground electrode; S1-First signal electrode; S2-Second signal electrode; C-Metal block; C1-First signal metal block; C2-Second signal metal block; C3-Ground metal block; C4-Bias metal block; D1-Bias electrode N1 - First interference arm; N11 - First heavily doped N-type region; N12 - First moderately doped N-type region; N13 - First lightly doped N-type region; P11 - First lightly doped P-type region; P12 - First moderately doped P-type region; N2 - Second interference arm; N21 - Second heavily doped N-type region; N22 - Second moderately doped N-type region; N23 - Second lightly doped N-type region; P21 - Second lightly doped P-type region; P22 - Second moderately doped P-type region; Pn - Heavyly doped P-type region; N3 - Common region. Detailed Implementation

[0045] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0047] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0048] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0050] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0051] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0052] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0053] In recent years, with the rapid development of artificial intelligence, big data models, and high-performance computing, data center traffic transmission has increased dramatically, placing higher demands on the transmission bandwidth of switches. Pluggable optical modules are small, hot-swappable optical transceivers installed in switch ports. Electro-optic modulators are an important component of optical transceivers, primarily used to convert electrical signals into optical signals.

[0054] Compared to traditional photonic integrated circuits, silicon-based optoelectronics shows great potential for large-scale optoelectronic integration: optical interconnects have advantages such as high bandwidth, low latency and low power consumption, and are compatible with mature complementary metal-oxide-semiconductor (CMOS) processes with low cost, large scale, high integration and high reliability.

[0055] On silicon-based platforms, the most common modulator is the Mach-Zehnder modulator (MZM) using a symmetrical coplanar waveguide electrode structure (GSGSG). However, the commonly used GGSG MZM has a large capacitance due to its doped PN (or PIN) junction modulation structure. This causes the electrical signal to attenuate significantly when it is transmitted along the transmission line, resulting in a low bandwidth at the final output of the MZM, which cannot meet the requirements of high-speed signals.

[0056] To address the aforementioned issues, this application first provides an electro-optic modulation structure and its silicon-based modulator. A bottom metal layer is disposed between a symmetrical coplanar waveguide electrode structure layer and a PN junction modulation layer. The symmetrical coplanar waveguide electrode structure layer receives an externally input target differential electrical signal, which is transmitted to the PN junction modulation layer via the conductive path of the bottom metal layer. Secondly, the bottom metal layer is not completely conductive; instead, it forms a specific capacitance structure (increased capacitance) with the symmetrical coplanar waveguide electrode structure layer or the PN junction modulation layer. This increased capacitance is in series with the equivalent capacitance of the PN junction modulation layer itself. Therefore, the total equivalent capacitance after series connection is less than the equivalent capacitance of a single PN junction. Since capacitive loss is positively correlated with capacitance, reducing the total capacitance effectively reduces capacitive attenuation during signal transmission, thereby increasing the signal transmission rate. This allows the PN junction modulation layer to change its waveguide refractive index based on the differential electrical signal, achieving phase modulation of the input optical signal. This solves the problem of insufficient bandwidth in existing GSGSG structures and improves the bandwidth of phase-modulated optical signals.

[0057] Based on the above ideas, this application first provides an electro-optic modulation structure, such as... Figure 1 As shown, the electro-optic modulation structure includes a symmetrical coplanar waveguide electrode structure layer 10, a bottom metal layer 20, and a PN junction modulation layer 30. The bottom metal layer 20 is disposed between the symmetrical coplanar waveguide electrode structure layer 10 and the PN junction modulation layer 30. The symmetrical coplanar waveguide electrode structure layer 10 is electrically connected to the bottom metal layer 20, and the bottom metal layer 20 is electrically connected to the PN junction modulation layer 30.

[0058] The symmetrical coplanar waveguide electrode structure layer 10 represents a symmetrical arrangement of parallel electrodes, from left to right: first ground electrode G1, first signal electrode S1, second ground electrode G2, second signal electrode S2, and third ground electrode G3. The middle second ground electrode G2 serves as the symmetry reference, and the "ground electrode + signal electrode" combinations on both sides (G1-S1 and S2-G3) are completely symmetrical with respect to the second ground electrode G2, forming paired signal transmission channels specifically adapted for the transmission of differential electrical signals at their positive and negative ends.

[0059] The electro-optic modulation structure designed above comprises a symmetrical coplanar waveguide electrode structure layer 10, a bottom metal layer 20, and a PN junction modulation layer 30, arranged sequentially from top to bottom. The bottom metal layer 20 serves as an intermediate transition layer, enabling electrical connection and capacitance formation between the upper and lower layers. Specifically, the symmetrical coplanar waveguide electrode structure layer 10 receives an externally input target differential electrical signal. This target differential electrical signal represents a signal pair composed of two electrical signals with equal amplitude and opposite phase. Compared to single-ended electrical signals, it has advantages such as strong anti-interference capability and high transmission rate. In this invention, the target differential electrical signal is the high-speed electrical signal used to drive the electro-optic modulation structure.

[0060] The target differential electrical signal is transmitted to the PN junction modulation layer 30 through the conductive path of the bottom metal layer 20. After receiving the differential electrical signal, the PN junction modulation layer 30 changes its waveguide refractive index based on the electro-optic effect to achieve phase modulation of the input optical signal.

[0061] In this circuit, the bottom metal layer 20 is not completely conductive; instead, it forms a specific augmenting capacitance Cld with the symmetrical coplanar waveguide electrode structure layer 10 or the PN junction modulation layer 30. This augmenting capacitance Cld is in series with the equivalent capacitance Cpn of the PN junction modulation layer 30 itself, thereby reducing the total equivalent capacitance of the entire circuit. Specifically, as shown... Figure 2 As shown, it is an equivalent circuit diagram of an electro-optic modulation structure. It can be seen from the figure that the total equivalent capacitance Cep = 1 / (1 / Cpn + 1 / Cld). Therefore, the total equivalent capacitance Cep after series connection will be less than the equivalent capacitance Cpn of a single PN junction modulation layer 30. Since capacitive loss is positively correlated with capacitance value, reducing the total capacitance can effectively reduce capacitive attenuation during electrical signal transmission, thereby increasing the electrical signal transmission rate. This allows the PN junction modulation layer to change its waveguide refractive index based on the differential electrical signal, thereby achieving phase modulation of the input optical signal. This solves the problem of insufficient bandwidth of the existing GSGSG structure MZM and improves the bandwidth of the phase-modulated optical signal.

[0062] The electro-optic modulation structure designed above uses a bottom metal layer between the symmetrical coplanar waveguide electrode structure layer and the PN junction modulation layer. The symmetrical coplanar waveguide electrode structure layer receives the target differential electrical signal input from the outside, and the signal is transmitted to the PN junction modulation layer through the conductive path of the bottom metal layer. Secondly, the bottom metal layer is not completely conductively connected, but forms a specific capacitance structure (increased capacitance) with the symmetrical coplanar waveguide electrode structure layer or the PN junction modulation layer. This increased capacitance is in series with the equivalent capacitance of the PN junction modulation layer itself. Therefore, the total equivalent capacitance value after series connection will be less than the equivalent capacitance of a single PN junction. Since capacitive loss is positively correlated with capacitance value, reducing the total capacitance can effectively reduce capacitive attenuation during electrical signal transmission, thereby increasing the electrical signal transmission rate. This allows the PN junction modulation layer to change its waveguide refractive index based on the differential electrical signal, thereby achieving phase modulation of the input optical signal. This solves the problem of insufficient bandwidth in the existing GGSSG structure MZM and improves the bandwidth of the phase-modulated optical signal.

[0063] In an optional implementation of this embodiment, such as Figure 3 As shown, the bottom metal layer 20 of this design includes a metal block array formed by multiple parallel metal blocks C, wherein, as... Figure 3 As shown in (a), each metal block C in the metal block array is electrically connected to the PN junction modulation layer 30; some metal blocks in the metal block array are electrically connected to the symmetrical coplanar waveguide electrode structure layer 10, while the remaining metal blocks are insulated from the symmetrical coplanar waveguide electrode structure layer 10 to form an augmenting capacitance Cld; or, as shown in (a), each metal block C in the metal block array is electrically connected to ... Figure 3 As shown in (b), each metal block C in the metal block array is electrically connected to the symmetrical coplanar waveguide electrode structure layer 10; some metal blocks in the metal block array are electrically connected to the PN junction modulation layer 30, while the remaining metal blocks are insulated from the PN junction modulation layer 30 to form an augmented capacitance.

[0064] In the above implementation method, this solution forms the augmenting capacitor through two different electrical connection logics, and the implementation principle is divided into two categories: such as Figure 3 As shown in (a), the first type of logic is that the metal block C is fully connected to the PN junction modulation layer 30, and part of the metal block is connected to the symmetrical coplanar waveguide electrode structure layer 10 for transmitting electrical signals. The remaining part of the metal block is insulated from the symmetrical coplanar waveguide electrode structure layer 10. At this time, a gap is formed between the insulated remaining part of the metal block and the symmetrical coplanar waveguide electrode structure layer 10, which constitutes the augmented capacitor Cld. This augmented capacitor is connected in series with the equivalent capacitance of the PN junction modulation layer 30.

[0065] like Figure 3As shown in (b), the second type of logic involves a metal block C fully connected to the symmetrical coplanar waveguide electrode structure layer 10 and a portion of the metal block connected to the PN junction modulation layer 30 for transmitting electrical signals. The remaining metal block is insulated from the PN junction modulation layer 30, and the capacitance formed at the isolation point is the augmented capacitance, which is also connected in series with the equivalent capacitance of the PN junction. It should be noted that the value of the augmented capacitance can be determined based on the number and size of the metal blocks, as well as the insulation distance between the metal blocks and the symmetrical coplanar waveguide electrode structure layer 10 or the PN junction modulation layer 30.

[0066] In the above-described implementation, this solution designs a metal block array that uses selective electrical connections. By adjusting the number, size, and spacing of the insulating metal blocks, the capacitance value of the augmented capacitor can be precisely adjusted, thereby adapting to the bandwidth requirements of different high-speed signals. At the same time, the parallel arrangement of multiple metal blocks ensures that the augmented capacitor is evenly distributed between the symmetrical coplanar waveguide electrode structure layer and the PN junction modulation layer, avoiding signal distortion caused by local capacitance concentration and improving transmission stability. In addition, the metal block array structure allows for flexible adjustment of metal block parameters according to process precision without modifying the overall structure, exhibiting strong process scalability.

[0067] In an optional implementation of this embodiment, please refer to Figure 4 As mentioned above, the symmetrical coplanar waveguide electrode structure layer 10 designed in this scheme includes a first ground electrode G1, a first signal electrode S1, a second ground electrode G2, a second signal electrode S2, and a third ground electrode G3 arranged in parallel. The first signal electrode S1 is disposed between the first ground electrode G1 and the second ground electrode G2, and the second signal electrode S2 is disposed between the second ground electrode G2 and the third ground electrode G3. The first signal electrode S1 and the first ground electrode G1 are symmetrically arranged with respect to the second ground electrode G2, as are the second signal electrode S2 and the third ground electrode G3.

[0068] The bottom metal layer 20 includes multiple first signal metal blocks C1, multiple second signal metal blocks C2, and multiple ground metal blocks C3. The PN junction modulation layer 30 includes a first interference arm N1, a second interference arm N2, and a common area N3. The multiple first signal metal blocks C1 are disposed between the first signal electrode S1 and the first interference arm N1, the multiple second signal metal blocks C2 are disposed between the second signal electrode S2 and the second interference arm N2, and the multiple ground metal blocks C3 are disposed between the second ground electrode G2 and the common area N3.

[0069] In the above implementation scheme, the symmetrical coplanar waveguide electrode structure layer 10 is designed with a GSGSG arrangement. The first signal electrode S1 and the second signal electrode S2 transmit the positive and negative terminals of the differential electrical signal, respectively. The second ground electrode G2 serves as the central symmetrical reference, and the first ground electrode G1 and the third ground electrode G3 provide ground protection on both sides. The bottom metal layer 20 is provided with a first signal metal block C1, a second signal metal block C2, and a ground metal block C3 corresponding to the electrode layer. These blocks respectively establish transmission paths between the first signal electrode S1 and the first interference arm N1, the second signal electrode S2 and the second interference arm N2, and the second ground electrode G2 and the common area N3, thereby realizing the independent driving of the two interference arms by the differential electrical signal and the potential anchoring between the ground electrode and the common area. The first interference arm N1 and the second interference arm N2 of the PN junction modulation layer 30 correspond to the two optical transmission paths of the Mach-Zehnder modulator. The common area N3 serves as a shared doped region for the two interference arms, ensuring the electro-optical symmetry of the two arms.

[0070] In the above implementation scheme, the design of the symmetrical coplanar waveguide electrode structure layer, the bottom metal layer and the PN junction modulation layer is one-to-one, so that the positive and negative ends of the differential electrical signal are precisely applied to the first and second interference arms respectively. The amplitude and phase of the signals received by the two arms are completely symmetrical, avoiding modulation distortion caused by signal asymmetry and improving linearity. The signal transmission path is the shortest and most accurate, reducing the transmission distance and leakage of the electrical signal, and further reducing transmission loss. The symmetrical design of the GGSSG electrode structure and the two interference arms can effectively shield external electromagnetic interference, while reducing crosstalk between the two arms and improving anti-interference capability.

[0071] Furthermore, based on the symmetrical coplanar waveguide electrode structure layer, the bottom metal layer, and the PN junction modulation layer designed above, this scheme can achieve the formation of the augmented capacitance through the following various implementation methods:

[0072] As one possible implementation method, such as Figure 5 As shown, for the sake of brevity and clarity, Figure 5 The first grounding electrode G1 and the third grounding electrode G3 are not shown in the diagram. In this design, each first signal metal block C1 is electrically connected to the first signal electrode S1; some of the first signal metal blocks C1 are electrically connected to the first interference arm N1, while the remaining first signal metal blocks are insulated from the first interference arm; each second signal metal block C2 is electrically connected to the second signal electrode S2; some of the second signal metal blocks C2 are electrically connected to the second interference arm N2, while the remaining second signal metal blocks are insulated from the second interference arm N2; each grounding metal block C3 is electrically connected to the second grounding electrode G2 and the common area N3; wherein, the remaining first signal metal blocks and the remaining second signal metal blocks are metal blocks in opposite positions.

[0073] The above implementation uses a logic of connecting all signal metal blocks to the electrodes and partially to the interference arms to construct the augmented capacitance. The principle is as follows: All first signal metal blocks C1 are electrically connected to the first signal electrode S1, ensuring that the electrical signal transmitted by the electrode layer covers all first signal metal blocks C1. Part of the first signal metal blocks are electrically connected to the first interference arm N1, transmitting the electrical signal to the first interference arm N1 to adjust the refractive index. The remaining first signal metal blocks are insulated from the first interference arm N1, forming an augmented capacitance at the isolation points. Similarly, all second signal metal blocks C2 are electrically connected to the second signal electrode S2, and partially to the second interference arm N2, with the remainder isolated to form an augmented capacitance. Simultaneously, all grounding metal blocks C3 are electrically connected to the second ground electrode G2 and the common area N3, ensuring the stability of the common area potential. Furthermore, the insulated first and second signal metal blocks are positioned opposite each other, ensuring that the augmented capacitance values ​​corresponding to the two interference arms are equal, guaranteeing the symmetry of the differential electrical signal, avoiding phase adjustment imbalance due to capacitance differences between the two arms, and further optimizing signal transmission loss and modulation accuracy.

[0074] In the above implementation, the signal metal block being fully connected to the electrode layer ensures complete coverage of the electrical signal, while the partial connection to the interference arms enables precise signal transmission. The accumulating capacitance formed by the isolation portion is directly connected in series on the signal path, eliminating the need for additional layout and minimizing signal loss. The design of the isolation metal blocks with opposite positions allows for precise control of the accumulating capacitance values ​​of the two interference arms to be equal, ensuring the symmetry of the phase adjustment of the two arms and improving modulation accuracy. The full connection design between the signal metal block and the electrode layer reduces the number of electrical connection points, lowers the probability of contact failure, and improves structural reliability.

[0075] As another possible implementation, such as Figure 6 As shown, for the sake of brevity and clarity, Figure 6 In the diagram, the first grounding electrode G1 and the third grounding electrode G3 are not shown. Each first signal metal block C1 is electrically connected to the first interference arm N1. Some of the first signal metal blocks C1 are electrically connected to the first signal electrode S1, while the remaining first signal metal blocks are insulated from the first signal electrode S1. Each second signal metal block C2 is electrically connected to the second interference arm N2. Some of the second signal metal blocks C2 are electrically connected to the second signal electrode S2, while the remaining second signal metal blocks are insulated from the second signal electrode S2. Each grounding metal block C3 is electrically connected to the second grounding electrode G2 and the common area N3. Among these, the remaining first signal metal blocks and the remaining second signal metal blocks are metal blocks in opposite positions.

[0076] The above implementation uses a method of "signal metal blocks fully connected to the interferometer arm and partially connected to the electrode" to construct the augmented capacitance. The principle is as follows: the first signal metal blocks C1 are all electrically connected to the first interferometer arm N1, ensuring that the first interferometer arm N1 can receive a stable electrical signal. Part of the first signal metal blocks are electrically connected to the first signal electrode S1 to introduce the differential electrical signal into the electrode layer, while the remaining first signal metal blocks are insulated from the first signal electrode S1, forming an augmented capacitance at the isolation points. Similarly, the second signal metal blocks C2 adopt the same design, all electrically connected to the second interferometer arm N2, partially connected to the second signal electrode S2, and the remainder isolated to form an augmented capacitance. The grounding metal block C3 remains fully connected to ensure the stability of the common area potential. The design of the relatively opposite isolation metal blocks also maintains the capacitive symmetry of the two interferometer arms. The advantage of this design is that it allows the electrical signal to be distributed more evenly on the surface of the interferometer arm, reducing local electric field concentration and further reducing capacitive losses.

[0077] In the above implementation, the signal metal block fully connected to the interferometer arm can make the electrical signal uniformly distributed on the surface of the interferometer arm, avoiding excessively strong or weak local signals and improving the efficiency of the electric field in regulating the refractive index (high electric field utilization). The augmented capacitance is formed between the signal metal block and the electrode layer, close to the interferometer arm region. The capacitance change can directly affect the electro-optic response of the interferometer arm and improve the modulation sensitivity. The uniform electric field distribution avoids semiconductor material aging caused by local electric field concentration and extends the device life.

[0078] As another possible implementation method, such as Figure 7 As shown, for the sake of brevity and clarity, Figure 7 The first grounding electrode G1 and the third grounding electrode G3 are not shown in the diagram. In this design, each first signal metal block C1 is electrically connected to the first signal electrode S1 and the first interference arm N1; each second signal metal block C2 is electrically connected to the second signal electrode S2 and the second interference arm N2; each grounding metal block C3 is electrically connected to the second grounding electrode G2; some of the grounding metal blocks C3 are electrically connected to the common area N3, while the remaining grounding metal blocks are insulated from the common area N3. Alternatively, as... Figure 8 As shown, for the sake of brevity and clarity, Figure 8 The first grounding electrode G1 and the third grounding electrode G3 are not shown in the diagram. Each grounding metal block C3 is electrically connected to the common area N3. Some of the grounding metal blocks C3 are electrically connected to the second grounding electrode G2, while the remaining grounding metal blocks are isolated from the second grounding electrode G2.

[0079] In the above implementation, this solution shifts the formation location of the augmented capacitor to the grounding metal block C3, while the signal metal block remains fully connected. The implementation principle is divided into two categories: the first category is "the grounding metal block is fully connected to the electrode and partially connected to the common area". Specifically, all grounding metal blocks C3 are electrically connected to the second grounding electrode G2, some grounding metal blocks are electrically connected to the common area N3 to anchor the potential of the common area, and the remaining grounding metal blocks are insulated from the common area N3. An augmented capacitor is formed at the isolation point, and this capacitor is connected in series with the equivalent capacitance of the PN junction.

[0080] The second type is "grounding metal blocks are fully connected to the common area and partially connected to the electrode". All grounding metal blocks C3 are electrically connected to the common area N3, partially connected to the second grounding electrode G2, and the rest are isolated to form an increased capacitance.

[0081] In the above implementation, the fully connected design of the signal metal block ensures lossless transmission of differential electrical signals. The induced capacitance is formed only through the grounding metal block and does not affect the signal transmission path. It can significantly reduce the total capacitance and increase the bandwidth while ensuring signal integrity. The partial connection design of the grounding metal block can anchor the common area potential and avoid potential fluctuations from affecting the electro-optic characteristics of the two interference arms, ensuring the consistency of modulation effect under different working conditions.

[0082] As another possible implementation method, such as Figure 9 As shown, the symmetrical coplanar waveguide electrode structure layer 10 also includes a bias electrode D1, and the bottom metal layer 20 also includes a bias metal block C4; the bias electrode D1 is electrically connected to the common area N3 through the bias metal block C4. Based on this, in this design, each first signal metal block C1 is electrically connected to the first signal electrode S1 and the first interference arm N1; each second signal metal block C2 is electrically connected to the second signal electrode S2 and the second interference arm N2; each ground metal block C3 is electrically connected to the second ground electrode G2, and all ground metal blocks C3 are insulated from the common area N3.

[0083] In the above implementation, this solution adds a bias electrode D1 and a bias metal block C4. The bias electrode D1 can be connected to an external DC bias power supply. The bias voltage is transmitted to the common region N3 of the PN junction modulation layer 30 through the bias metal block C4, changing the potential level of the common region N3, thereby adjusting the depletion layer width of the PN junction in the first interference arm N1 and the second interference arm N2. By optimizing the depletion layer width, the PN junction can be made to work in the region where the electro-optic effect is most sensitive, improving the efficiency of the electrical signal in regulating the refractive index, while improving the linear dynamic range of the modulator and avoiding modulation distortion caused by changes in signal amplitude.

[0084] Based on the above configuration of bias electrode D1 and bias metal block C4, as follows: Figure 9As shown, this scheme adopts a design of "grounded metal blocks fully connected to electrodes and fully isolated common area". Specifically, the first signal metal block C1 and the second signal metal block C2 are kept fully connected to ensure that the differential electrical signal is efficiently transmitted to the two interference arms. All grounded metal blocks C3 are electrically connected to the second ground electrode G2 and are completely insulated from the common area N3. At this time, the accumulating capacitance is formed by the isolation gap between the grounded metal block C3 and the common area N3, and the capacitance is evenly distributed. The potential of the common area N3 is completely adjusted by the bias electrode D1 through the bias metal block C4 to avoid the interference of the ground electrode on the potential of the common area and to precisely control the operating point of the PN junction.

[0085] In the above-described implementation, the bias electrode in this design applies a DC bias voltage to the common region through a bias metal block, which can precisely adjust the depletion layer width of the PN junction, enabling the PN junction to operate in the region most sensitive to electro-optic effects. This improves the efficiency of electrical signal modulation of optical phase. Simultaneously, the ground metal block is completely isolated from the common region, and the potential of the common region is controlled solely by the bias electrode, avoiding interference from potential fluctuations of the ground electrode on the operating point. This achieves high-precision adjustment of the operating point, thereby improving modulation sensitivity. The fully isolated design ensures that the accumulator capacitance is evenly distributed between the ground metal block and the common region, resulting in a stable total capacitance value and ensuring that the modulator bandwidth remains stable under different operating conditions. The independent bias control and ground shielding design effectively resist external electromagnetic interference and internal crosstalk, significantly enhancing anti-interference capabilities.

[0086] As another possible implementation method, such as Figure 10 As shown, based on the above-mentioned setting of bias electrode D1 and bias metal block C4, this scheme designs each first signal metal block C1 to be electrically connected to the first signal electrode S1 and the first interference arm N1; each second signal metal block C2 to be electrically connected to the second signal electrode S2 and the second interference arm N2; each ground metal block C3 to be electrically connected to the common area N3, and all ground metal blocks in the plurality of ground metal blocks C3 are insulated from the second ground electrode G2.

[0087] In the above implementation, this solution adopts a structure of "grounding metal blocks fully connected to the common area and fully isolated electrodes". Specifically, the first signal metal block C1 and the second signal metal block C2 are fully connected to ensure signal transmission; all grounding metal blocks C3 are electrically connected to the common area N3, and are completely insulated from the second grounding electrode G2. The accumulating capacitance is formed by the isolation gap between the grounding metal block C3 and the second grounding electrode G2; the potential of the common area N3 is initially anchored by the grounding metal block C3, and at the same time, a fine-tuning voltage is applied by the bias electrode D1 to achieve precise control of the potential of the common area N3.

[0088] In the above implementation scheme, the grounding metal block is fully connected to the common area to initially anchor the potential of the common area. The bias electrode applies a fine-tuning voltage to achieve stable and precise adjustment of the potential, ensuring the consistency of the modulation effect. The grounding metal block is completely isolated from the electrode layer, and the augmentation capacitor and the grounding path are independent of each other, avoiding signal leakage from the grounding path from affecting the performance of the augmentation capacitor and further reducing signal loss.

[0089] In an optional embodiment of this example, the scheme further designs a symmetrical coplanar waveguide electrode structure layer 10 and the bottom metal layer 20 connected by metal vias (for example, the first signal electrode S1 and each of the first signal metal blocks C1 below it are connected by metal vias). The metal vias are vertical through-hole structures, which can realize low impedance and low loss electrical connection between the two metal structures and avoid signal attenuation and impedance mismatch caused by planar connection.

[0090] The bottom metal layer 20 and the PN junction modulation layer 30 are connected by metal contact holes (for example, each first signal metal block C1 and its lower first interference arm N1 are connected by metal contact holes). The metal contact holes penetrate into the doped region of the PN junction modulation layer to ensure good ohmic contact between the metal and the semiconductor, reduce contact resistance, and improve the efficiency of electrical signal transmission.

[0091] In the above implementation scheme, the symmetrical coplanar waveguide electrode structure layer 10 and the bottom metal layer 20 are connected by metal vias. The vertical low impedance connection is achieved through the metal vias. Compared with the planar connection, the transmission distance is shorter, the contact resistance is smaller, and the electrical signal loss is significantly reduced. The bottom metal layer 20 and the PN junction modulation layer 30 are connected by metal contact holes. The metal contact holes penetrate into the PN junction doped region to form a good ohmic contact, avoiding signal attenuation and heat generation caused by excessive contact resistance, and improving connection stability and device reliability.

[0092] In an optional implementation of this embodiment, please refer to Figures 5 to 11 The first interference arm N1 of the PN junction modulation layer 30 designed in this scheme can be based on the first N-type heavily doped region N11, the first N-type medium doped region N12, the first N-type lightly doped region N13, the first P-type lightly doped region P11, the first P-type medium doped region P12, and the P-type heavily doped region Pn; the second interference arm N2 is based on the P-type heavily doped region Pn, the second P-type medium doped region P22, the second P-type lightly doped region P21, the second N-type lightly doped region N23, the second N-type medium doped region N22, and the second N-type heavily doped region N21.

[0093] Among them, when multiple first signal metal blocks C1 are connected to the first interference arm N1, they are connected to the first N-type heavily doped region N11; when multiple second signal metal blocks C2 are connected to the second interference arm N2, they are connected to the second N-type heavily doped region N21.

[0094] In the above implementation, this scheme optimizes the electric field distribution and capacitance characteristics based on gradient doping: the first interference arm adopts a gradient doping structure of "first N-type heavily doped region N11 → first N-type medium doped region N12 → first N-type light doped region N13 → first P-type light doped region P11 → first P-type medium doped region P12 → P-type heavily doped region Pn (common region)" to form a continuous PN junction transition region; the second interference arm N2 adopts a symmetrical gradient doping structure of "P-type heavily doped region Pn (common region) → second P-type medium doped region P22 → second P-type light doped region P21 → second N-type light doped region N23 → second N-type medium doped region N22 → second N-type heavily doped region N21" to make the electro-optic characteristics of the two interference arms completely symmetrical. Gradient doping design can increase the depletion layer area of ​​the PN junction and reduce the capacitance density per unit area, thereby reducing the equivalent capacitance of the PN junction. At the same time, the uniform electric field distribution can improve the efficiency of the electrical signal in regulating the refractive index, further reducing the transmission loss of the electrical signal. In addition, the first and second heavily doped N-type regions are electrically connected to the first and second signal metal blocks, respectively, to ensure that the electrical signal can be efficiently injected into the interferometer arm.

[0095] This application also provides a silicon-based modulator, such as Figure 12 As shown, the silicon-based modulator may include a substrate layer 1, an insulating layer 2, a cladding layer 3, and an electro-optic modulation structure 4 according to any of the optional embodiments described above. The insulating layer 2 is disposed on the substrate layer 1, the cladding layer 3 is disposed on the insulating layer 2, and the electro-optic modulation structure 4 is disposed within the cladding layer 3. The cladding layer 3 is used to cover the electro-optic modulation structure 4 for light confinement and isolation. The substrate layer 1 may be made of silicon; the insulating layer 2 may be made of any insulating material; and the cladding layer 3 may be made of an insulating material such as silicon dioxide.

[0096] In the silicon-based modulator designed above, the substrate layer 1 is made of high-purity silicon material, providing mechanical support and a heat conduction path for the entire device, ensuring the heat dissipation stability during device operation. The insulating layer 2 is disposed between the substrate layer 1 and the cladding layer 3, which can isolate the substrate layer 1 and the cladding layer 3, avoiding the influence of bottom factors on the electro-optic modulation effect, and reducing the leakage loss of optical signal to the substrate layer. The cladding layer 3 is made of insulating materials such as silicon dioxide, covering the electro-optic modulation structure 4. On the one hand, it can support the various structural components within the electro-optic modulation structure 4, and on the other hand, it can confine the optical signal within the electro-optic modulation structure 4 for transmission, reducing light scattering loss, and at the same time, it can provide physical protection for the electro-optic modulation structure 4. The electro-optic modulation structure 4 is embedded in the cladding layer. Through the cooperation of the bottom metal layer 20 and the upper and lower structures, it realizes efficient transmission of electrical signals and phase modulation of optical signals, and finally completes the electro-optic conversion function.

[0097] The silicon-based modulator designed above, because it includes the electro-optic modulation structure described above to achieve phase modulation of the optical signal, can solve the problem of insufficient bandwidth of the existing GGSSG structure MZM and improve the bandwidth of the output signal of the silicon-based modulator.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An electro-optic modulation structure, characterized in that, The electro-optic modulation structure includes a symmetrical coplanar waveguide electrode structure layer, a bottom metal layer, and a PN junction modulation layer; the bottom metal layer is disposed between the symmetrical coplanar waveguide electrode structure layer and the PN junction modulation layer, the symmetrical coplanar waveguide electrode structure layer is electrically connected to the bottom metal layer, and the bottom metal layer is electrically connected to the PN junction modulation layer; The symmetrical coplanar waveguide electrode structure layer is used to receive the target differential electrical signal and transmit the target differential electrical signal to the PN junction modulation layer through the bottom metal layer; The bottom metal layer is used to form an augmentation capacitor in series with the symmetrical coplanar waveguide electrode structure layer or the PN junction modulation layer, thereby reducing the transmission loss of the target differential electrical signal. The PN junction modulation layer is used to adjust the waveguide refractive index based on the target differential electrical signal, wherein the adjusted waveguide refractive index is used to perform phase modulation on the optical signal to be modulated. The bottom metal layer comprises a metal block array formed by multiple parallel metal blocks; each metal block in the metal block array is electrically connected to the PN junction modulation layer; some metal blocks in the metal block array are electrically connected to the symmetrical coplanar waveguide electrode structure layer, while the remaining metal blocks are insulated from the symmetrical coplanar waveguide electrode structure layer to form the augmented capacitance. Alternatively, each metal block in the metal block array is electrically connected to the symmetrical coplanar waveguide electrode structure layer; some metal blocks in the metal block array are electrically connected to the PN junction modulation layer, while the remaining metal blocks are insulated from the PN junction modulation layer to form the augmented capacitance.

2. The electro-optic modulation structure according to claim 1, characterized in that, The symmetrical coplanar waveguide electrode structure layer includes a first ground electrode, a first signal electrode, a second ground electrode, a second signal electrode, and a third ground electrode arranged in parallel. The first signal electrode is disposed between the first ground electrode and the second ground electrode, and the second signal electrode is disposed between the second ground electrode and the third ground electrode. The first signal electrode and the first ground electrode are symmetrically disposed with respect to the second ground electrode, as are the second signal electrode and the third ground electrode. The bottom metal layer includes a plurality of first signal metal blocks, a plurality of second signal metal blocks, and a plurality of ground metal blocks. The PN junction modulation layer includes a first interference arm, a second interference arm, and a common area. The plurality of first signal metal blocks are disposed between the first signal electrode and the first interference arm, the plurality of second signal metal blocks are disposed between the second signal electrode and the second interference arm, and the plurality of ground metal blocks are disposed between the second ground electrode and the common area.

3. The electro-optic modulation structure according to claim 2, characterized in that, Each of the first signal metal blocks is electrically connected to the first signal electrode; some of the first signal metal blocks are electrically connected to the first interference arm, while the remaining first signal metal blocks are insulated from the first interference arm. Each of the second signal metal blocks is electrically connected to the second signal electrode. Some of the plurality of second signal metal blocks are electrically connected to the second interference arm, while the remaining second signal metal blocks are insulated from the second interference arm. Each of the grounding metal blocks is electrically connected to the second grounding electrode and the common area; Among them, the remaining first signal metal block and the remaining second signal metal block are metal blocks that are positioned opposite each other.

4. The electro-optic modulation structure according to claim 2, characterized in that, Each of the first signal metal blocks is electrically connected to the first interference arm; some of the first signal metal blocks are electrically connected to the first signal electrode, while the remaining first signal metal blocks are insulated from the first signal electrode. Each of the second signal metal blocks is electrically connected to the second interference arm. Some of the second signal metal blocks are electrically connected to the second signal electrode, while the remaining second signal metal blocks are insulated from the second signal electrode. Each of the grounding metal blocks is electrically connected to the second grounding electrode and the common area; Among them, the remaining first signal metal block and the remaining second signal metal block are metal blocks that are positioned opposite each other.

5. The electro-optic modulation structure according to claim 2, characterized in that, Each of the first signal metal blocks is electrically connected to the first signal electrode and the first interference arm, and each of the second signal metal blocks is electrically connected to the second signal electrode and the second interference arm; Each of the grounding metal blocks is electrically connected to the second grounding electrode; some of the grounding metal blocks are electrically connected to the common area, while the remaining grounding metal blocks are insulated from the common area; or, each of the grounding metal blocks is electrically connected to the common area, some of the grounding metal blocks are electrically connected to the second grounding electrode, while the remaining grounding metal blocks are isolated from the second grounding electrode.

6. The electro-optic modulation structure according to claim 2, characterized in that, The symmetrical coplanar waveguide electrode structure layer further includes a bias electrode, and the bottom metal layer further includes a bias metal block; the bias electrode is electrically connected to the common area through the bias metal block.

7. The electro-optic modulation structure according to claim 6, characterized in that, Each of the first signal metal blocks is electrically connected to the first signal electrode and the first interference arm; Each of the second signal metal blocks is electrically connected to the second signal electrode and the second interference arm; Each of the grounding metal blocks is electrically connected to the second grounding electrode, and all of the plurality of grounding metal blocks are insulated from the common area.

8. The electro-optic modulation structure according to claim 7, characterized in that, Each of the first signal metal blocks is electrically connected to the first signal electrode and the first interference arm; Each of the second signal metal blocks is electrically connected to the second signal electrode and the second interference arm; Each of the grounding metal blocks is electrically connected to the common area, and all of the plurality of grounding metal blocks are insulated from the second grounding electrode.

9. The electro-optic modulation structure according to claim 2, characterized in that, The first interference arm is composed of a first N-type heavily doped region, a first N-type medium doped region, a first N-type lightly doped region, a first P-type lightly doped region, a first P-type medium doped region, and a P-type heavily doped region; The second interference arm is composed of a P-type heavily doped region, a second P-type moderately doped region, a second P-type lightly doped region, a second N-type lightly doped region, a second N-type moderately doped region, and a second N-type heavily doped region; wherein, the P-type heavily doped region is the common region; The first N-type heavily doped region is used to be electrically connected to the plurality of first signal metal blocks, and the second N-type heavily doped region is used to be electrically connected to the plurality of second signal metal blocks.

10. The electro-optic modulation structure according to claim 1, characterized in that, The symmetrical coplanar waveguide electrode structure layer is electrically connected to the bottom metal layer through a metal via, and the bottom metal layer is electrically connected to the PN junction modulation layer through a metal contact hole.

11. A silicon-based modulator, characterized in that, The silicon-based modulator includes a substrate layer, an insulating layer, a cladding layer, and the electro-optic modulation structure according to any one of claims 1-10; The insulating layer is disposed on the substrate layer, the cladding layer is disposed on the insulating layer, and the electro-optic modulation structure is disposed within the cladding layer; The cladding is used to cover the electro-optic modulation structure for light confinement and isolation.

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