N-type driving low dropout linear regulator with bootstrap gate voltage structure
By using an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure and employing the cyclic charging and discharging technology of an error amplifier and a gate voltage bootstrap capacitor array, the problem of limited output voltage is solved, achieving low power consumption, small area, high stability, and high reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-03-10
AI Technical Summary
Existing low-dropout linear regulators, when using NMOS as the driver transistor, suffer from limited output voltage, high power consumption and area overhead, and insufficient stability and reliability, especially in low-power applications.
The N-type driven low-dropout linear regulator with a bootstrap gate voltage structure generates a control voltage through an error amplifier. It uses a gate voltage bootstrap capacitor array to charge and discharge in a specific time sequence to gradually raise the gate voltage of the N-type drive transistor in the output stage. An improved gate voltage bootstrap switch ensures the transmission of the power supply voltage signal.
It improves the stability of the output voltage close to the input voltage, reduces power consumption and layout area, while enhancing the reliability and stability of the regulator and avoiding the introduction of an additional charge pump circuit.
Smart Images
Figure CN121635607A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit power management, specifically to an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure. Background Technology
[0002] Currently, low-dropout regulators (LDOs) typically use PMOS or NMOS transistors as output drivers. Traditionally, LDOs designed for low-dropout applications use PMOS transistors as drivers, but NMOS transistors are more suitable for applications requiring high current output and high transient response. However, because the output voltage of an LDO driven by an NMOS transistor is inherently lower than the gate voltage of the power transistor by a threshold voltage, and the gate voltage is limited by the error amplifier in the preceding stage to be at least one saturation drop below the input voltage, the output voltage is thus lower than the input voltage by one threshold voltage plus one saturation drop.
[0003] To address the aforementioned issues, traditional methods often introduce a charge pump. This involves using an N-type LDO with a charge pump structure to pump the gate voltage of the power transistor to the input voltage or even higher, thereby increasing the output voltage. While this approach solves the problem of a large voltage drop across the power transistor during conduction, it significantly increases the overall power consumption and layout area of the LDO. Furthermore, the introduction of the charge pump negatively impacts the LDO's stability, robustness, and its effectiveness under varying load conditions, making it unsuitable for low-power applications such as handheld devices. Therefore, designing an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure is essential to reduce area overhead, lower power consumption, and simultaneously improve stability and reliability. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention proposes an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure, which mainly solves the problem that existing technologies struggle to maintain high stability and reliability while reducing area overhead and power consumption.
[0005] The technical solution for realizing the present invention is: an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure, comprising an error amplifier, a gate voltage bootstrap capacitor array, and an output stage;
[0006] The error amplifier has its input terminal connected to a reference voltage V. bg and feedback voltage V fb The output terminal is connected to the left input terminal of the gate voltage bootstrap capacitor array, and the control voltage V is generated by comparing the difference between the reference voltage and the feedback voltage. A As the output of the error amplifier;
[0007] The gate voltage bootstrap capacitor array includes a main flying capacitor CG and two slave flying capacitors C1 and C2. Slave flying capacitor C1 is above the main flying capacitor CG, and slave flying capacitor C2 is below the main flying capacitor CG. Each slave flying capacitor and the main flying capacitor CG form a sub-circuit. Each sub-circuit contains four clock-controlled gate voltage bootstrap switches S1, S2, S1D, and S2D. The inputs of the sub-circuit are a reference voltage and GND. The left side of the gate voltage bootstrap capacitor array is connected to the control voltage V output by the error amplifier. A The right side is connected to the gate of the output stage N-type transistor and outputs the gate voltage V. B ;
[0008] Under the control of a clock signal, the bootstrap gate capacitor array operates according to a specific time cycle. It gradually raises the gate voltage by transferring charge through alternating parallel connections between flying capacitors C1 and C2 and the main flying capacitor CG. The operation of the bootstrap gate capacitor array, controlled by the clock signal according to a specific time cycle, can be divided into four stages: t1 is the initial disconnection period, t2 is the charge transfer period from flying capacitor C1 (i.e., the charging period from flying capacitor C2), t3 is the transition disconnection period, and t4 is the charge transfer period from flying capacitor C2 (i.e., the charging period from flying capacitor C1). During time t1, all eight switches in the bootstrap gate capacitor array are disconnected. This stage ensures that all switches are in the disconnected state, preventing charge transfer between capacitors. During time t2, switches S1 and S1D in the bootstrap gate capacitor array are closed, while switches S2 and S2D are open. At this time, for the flyover capacitor C1, its two ends are connected to the two ends of the main flyover capacitor CG, realizing the redistribution of charge. For the flyover capacitor C2, its two ends are connected to GND and Vref, respectively, and capacitor C2 is charged to Vref. During time period t3, C1 and CG are disconnected, and C2 and GND and the reference voltage Vref are disconnected. During this stage, all switches are turned off to prevent charge transfer between capacitors. During time period t4, switches S1 and S1D in the bootstrap gate voltage capacitor array are turned off, and switches S2 and S2D are closed. At this time, for the flyover capacitor C1, its two ends are connected to GND and Vref, respectively, charging capacitor C1 and preparing for the charge distribution of the next cycle. At the same time, the two ends of the flyover capacitor C2 are connected to the two ends of the main flyover capacitor, realizing the redistribution of charge. Starting from t5, the working state of time periods t1 to t4 above is repeated to form a "ping-pong" charging. After multiple cycles, the potential difference across CG gradually approaches Vref, and V... B Gradually increase the voltage to meet the conduction requirements of N1;
[0009] After the gate voltage is raised through the above-described cycle, the gate voltage of the output stage transistor may exceed the power supply voltage of the switch. To ensure the circuit operates normally, the gate voltage bootstrap switch is improved to transmit an input signal higher than the power supply voltage. The improved gate voltage bootstrap switch includes 13 transistors M1 to M12 and MS, bootstrap capacitor Cb and sampling capacitor CS, ground voltage VSS, and input voltage V. in Output voltage V out Power supply voltage VDD, clock signal CK; The working state of the improved gate voltage bootstrap switch is controlled by the clock signal CK, and there are two working states: CK low level and CK high level.
[0010] When CK is low, transistor M6 is turned on, and the lower plate of bootstrap capacitor Cb is pulled down to ground voltage VSS; transistors M10 and M11 are turned on, the gate of transistor M7 is pulled to ground voltage VSS, M7 is turned on, and the upper plate of bootstrap capacitor Cb is charged to the power supply voltage VDD; transistor M3 is turned on at this time, and the drain of transistor M4 is pulled up to VDD, so M4 is turned on; transistors M3, M4, and M5 are equivalent to simple inverters, maintaining the function of a traditional gate voltage bootstrap switch; when CK is high, transistor M3 is turned off, M5 is turned on, the voltage at node c is equal to the voltage at node a, M4 is turned off and cuts off the path of leakage from M3 to VDD caused by the voltage at node c being higher than the power supply voltage, thus avoiding current backflow;
[0011] The output stage includes an N-type transistor N1, a first resistor R1, a second resistor R2, and a load capacitor C. out The drain of N1 is connected to the input voltage, the source to the output voltage, and the gate to the gate voltage V output by the bootstrap capacitor array. B The first resistor R1 and the second resistor R2 are connected in series between the output voltage and GND to achieve voltage division and output feedback voltage V. fb This forms a negative feedback loop with the error amplifier;
[0012] Compared with the prior art, the beneficial effects of this invention are as follows: This invention compares the reference voltage and the feedback voltage using an error amplifier to output a control voltage; the gate voltage bootstrap capacitor array is cyclically charged and discharged according to a certain timing sequence, alternately charging two flying capacitors to the reference voltage and then connecting them in parallel with the main flying capacitor to transfer charge, gradually raising the gate voltage of the N-type driver transistor in the output stage, and generating a feedback voltage by reasonably setting the ratio of the output stage resistors to form a closed-loop feedback, which solves the problem of limited output voltage, makes the output voltage close to the input voltage, improves the stability of the system, eliminates the need for an additional charge pump circuit, and reduces power consumption while reducing the layout area; the improved gate voltage bootstrap switch blocks current backflow by adding a protection transistor to ensure the transmission of the over-power supply voltage signal, improving the reliability of the voltage regulator. Attached Figure Description
[0013] Figure 1 This is a circuit diagram of an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure, as described in an embodiment of this application.
[0014] Figure 2 This is a timing diagram of the gate voltage bootstrap capacitor array in an embodiment of this application;
[0015] Figure 3 This is the circuit diagram corresponding to time t2 in the embodiments of this application;
[0016] Figure 4 This is the circuit diagram corresponding to time t4 in the embodiments of this application;
[0017] Figure 5 This is a circuit diagram of a gate voltage bootstrap switch with backflow protection, in which the input signal is higher than the power supply voltage in an embodiment of this application. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0019] like Figure 1 As shown, a specific embodiment of the present invention discloses an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure, including an error amplifier, a gate voltage bootstrap capacitor array, and an output stage;
[0020] The error amplifier has its input terminal connected to a reference voltage V. bg and feedback voltage V fb The output terminal is connected to the left input terminal of the gate voltage bootstrap capacitor array, and the control voltage V is generated by comparing the difference between the reference voltage and the feedback voltage. A As the output of the error amplifier;
[0021] The gate voltage bootstrap capacitor array includes a main flying capacitor CG and two slave flying capacitors C1 and C2. Slave flying capacitor C1 is above the main flying capacitor CG, and slave flying capacitor C2 is below the main flying capacitor CG. Each slave flying capacitor and the main flying capacitor CG form a sub-circuit. Each sub-circuit contains four clock-controlled gate voltage bootstrap switches S1, S2, S1D, and S2D. The inputs of the sub-circuit are a reference voltage and GND. The left side of the gate voltage bootstrap capacitor array is connected to the control voltage V output by the error amplifier. A The output on the right side is connected to the gate of the N-type transistor, and the gate voltage V is raised by the capacitor charging and discharging timing. B ;
[0022] The output stage includes an N-type transistor N1, a first resistor R1, a second resistor R2, and a load capacitor C. outThe drain of N1 is connected to the input voltage, the source to the output voltage, and the gate to the gate voltage V output by the bootstrap capacitor array. B The first resistor R1 and the second resistor R2 are connected in series between the output voltage and GND to achieve voltage division and output feedback voltage V. fb This forms a negative feedback loop with the error amplifier;
[0023] This embodiment provides an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure. An error amplifier compares the reference voltage with the feedback voltage to output a control voltage. A gate voltage bootstrap capacitor array is cyclically charged and discharged according to a specific timing sequence. Two flying capacitors are alternately charged to the reference voltage and then connected in parallel with the main flying capacitor to transfer charge, gradually raising the gate voltage of the N-type driver transistor in the output stage. A feedback voltage is generated by appropriately setting the ratio of the output stage resistors, forming a closed-loop feedback. This solves the problem of limited output voltage, making the output voltage close to the input voltage, improving system stability, eliminating the need for an additional charge pump circuit, and reducing power consumption while minimizing layout area. An improved gate voltage bootstrap switch adds a protection transistor to block current backflow, ensuring overvoltage signal transmission and improving the regulator's reliability.
[0024] The error amplifier has its input terminal connected to a reference voltage V. bg and feedback voltage V fb The output terminal is connected to the left input terminal of the gate voltage bootstrap capacitor array, and the control voltage V is generated by comparing the difference between the reference voltage and the feedback voltage. A As the output of the error amplifier;
[0025] In some preferred embodiments, the error amplifier receives a reference voltage V. bg and the feedback voltage V from the output stage after being divided by the first resistor R1 fb By amplifying the reference voltage V bg and feedback voltage V fb The small difference between them is used to obtain the control voltage V. A As the output of the error amplifier, it is input to the left interface of the main flying capacitor CG in the gate voltage bootstrap capacitor array;
[0026] The gate voltage bootstrap capacitor array includes a main flying capacitor CG and two slave flying capacitors C1 and C2. Slave flying capacitor C1 is above the main flying capacitor CG, and slave flying capacitor C2 is below the main flying capacitor CG. Each slave flying capacitor and the main flying capacitor CG form a sub-circuit. Each sub-circuit contains four clock-controlled gate voltage bootstrap switches S1, S2, S1D, and S2D. The inputs of the sub-circuit are a reference voltage and GND. The left side of the gate voltage bootstrap capacitor array is connected to the control voltage V output by the error amplifier. A The right side is connected to the gate of the output stage N-type transistor and outputs the gate voltage V.B ;
[0027] In some preferred embodiments, the main flyover capacitor CG is used to transmit the control voltage V from the error amplifier. A And store charge to perform voltage boosting to obtain gate voltage V B Two flying capacitors C1 and C2 are used to alternately store the reference voltage V. bg The charge is transferred through a timing control switch connected in parallel with the main flying capacitor CG, gradually increasing the potential difference across the main flying capacitor CG. In the sub-circuit containing the main flying capacitor CG and the slave flying capacitor C1, gate voltage bootstrap switches S1 and S1D are used to control the parallel connection of the main flying capacitor CG and the slave flying capacitor C1, while gate voltage bootstrap switches S2 and S2D are used to control the connection between the slave flying capacitor C1 and the reference voltage V. ref The connection to GND; in the sub-circuit containing the main flying capacitor CG and the slave flying capacitor C2, gate voltage bootstrap switches S2 and S2D are used to control the parallel connection of the main flying capacitor CG and the slave flying capacitor C2, while gate voltage bootstrap switches S1 and S1D are used to control the connection between the slave flying capacitor C2 and the reference voltage V. ref Connection with GND;
[0028] In some preferred embodiments, the bootstrap gate voltage capacitor array operates in a specific time cycle under the control of a clock signal, gradually raising the gate voltage by transferring charge from the alternating parallel connection between flying capacitors C1 and C2 and the main flying capacitor CG;
[0029] like Figure 2 As shown, the bootstrap gate voltage capacitor array is controlled by a clock signal in a specific time cycle, which is divided into four stages: t1 is the initial disconnection period, t2 is the charge transfer period from flying capacitor C1 (i.e., the charging period from flying capacitor C2), t3 is the transition disconnection period, and t4 is the charge transfer period from flying capacitor C2 (i.e., the charging period from flying capacitor C1).
[0030] Specifically, in stage t1, all eight switches in the bootstrap gate capacitor array are turned off. At this time, the two slave flying capacitors C1 and C2 are disconnected from the main flying capacitor CG, and only the control voltage V is connected across CG. A and gate voltage V B There is no external charge input; this stage prepares for subsequent charge transfer by ensuring that all switches are in the open state and avoiding charge interference between different capacitors.
[0031] In stage t2, such as Figure 3 As shown, when switches S1 and S1D in the two sub-circuits of the bootstrap gate capacitor array are closed, the flyby capacitor C1 and the main flyby capacitor CG are connected in parallel. Since the initial potential difference of C1 is 0, the potential difference across CG remains unchanged after C1 and CG are connected in parallel. The control voltage VA and gate voltage V B To maintain stability, connect one end of the flying capacitor C2 to GND and the other end to the reference voltage V. ref At this point, C2 begins to charge until the voltage across its terminals reaches V. ref Let Q1 be the amount of charge stored in C2 at this time, and its value be expressed as C2*(V ref - GND); This stage is for charging C2 with a stable charge to prepare for charge transfer after C2 and CG are connected in parallel;
[0032] During stage t3, all switches are disconnected. At this time, C1 and CG are disconnected, and C2 and GND, along with the reference voltage V, are disconnected. ref When disconnected, the potential difference across the main flying capacitor remains constant, and there is no discharge path from the floating terminals of flying capacitor C2, thus maintaining the charge of Q1 unchanged; during this stage, by disconnecting all switches, charge surges during subsequent switch switching are avoided, preventing instantaneous current interference with voltage stability.
[0033] In stage t4, such as Figure 4 As shown, when switches S2 and S2D in the two sub-circuits of the bootstrap gate voltage capacitor array are closed, the flyby capacitor C1 and the main flyby capacitor CG in the upper half of the capacitor array are disconnected, and their two ends are connected to GND and V, respectively. ref Starting with the flying capacitor C1, since the two flying capacitors have the same capacitance, the amount of charge stored is equal to Q1. For the lower half of the capacitor array, the charged flying capacitor C2 is now connected in parallel with the main flying capacitor CG. According to the law of conservation of charge, the total charge before and after the parallel connection remains unchanged. At this time, the gate voltage V... B The value changes and becomes ((V) B -V A )*CG+(V ref -GND)*C2) / (CG+C2)+V A This stage raises the gate voltage V by connecting C2 in parallel with CG to transfer charge from C2. B ;
[0034] Starting from t5, the working state of the time period t1~t4 is repeated to form a "ping-pong" charging pattern. After multiple cycles, the potential difference across CG gradually approaches Vref, and V... B Gradually increase the voltage to meet the conduction requirements of N1;
[0035] In some preferred embodiments, after the gate voltage is raised through the above-described cycle, V B Gate voltage V B The value may have exceeded the power supply voltage of the switch. In order for the circuit to operate normally, the gate voltage bootstrap switch is improved to enable the transmission of input signals higher than the power supply voltage.
[0036] Specifically, such as Figure 5 As shown, the improved gate voltage bootstrap switch with reverse current protection, whose input signal is higher than the power supply voltage, includes 13 transistors M1 to M12 and MS, bootstrap capacitor Cb and sampling capacitor CS, ground voltage VSS, and input voltage V. in Output voltage V out Power supply voltage VDD, clock signal CK; The working state of the improved gate voltage bootstrap switch is controlled by the clock signal CK, and there are two working states: CK low level and CK high level.
[0037] When CK is low, the improved gate voltage bootstrap switch is in normal transmission state. Transistor M6 is turned on, and the lower plate of bootstrap capacitor Cb is pulled down to ground voltage VSS. Transistors M10 and M11 are turned on, and the gate of transistor M7 is pulled to ground voltage VSS, so M7 is turned on. The upper plate of bootstrap capacitor Cb is charged to the power supply voltage VDD, and the voltage difference across bootstrap capacitor Cb is maintained at VDD. Transistor M3 is turned on at this time, and the drain of transistor M4 is pulled up to VDD, so M4 is turned on. Transistors M3, M4, and M5 form an equivalent inverter, maintaining the function of the traditional gate voltage bootstrap switch.
[0038] When CK is high, the improved gate voltage bootstrap switch is in reverse-current protection mode, transistor M3 is off, M5 is on, the voltage at node c is equal to the voltage at node a, the gate of M4 is connected to node a, and the voltage difference between the gate and source of M4 is 0, which is the off state. When M4 is off, the path of leakage from M3 to VDD caused by the voltage at node c being higher than the power supply voltage is cut off, thus avoiding current reverse current.
[0039] The output stage includes an N-type transistor N1, a first resistor R1, a second resistor R2, and a load capacitor C. out The drain of N1 is connected to the input voltage, and the source is connected to the output voltage V. out The gate voltage V output from the gate voltage bootstrap capacitor array is connected to the gate voltage. B The first resistor R1 and the second resistor R2 are connected in series in the output voltage V. out A voltage divider is implemented between GND and the ground plane to output a feedback voltage V. fb This forms a negative feedback loop with the error amplifier;
[0040] In some preferred embodiments, the drain of the N-type transistor N1 is connected to the input voltage, and the gate is connected to the gate voltage V output by the gate voltage bootstrap capacitor array. B The source is connected to the output voltage V. out The first resistor R1 and the second resistor R2 are connected in series in the output voltage V. out The output feedback voltage V at the series node between GND and GND is... fbThe error amplifier, based on the closed-loop feedback principle, adjusts the ratio between the first resistor R1 and the second resistor R2 to control the output voltage V. out Adjustment is performed; the load capacitor is connected in series with the output voltage V. out Between GND and the circuit current, the output voltage V is suppressed by releasing charge to replenish the current when the circuit current fluctuates. out To reduce fluctuations and enhance the loop stability of the voltage regulator;
[0041] The N-type driven low-dropout linear regulator employing the bootstrap gate voltage structure in this embodiment of the invention outputs a control voltage by comparing the reference voltage and the feedback voltage through an error amplifier. The gate voltage bootstrap capacitor array is cyclically charged and discharged according to a certain timing sequence, alternately charging two flying capacitors to the reference voltage and then connecting them in parallel with the main flying capacitor to transfer charge, gradually raising the gate voltage of the N-type driver transistor in the output stage. By reasonably setting the ratio of the output stage resistors, a feedback voltage is generated to form a closed-loop feedback, solving the problem of limited output voltage, making the output voltage close to the input voltage, improving the stability of the system, eliminating the need for an additional charge pump circuit, and reducing power consumption while shrinking the layout area. The improved gate voltage bootstrap switch blocks current backflow by adding a protection transistor, ensuring the transmission of the over-power supply voltage signal and improving the reliability of the regulator.
[0042] In this embodiment, an application-specific integrated circuit is also provided to implement an N-type driven low-dropout linear regulator with a bootstrap gate voltage structure disclosed in this embodiment;
[0043] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An N-type driving low-dropout linear regulator with bootstrap gate voltage structure, characterized in that, The error amplifier receives a reference voltage and a feedback voltage, and outputs a control voltage to the left input terminal of the gate voltage self-boosting capacitor array; the gate voltage self-boosting capacitor array comprises a main flying capacitor, two slave flying capacitors and a plurality of gate voltage self-boosting switches, receives the control voltage and outputs a boosted gate voltage; the improved gate voltage self-boosting switch is integrated in the switch control channel of the gate voltage self-boosting capacitor array, comprises a P-type transistor M3, an N-type transistor M5, a self-boosting capacitor and a protection tube P-type transistor M4, receives the gate voltage, transmits the gate voltage and blocks current backflow; the output stage comprises an N-type transistor, a first resistor, a second resistor and a load capacitor, the N-type transistor receives the gate voltage transmitted by the improved gate voltage self-boosting switch, the first resistor and the second resistor are connected in series to generate a feedback voltage which is fed back to the error amplifier, and the load capacitor is connected in parallel between the output voltage and the ground.
2. The N-type driving low-dropout linear regulator with bootstrap gate voltage structure of claim 1, wherein, The source and the drain of the protection tube of the improved gate voltage self-boosting switch are connected with the drain of the N-type transistor M5 and the drain of the P-type transistor M3 respectively, the gate of the protection tube is connected with the lower plate of the self-boosting capacitor, and the protection tube is turned on and turned off to realize the anti-backflow protection; The improved gate voltage self-boosting switch is controlled by a clock signal, when the clock signal is low, the protection tube M4 is turned on, and the transistors M3-M5 constitute an inverter; when the clock signal is high, the protection tube is turned off to cut off the current backflow path.
3. The N-type driving low-dropout linear regulator with bootstrap gate voltage structure of claim 2, wherein, The two slave flying capacitors of the gate voltage self-boosting capacitor array are located above and below the main flying capacitor respectively, each slave flying capacitor and the main flying capacitor form a sub-circuit, and each sub-circuit comprises four gate voltage self-boosting switches controlled by a clock, and the other two ends of the sub-circuit are connected with the reference voltage and the ground respectively; The gate voltage self-boosting switches are controlled periodically, and the parallel connection of the slave flying capacitors and the main flying capacitor is alternately realized to complete the charge transfer, and the connection of the slave flying capacitors and the reference voltage and the ground is alternately realized to complete the charging.
4. The N-type driving low-dropout linear regulator with bootstrap gate voltage structure of claim 3, wherein, The drain of the N-type transistor of the output stage is connected with the input voltage, the source is connected with the output voltage, and the gate receives the boosted gate voltage transmitted by the improved gate voltage self-boosting switch; The first resistor and the second resistor of the output stage are connected in series between the output voltage and the ground, and the feedback voltage is led out at the series connection node.
5. The N-type driving low-dropout linear regulator with bootstrap gate voltage structure of claim 4, wherein, The slave flying capacitors of the gate voltage self-boosting capacitor array are first connected with the reference voltage and the ground to charge, and then connected in parallel with the main flying capacitor to realize the charge transfer.
6. The N-type driving low-dropout linear regulator with bootstrap gate voltage structure of claim 5, wherein, The error amplifier compares the difference between the reference voltage and the feedback voltage, amplifies the difference and outputs a control voltage to the gate voltage self-boosting capacitor array.
7. The N-type driving low-dropout linear regulator with bootstrap gate voltage structure of claim 6, wherein, The period control of the gate voltage self-boosting capacitor array comprises an initial disconnection period, a slave flying capacitor charging period, a transition disconnection period, a flying capacitor charging period and a subsequent initial period.