A noise reduction filter and soft start multiplexing circuit

Abstract

The present application relates to the field of integrated circuits, in particular to a noise reduction filter and soft start multiplexing circuit, which comprises a noise reduction capacitor controller and a soft start multiplexing module, wherein the soft start multiplexing module charges an external capacitor by using a current source according to two reference voltages provided by a reference voltage module under the condition of enabling normal; when the charging reaches the flip threshold of the internal comparator of the soft start multiplexing module, the charging is stopped by the noise reduction capacitor controller, and an RC filter is used to filter the reference voltage to obtain a low-noise reference voltage. The present application introduces a soft start power-on controller and a reference noise reduction filter, and can save the port and chip area, so as to better control the research and development cost of the chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a noise reduction filtering and soft-start multiplexing circuit. Background Technology

[0002] Linear drop-out regulators (LDOs) are widely used in complete systems as secondary power supplies due to their excellent current capability and ripple suppression. In practical applications, traditional LDOs, due to their loop response, experience overshoot at the output because the loop response is slower than the reference voltage during power-on. This overshoot can cause electrical stress damage to downstream systems under prolonged overshoot conditions, which is unacceptable. Therefore, a soft-start circuit is incorporated into the design of LDOs to address the overshoot problem. Traditional soft-start circuits typically add a unity-gain buffer to the reference voltage terminal. The reference voltage, after passing through the buffer, then serves as the LDO's reference voltage. The buffer's reference input transistors are connected to a power-on offset transistor pair, acting as the soft-start power-on control unit. The core of this control unit is a capacitor connected to the offset transistor pair, which controls the power-on time of the soft-start circuit. However, this structure has a drawback: due to the limited gain of the buffer, it cannot accurately reflect the reference voltage, and the large capacitor only serves as a time controller for soft-start power-on and cannot participate in the filtering and noise reduction of the reference voltage. Summary of the Invention

[0003] To address the problems existing in the prior art and reduce port and chip area, this invention proposes a noise reduction filtering and soft-start multiplexing circuit. The circuit includes a noise reduction capacitor controller and a soft-start multiplexing module. When the soft-start multiplexing module is enabled normally, it charges an external capacitor using a current source based on two reference voltages provided by the reference voltage module. When the charging reaches the toggling threshold of the comparator inside the soft-start multiplexing module, the noise reduction capacitor controller stops charging and performs RC filtering on the reference voltage to obtain a low-noise reference voltage.

[0004] The noise reduction filtering and soft-start multiplexing circuit provided by this invention introduces a circuit that can function as both a soft-start power-on controller and a reference noise reduction filter, while also saving port and chip area, thus better controlling chip development costs. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a traditional linear voltage regulator with soft start.

[0006] Figure 2 This is a schematic diagram of a traditional linear regulator circuit with soft start;

[0007] Figure 3This is a schematic diagram illustrating the principle of a noise reduction filtering and soft-start multiplexing circuit of the present invention applied to a linear regulator.

[0008] Figure 4 This is a schematic diagram of the circuit structure of a noise reduction filtering and soft-start multiplexing circuit according to the present invention;

[0009] Figure 5 This is a schematic diagram showing the noise simulation results of the present invention and the traditional structure;

[0010] Figure 6 This is a simulation diagram of the power-on soft start of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] This invention proposes a noise reduction filtering and soft-start multiplexing circuit. The circuit includes a noise reduction capacitor controller and a soft-start multiplexing module. When the soft-start multiplexing module is normally enabled, it charges an external capacitor using a current source based on two reference voltages provided by a reference voltage module. When the charging reaches the toggling threshold of the comparator inside the soft-start multiplexing module, the noise reduction capacitor controller stops charging and performs RC filtering on the reference voltage to obtain a low-noise reference voltage. When applied to an LDO, this invention provides a noise reduction filtering and soft-start multiplexing circuit for soft-start design during power-up. Simultaneously, the capacitor used in the soft-start power-up function acts as a noise reduction filter, increasing the compatibility of the single circuit in applications.

[0013] Appendix Figure 1 A traditional LDO with soft-start functionality includes a reference module, a soft-start module, an EA unit, and a feedback resistor unit. It mainly includes an error amplifier EA, a circuit composed of MOSFETs MP, a first feedback resistor R1, and a second feedback resistor R2. The reference serves as the LDO op-amp's reference. During power-up, because the loop establishment is slower than the reference establishment, overshoot occurs at the LDO output. To solve this problem, a soft-start module is added to the path connecting the reference to the LDO op-amp, slowing down the reference's power-up time and resolving the LDO power-up overshoot issue. However, traditional soft-start circuits are limited in function and lack noise reduction and filtering capabilities.

[0014] Appendix Figure 2 It is a traditional LDO soft-start module. Figure 2In this circuit, the first P-type MOSFET MP1 and the second P-type MOSFET MP2 serve as internal biases for the soft-start module. The first P-type MOSFET MP1 provides the charging current for the external capacitor C_ss. The second P-type MOSFET MP2 serves as the bias current for the operational amplifier (op-amp). The fifth P-type MOSFET MP5 acts as the control transistor for the soft-start. The sixth P-type MOSFET MP6 and the seventh P-type MOSFET MP7 serve as the first reference voltage Vref0 and the feedback input for the op-amp. The third N-type MOSFET MN3, the third P-type MOSFET MP3, and the fourth P-type MOSFET MP4 provide a negative feedback loop. Specifically, when the circuit is powered on, the main op-amp's loop has not yet been established, but the reference voltage has already been established. The additional fifth P-type MOSFET MP5 is used to bypass the loop establishment time. Figure 2 The structure is a basic soft-start circuit, but its function is limited. After startup, the operational amplifier gain is limited, resulting in low reference accuracy and no filtering function for the reference. In order to optimize this structure, a soft-start circuit with noise reduction filtering is introduced.

[0015] Figure 3 The invention provides an application scenario where the circuit is used between a reference voltage module and other external circuits to reduce noise and achieve soft-start of the reference voltage output by the reference voltage module. For example, in... Figure 3 This is used to provide a reference voltage for the inverting input of the error amplifier. Figure 3 The diagram provided only illustrates that the circuit of this invention consists of resistors, MOSFETs, current mirrors, and logic devices. Figure 3 The connection relationship in the middle is not the actual connection relationship of the present invention. The soft-start multiplexing module includes a constant current source, a power switch, and a comparator. The noise reduction capacitor controller outputs a control signal to control the power switch to turn on. When the power switch is turned on, the constant current source charges the external capacitor until the comparator's flip-flop threshold is reached. Then, the noise reduction capacitor controller outputs a low level to turn off the power switch, so that the external capacitor stops charging.

[0016] As an alternative implementation method, such as Figure 4 This invention utilizes a noise reduction, filtering, and soft-start multiplexing circuit to reduce noise and achieve soft-start for the two reference voltages output by the BANDGAP reference voltage module, namely the first reference voltage Vref0 and the second reference voltage Vref1. The power switch includes a first N-type MOSFET MN1, the comparator includes a first P-type MOSFET MP1 and a second P-type MOSFET MP2, and the soft-start multiplexing module further includes a tail current source composed of a third P-type MOSFET MP3, a fifth P-type MOSFET MP5, and a sixth P-type MOSFET MP6, and a current mirror load composed of a second N-type MOSFET MN2 and a third N-type MOSFET MN3.

[0017] The gate of the first N-type MOSFET is connected to the control signal output by the noise reduction capacitor controller, and the drain of the first N-type MOSFET is connected to the constant current source I. change The negative terminal of the constant current source is connected to the power supply terminal, the source of the first N-type MOS transistor is connected to the gate of the second P-type MOS transistor, the first reference voltage provided by the reference voltage module, and one end of the external voltage are connected together.

[0018] The gate of the second N-type MOS transistor is connected to its drain, the drain of the fifth P-type MOS transistor, and the gate of the third N-type MOS transistor. The source of the second N-type MOS transistor is connected to one end of the first resistor and the drain of the first P-type MOS transistor.

[0019] The drain of the third N-type MOSFET is connected to the drain of the sixth P-type MOSFET and serves as the output of the soft-start multiplexing module, which in turn serves as the input of the noise reduction capacitor controller; the source of the third N-type MOSFET is connected to one end of the second resistor and the drain of the second P-type MOSFET.

[0020] The gate of the first P-type MOS transistor is connected to the second reference voltage provided by the reference voltage module, and the source of the first P-type MOS transistor is connected to the drain of the third P-type MOS transistor and the source of the second P-type MOS transistor.

[0021] The gate of the third P-type MOSFET is connected to the gates of the fifth and sixth P-type MOSFETs, and is connected to the externally supplied bias current I. BIAS Connections: The drains of the third, fifth, and sixth P-type MOSFETs are connected to the power supply terminals.

[0022] The other end of the first resistor, the other end of the second resistor, and the other end of the external voltage are all connected to the ground terminal GND.

[0023] The noise reduction capacitor controller includes a seventh P-type MOSFET MP7, an eighth P-type MOSFET MP8, an OR unit, a first buffer Buffer0, a second buffer Buffer1, a first NAND_1, a second NAND_2, and a first inverter INV0, wherein:

[0024] The gate of the seventh P-type MOSFET is connected to the output of the first inverter. The source of the seventh P-type MOSFET and the source of the eighth P-type MOSFET are connected to the power supply terminal VIN. The drain of the seventh P-type MOSFET is connected to the output terminal of the soft-start multiplexing module and the input terminal of the first buffer.

[0025] The gate of the eighth P-type MOS transistor is connected to the output terminal of the first buffer and the input terminal of the first NAND arithmetic unit, and the drain of the eighth P-type MOS transistor is connected to the inverted signal output of the first buffer.

[0026] The output of the first NAND unit is connected to the input of the second buffer and the input of the second NAND unit.

[0027] The second enable signal ENN serves as the input to the second NAND operator, and the output of the second NAND operator is connected to the input of the first NAND operator.

[0028] The output of the second buffer serves as the input of the first inverter, and the output of the first inverter, i.e., endpoint C in the attached diagram, serves as the input of the OR operator.

[0029] The arithmetic logic unit (ALU) may receive the first enable signal ENN0 and the signal output from the first inverter, or the output of the ALU may be used as a control signal to turn on the power switch.

[0030] Once the reference is established, the reference voltage module outputs a first reference voltage Vref0 and a second reference voltage Vref1. At this time, the first reference voltage Vref0 > the second reference voltage Vref1. Since the first reference voltage Vref0 has a capacitance C... NR_SS This results in slow power-up. At this time, the first O-type MOSFET MP1 turns on, and the second P-type MOSFET MP2 turns off. The output terminal C of the first inverter in the noise reduction capacitor controller is at a high level. When the enable signal is normally enabled, the second enable signal ENN and the first enable signal ENN0 are at a low level. At this time, the switching transistor, i.e., the first N-type MOSFET MN1, turns on, and the current source supplies the external capacitor C. NR_SS During charging, when the charge reaches the comparator's toggling threshold, the output of the first inverter in the logic control module at point C becomes low, turning it off. This low level controls the first N-type MOSFET MN1 to turn off. At this time, C... NR_SS The capacitor stops charging, and the reference voltage is then RC filtered, resulting in a low-noise reference voltage. (Appendix) Figure 5 The comparison of the equivalent output noise voltage of the proposed structure and the traditional soft-start structure in simulation shows that the noise voltage of the proposed mechanism is reduced by 50% compared with that of the traditional structure; Appendix Figure 6 To simulate the power-on soft-start of a noise reduction filtering and soft-start multiplexing circuit according to the present invention, the simulation diagram shows that the time required for 90% power-on completion is 3ms.

[0031] In summary, the noise reduction filtering and soft-start multiplexing circuit of the present invention, through C NR_SSAn external capacitor, through an internal noise reduction and soft-start multiplexing module circuit, enables soft-start power-on delay and noise reduction filtering functions. In this invention, when the reference voltage is used as the operational amplifier's reference voltage, a soft-start circuit is introduced to prevent overshoot at the LDO output. Simultaneously, to reduce the output noise of the reference voltage, thereby reducing the overall noise of the LDO, this structure achieves both soft-start and noise reduction filtering functions within the same circuit. Compared to traditional LDOs, this enhances the versatility of a single circuit module, saves chip area in circuit design, and enables low-noise characteristics in applications, realizing two functions within a single module circuit.

[0032] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A noise reduction filtering and soft-start multiplexing circuit, characterized in that, This circuit is positioned between the reference voltage module and the external circuit using the reference voltage. It is used for noise reduction during the reference voltage process and soft-start of the circuit. The circuit includes a noise reduction capacitor controller, a soft-start multiplexing module, and an external capacitor. When the soft-start multiplexing module is enabled normally, it charges the external capacitor using a current source based on the two reference voltages provided by the reference voltage module. When the charging reaches the flip-flop threshold of the comparator inside the soft-start multiplexing module, the noise reduction capacitor controller stops charging and performs RC filtering on the reference voltage to obtain a low-noise reference voltage.

2. The noise reduction filtering and soft-start multiplexing circuit according to claim 1, characterized in that, The soft-start multiplexing module includes a constant current source, a power switch, and a comparator. The noise reduction capacitor controller outputs a control signal to control the power switch to turn on. When the power switch is on, the constant current source charges the external capacitor until the comparator's flip-flop threshold is reached. Then, the noise reduction capacitor controller outputs a low level to turn off the power switch, stopping the external capacitor from charging.

3. The noise reduction filtering and soft-start multiplexing circuit according to claim 2, characterized in that, In the soft-start multiplexing module, the power switch includes a first N-type MOSFET, the comparator includes a first P-type MOSFET and a second P-type MOSFET, and the soft-start multiplexing module also includes a tail current source composed of a third P-type MOSFET, a fifth P-type MOSFET, and a sixth P-type MOSFET, and a current mirror load composed of a second N-type MOSFET and a third N-type MOSFET, wherein: The gate of the first N-type MOS transistor is connected to the control signal output by the noise reduction capacitor controller. The drain of the first N-type MOS transistor is connected to the negative terminal of the constant current source. The positive terminal of the constant current source is connected to the power supply terminal. The source of the first N-type MOS transistor is connected to the gate of the second P-type MOS transistor, the first reference voltage provided by the reference voltage module, and one end of the external voltage. The gate of the second N-type MOS transistor is connected to its drain, the drain of the fifth P-type MOS transistor, and the gate of the third N-type MOS transistor. The source of the second N-type MOS transistor is connected to one end of the first resistor and the drain of the first P-type MOS transistor. The drain of the third N-type MOSFET is connected to the drain of the sixth P-type MOSFET and serves as the output of the soft-start multiplexing module, which in turn serves as the input of the noise reduction capacitor controller; the source of the third N-type MOSFET is connected to one end of the second resistor and the drain of the second P-type MOSFET. The gate of the first P-type MOS transistor is connected to the second reference voltage provided by the reference voltage module, and the source of the first P-type MOS transistor is connected to the drain of the third P-type MOS transistor and the source of the second P-type MOS transistor. The gate of the third P-type MOSFET is connected together with the gates of the fifth P-type MOSFET and the sixth P-type MOSFET, and is connected to the external bias current; the drains of the third P-type MOSFET, the fifth P-type MOSFET, and the sixth P-type MOSFET are connected to the power supply terminal. The other end of the first resistor, the other end of the second resistor, and the other end of the external voltage are all connected to the ground terminal.

4. The noise reduction filtering and soft-start multiplexing circuit according to claim 3, characterized in that, The first reference voltage provided by the reference voltage module is less than the second reference voltage provided by the reference voltage module.

5. The noise reduction filtering and soft-start multiplexing circuit according to claim 3, characterized in that, The noise reduction capacitor controller includes a seventh P-type MOSFET, an eighth P-type MOSFET, an OR operation unit, a first buffer, a second buffer, a first NAND operation unit, a second NAND operation unit, and a first inverter, wherein: The gate of the seventh P-type MOSFET is connected to the output of the first inverter, the source of the seventh P-type MOSFET and the source of the eighth P-type MOSFET are connected to the power supply terminal, and the drain of the seventh P-type MOSFET is connected to the output terminal of the soft-start multiplexing module and the input terminal of the first buffer. The gate of the eighth P-type MOS transistor is connected to the output terminal of the first buffer and the input terminal of the first NAND arithmetic unit, and the drain of the eighth P-type MOS transistor is connected to the inverted signal output of the first buffer. The output of the first NAND unit is connected to the input of the second buffer and the input of the second NAND unit. The second enable signal serves as the input to the second NAND operator, and the output of the second NAND operator is connected to the input of the first NAND operator. The output of the second buffer is used as the input of the first inverter, and the output of the first inverter is used as the input of the OR operator. The arithmetic logic unit (ALU) may receive the first enable signal and the signal output from the first inverter, or the output of the ALU may be used as a control signal to turn on the power switch.

6. The noise reduction filtering and soft-start multiplexing circuit according to claim 5, characterized in that, When the reference voltage module starts to provide the first reference voltage and the second reference voltage, and the first enable signal and the second enable signal are at low level, the first P-type MOSFET is turned on and the second P-type MOSFET is turned off, and the first inverter of the noise reduction capacitor controller outputs a high level.

7. A noise reduction filtering and soft-start multiplexing circuit according to claim 5 or 6, characterized in that, When the external capacitor is charged to the comparator's flip-flop threshold, the first inverter of the noise reduction capacitor controller outputs a low level to control the first N-type MOSFET to turn off, stopping the charging of the external capacitor.

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