Current mirror circuit for compensating current source to be calibrated
By using NMOS transistors and operational amplifiers in the current mirror circuit, the problem of inaccurate compensation current in the current mirror circuit is solved, achieving high accuracy in the current source calibration process and ensuring the precise addition of compensation current.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-10
AI Technical Summary
Existing current mirror circuits cannot accurately add the compensation current to the current source to be calibrated when compensating for the current, resulting in insufficient accuracy in the current source calibration process.
A current mirror consisting of NMOS transistors MN1 and MN2 is used, combined with an operational amplifier and a bias unit. The voltage at the input and output terminals of the current mirror is kept equal by a voltage regulation unit. The "virtual short" characteristic between the inverting and non-inverting input terminals of the operational amplifier is utilized to make the drain voltages of NMOS transistors MN1 and MN2 equal, thus avoiding the influence of channel length modulation effect.
It achieves precise compensation for the current source to be calibrated, improves the accuracy of the current source calibration process, and ensures that the difference between the output mirror current and the input current is within 10nA, thus ensuring that the compensation current is accurately added to the current source to be calibrated.
Smart Images
Figure CN121635623A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of current source calibration, and in particular relates to a current mirror circuit for compensating a current source to be calibrated. Background Technology
[0002] When performing current compensation on the current source Iu to be calibrated, a conventional current source compensation circuit, such as... Figure 1 As shown. The current output from the compensation current source Ical passes through a current mirror composed of NMOS transistors MN1 and MN2. The drain of NMOS transistor MN2 is then connected to the drain of NMOS transistor MN10, which forms the current source to be corrected, for combined output, thus achieving the compensation function. Due to the channel length modulation effect of MOS transistors, i.e., the leakage current I of the MOS transistor... d It will change with the voltage difference between its drain and source; in the above compensation method, the voltage V at node B B Determined by the upper bias circuit of the current Iout, i.e.: V B This can be considered a fixed value. Although the gate-source voltages of NMOS transistors MN1 and MN2 in the current mirror are the same, the drain voltage (i.e., the voltage at node A) of NMOS transistor MN1 is different. A The current will vary with the output current of the compensation current source Ical, resulting in the compensation current replicated at the drain of the NMOS transistor MN2 being inaccurate. Summary of the Invention
[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a current mirror circuit that can be used for compensation of a current source to be calibrated, so as to accurately add the compensation current generated by other modules to the current source to be calibrated and improve the accuracy of the current source calibration process.
[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A current mirror circuit for compensating a current source to be calibrated, comprising: The compensation current source Ical is used at the input terminal of the mirror; A current mirror is used to output a corresponding mirror current at its output terminal based on the compensation current source that provides the compensation current to the current output, and to compensate the current source Iu to be calibrated through the mirror current; and The voltage unit is used to provide a bias voltage for the current mirror and to maintain equal voltages at the input and output terminals of the current mirror.
[0005] Furthermore, the current mirror includes NMOS transistor MN1 and NMOS transistor MN2; the drain of NMOS transistor MN1 serves as the input terminal of the current mirror and is electrically connected to the compensation current source Ical; the drain of NMOS transistor MN2 serves as the output terminal of the current mirror and is electrically connected to the current source to be calibrated; the gate of NMOS transistor MN1 is electrically connected to the gate of NMOS transistor MN2; and the sources of both NMOS transistor MN1 and NMOS transistor MN2 are grounded.
[0006] Furthermore, both NMOS transistors MN1 and MN2 are fabricated using the TSMC 12nm FinFET process.
[0007] Furthermore, the current source Iu to be corrected is defined as an NMOS transistor MN10, the drain of the NMOS transistor MN10 is electrically connected to the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN10 is connected to the bias voltage Vbias0, and the source of the NMOS transistor MN10 is grounded.
[0008] Furthermore, the voltage unit includes a voltage regulation unit and a bias unit. The voltage regulation unit is used to maintain the voltage at the input and output terminals of the current mirror equal. The drains of NMOS transistor MN1 and NMOS transistor MN2 are electrically connected to the voltage regulation unit, respectively. The bias unit is used to provide operating bias voltage for the gates of NMOS transistor MN1 and NMOS transistor MN2.
[0009] Furthermore, the voltage regulation unit is defined as an operational amplifier, the inverting input terminal of the operational amplifier is electrically connected to the drain of NMOS transistor MN1, the non-inverting input terminal of the operational amplifier is electrically connected to the drain of NMOS transistor MN2, and the output terminal of the operational amplifier is electrically connected to the bias unit.
[0010] Furthermore, the operational amplifier includes PMOS transistor MP2, PMOS transistor MP3, NMOS transistor MN5, and NMOS transistor MN6; the sources of PMOS transistor MP2 and PMOS transistor MP3 are both electrically connected to the second bias current source Ibias2, and the gate of PMOS transistor MP2 is electrically connected to the drain of NMOS transistor MN1 as the inverting input terminal of the operational amplifier. The gate of the PMOS transistor MP3 is electrically connected to the drain of the NMOS transistor MN2 as the non-inverting input terminal of the operational amplifier. The drain of the PMOS transistor MP3 is electrically connected to the bias unit as the output terminal of the operational amplifier. The drain of the PMOS transistor MP3 is also electrically connected to the drain of the NMOS transistor MN6. The drain of the PMOS transistor MP2 is electrically connected to the drain of the NMOS transistor MN5, the gate of the NMOS transistor MN5, and the gate of the NMOS transistor MN6, respectively. The source of the NMOS transistor MN5 and the source of the NMOS transistor MN6 are both grounded.
[0011] Furthermore, the second bias current source Ibias2 includes a PMOS transistor MP4 and a PMOS transistor MP5. The source of the PMOS transistor MP4 is connected to the supply voltage VDD, the gate of the PMOS transistor MP4 is connected to the bias voltage Vbias1, and the drain of the PMOS transistor MP4 is electrically connected to the source of the PMOS transistor MP5. The gate of the PMOS transistor MP5 is connected to the bias voltage Vbias2, and the drain of the PMOS transistor MP5 is electrically connected to the sources of PMOS transistors MP2 and MP3.
[0012] Furthermore, the bias unit includes a PMOS transistor MP1, an NMOS transistor MN3, an NMOS transistor MN4, and a first bias current source Ibias1. The drain of the NMOS transistor MN1 is electrically connected to the compensation current source Ical through the NMOS transistor MN3. The drain of the NMOS transistor MN3 is electrically connected to the compensation current source Ical, the gate of the NMOS transistor MN3 is electrically connected to the output terminal of the operational amplifier, and the source of the NMOS transistor MN3 is electrically connected to the drain of the NMOS transistor MN1. The source of the PMOS transistor MP1 is connected to the supply voltage VDD. The gate and drain of the PMOS transistor MP1 are both electrically connected to the drain of the NMOS transistor MN4. The gate of the NMOS transistor MN4 is electrically connected to the drain of the NMOS transistor MN3. The source of the NMOS transistor MN4 is electrically connected to the gates of the NMOS transistors MN1 and MN2. The source of the NMOS transistor MN4 is also electrically connected to the first bias current source Ibias1.
[0013] Furthermore, the first bias current source Ibias1 is defined as an NMOS transistor MN7, the drain of which is electrically connected to the gates of NMOS transistors MN1 and MN2, the gate of which is connected to a bias voltage Vbias3, and the source of which is grounded.
[0014] In this invention, by electrically connecting the drains of NMOS transistors MN1 and MN2 to the inverting and non-inverting inputs of an operational amplifier, respectively, the "virtual short" characteristic between the inverting and non-inverting inputs of the operational amplifier can be utilized to ensure that the drain voltages of NMOS transistors MN1 and MN2 are equal. This avoids the influence of the MOS channel length modulation effect and achieves accurate current replication. Furthermore, the structural design of the voltage unit can provide a stable bias voltage for the gates of NMOS transistors MN1 and MN2, improving the accuracy of the current source calibration process. Attached Figure Description
[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 Circuit diagram of a conventional current source compensation circuit.
[0016] Figure 2 This is a circuit diagram showing an embodiment of the current mirror circuit for compensating a current source to be calibrated according to the present invention, after being connected to the current source to be calibrated.
[0017] Figure 3 This is a circuit diagram of a specific example of an operational amplifier.
[0018] Figure 4 The circuit diagram is a specific example of the first bias current source and the second bias current source. Detailed Implementation
[0019] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0020] Please see Figure 2 , Figure 2 This is a circuit diagram of an embodiment of the current mirror circuit for compensating a current source to be calibrated according to the present invention. The current mirror circuit of this embodiment includes a compensation current source Ical, a current mirror, and a voltage unit. The compensation current source Ical provides compensation current to the input terminal of the current mirror.
[0021] The current mirror is used to output a corresponding mirror current at its output terminal according to the compensation current output by the compensation current source, and to compensate the current source Iu to be calibrated through the mirror current. In this embodiment, the current mirror includes NMOS transistor MN1 and NMOS transistor MN2; both NMOS transistor MN1 and NMOS transistor MN2 are preferably fabricated using TSMC 12nm FinFET process.
[0022] The drain of NMOS transistor MN1 is electrically connected to the compensation current source Ical as the input terminal of the current mirror, and the drain of NMOS transistor MN2 is electrically connected to the current source to be calibrated as the output terminal of the current mirror. The gates of NMOS transistor MN1 and NMOS transistor MN2 are electrically connected, and the sources of both NMOS transistor MN1 and NMOS transistor MN2 are grounded.
[0023] The current source Iu to be calibrated can be formed using an NMOS transistor MN10. Specifically, the drain of the NMOS transistor MN10 is electrically connected to the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN10 is connected to a bias voltage Vbias0, and the source of the NMOS transistor MN10 is grounded. The bias voltage Vbias0 is used to make the NMOS transistor MN10 operate in the saturation region. At this time, the drain current of the NMOS transistor MN10 is not sensitive to changes in its drain-source voltage, and can output a constant current. Of course, the current source Iu to be calibrated can also use other current source structures.
[0024] The voltage unit is used to provide a bias voltage for the current mirror and to maintain equal voltages at the input and output terminals of the current mirror. Specifically, the voltage unit may include a voltage regulator unit and a bias unit. The voltage regulator unit is used to maintain equal voltages at the input and output terminals of the current mirror. The drains of NMOS transistors MN1 and MN2 are electrically connected to the voltage regulator unit, respectively. The bias unit is used to provide operating bias voltages for the gates of NMOS transistors MN1 and MN2.
[0025] In this embodiment, the voltage regulation unit is defined as an operational amplifier. The inverting input terminal of the operational amplifier is electrically connected to the drain of NMOS transistor MN1, the non-inverting input terminal of the operational amplifier is electrically connected to the drain of NMOS transistor MN2, and the output terminal of the operational amplifier is electrically connected to the bias unit.
[0026] Please see Figure 3Specifically, the operational amplifier may include PMOS transistor MP2, PMOS transistor MP3, NMOS transistor MN5, and NMOS transistor MN6. The PMOS transistors MP2, MP3, MN5, and MN6 are preferably fabricated using a TSMC 12nm FinFET process.
[0027] The sources of both PMOS transistors MP2 and MP3 are electrically connected to the second terminal of the second bias current source Ibias2, and the first terminal of the second bias current source Ibias2 is connected to the supply voltage VDD. Please refer to [link / reference]. Figure 4 The second bias current source Ibias2 may include PMOS transistors MP4 and MP5, which are preferably fabricated using a TSMC 12nm FinFET process. The source of PMOS transistor MP4 is connected to the supply voltage VDD, the gate of PMOS transistor MP4 is connected to the bias voltage Vbias1, and the drain of PMOS transistor MP4 is electrically connected to the source of PMOS transistor MP5. The gate of PMOS transistor MP5 is connected to the bias voltage Vbias2, and the drain of PMOS transistor MP5 is electrically connected to the sources of PMOS transistors MP2 and MP3. The bias voltages Vbias1 and Vbias2 work together to ensure that PMOS transistor MP4 operates in the saturation region, and simultaneously, bias voltage Vbias2 also ensures that PMOS transistor MP5 operates in the saturation region, thus forming a current source through PMOS transistors MP4 and MP5.
[0028] In this embodiment, two MOS transistors (i.e., PMOS transistor MP4 and PMOS transistor MP5) are used to form the second bias current source Ibias2, which has a higher power supply rejection ratio and stronger immunity to power supply noise. Of course, the second bias current source Ibias2 can also adopt other current source structures.
[0029] The gate of PMOS transistor MP2 is electrically connected to the drain of NMOS transistor MN1 as the inverting input of an operational amplifier, forming node X. The gate of PMOS transistor MP3 is electrically connected to the drain of NMOS transistor MN2 as the non-inverting input of an operational amplifier, forming node Y. The drain of PMOS transistor MP3 is electrically connected to the bias unit as the output of the operational amplifier, and the drain of PMOS transistor MP3 is also electrically connected to the drain of NMOS transistor MN6. The drain of PMOS transistor MP2 is electrically connected to the drain of NMOS transistor MN5, the gate of NMOS transistor MN5, and the gate of NMOS transistor MN6, respectively. The sources of NMOS transistor MN5 and NMOS transistor MN6 are both grounded.
[0030] Using the above circuit structure, based on the "virtual short" (i.e., the same potential) characteristic between the non-inverting and inverting input terminals of the operational amplifier, the voltage at node X and the voltage at node Y are equal. The function of the operational amplifier is to ensure that the drain voltage of NMOS transistor MN1, which constitutes the reference current source in the current mirror, and NMOS transistor MN2, which constitutes the output current source, are equal, thereby avoiding the influence of the MOS channel length modulation effect on the accuracy of the output current.
[0031] The bias unit includes a PMOS transistor MP1, an NMOS transistor MN3, an NMOS transistor MN4, and a first bias current source Ibias1. In this embodiment, the PMOS transistor MP1, NMOS transistor MN3, and NMOS transistor MN4 are preferably fabricated using the TSMC 12nm FinFET process.
[0032] The drain of NMOS transistor MN1 is electrically connected to the second terminal of compensation current source Ical via NMOS transistor MN3. The first terminal of compensation current source Ical is connected to the supply voltage VDD. The drain of NMOS transistor MN3 is electrically connected to compensation current source Ical, the gate of NMOS transistor MN3 is electrically connected to the output terminal of operational amplifier, and the source of NMOS transistor MN3 is electrically connected to the drain of NMOS transistor MN1.
[0033] The source of the PMOS transistor MP1 is connected to the supply voltage VDD. The gate and drain of the PMOS transistor MP1 are both electrically connected to the drain of the NMOS transistor MN4. The gate of the NMOS transistor MN4 is electrically connected to the drain of the NMOS transistor MN3. The source of the NMOS transistor MN4 is electrically connected to the gates of both NMOS transistors MN1 and MN2, forming node G. The source of the NMOS transistor MN4 is also electrically connected to the first terminal of the first bias current source Ibias1, and the second terminal of the first bias current source Ibias1 is grounded.
[0034] Please continue reading. Figure 4 In this embodiment, the first bias current source Ibias1 is defined as an NMOS transistor MN7, which is preferably fabricated using a TSMC 12nm FinFET process. The drain of the NMOS transistor MN7 is electrically connected to the gates of NMOS transistors MN1 and MN2, and the gate of the NMOS transistor MN7 is connected to a bias voltage Vbias3, which is used to make the NMOS transistor MN7 operate in the saturation region; the source of the NMOS transistor MN7 is grounded. Of course, the first bias current source Ibias1 can also adopt other current source structures.
[0035] The bias unit adopts a circuit structure, and the potential V of node Y is... Y Determined by the external bias voltage, and V Y This ensures that NMOS transistor MN2 operates in the saturation region. Based on the "virtual short" characteristic of operational amplifiers, the potential of node X is equal to the potential of node Y, i.e., VX. X =V Y Furthermore, because NMOS transistors MN1 and MN2 form a current mirror, therefore V X This ensures that NMOS transistor MN1 operates in the saturation region. As the supply voltage rises, the diodes formed by the Ical current source and the PMOS transistor MP1 cause the drain potentials of NMOS transistors MN3 and MN4 to rise. The initial potential V at node G... G Since the voltage is 0V, the gate-source voltage of NMOS transistor MN4 continuously increases. When the gate-source voltage of NMOS transistor MN4 exceeds its threshold voltage, NMOS transistor MN4 turns on, and the potential V at node G... G As the potential V at node G increases continuously, G Increase until the following expression is satisfied: 1 / 2(μ n C ox (W / L) MN1 (VG -Vthn1) 2 =I cal V G This remains unchanged, thus stabilizing the bias voltages at the gates of NMOS transistors MN1 and MN2. Where μ... n Indicates electron mobility; C ox This represents the gate oxide capacitance per unit area; (W / L) MN1 Vthn1 represents the width-to-length ratio of NMOS transistor MN1; Vthn1 represents the threshold voltage of NMOS transistor MN1; I cal This represents the compensation current output by the compensation current source Ical.
[0036] In this embodiment, by electrically connecting the drains of NMOS transistors MN1 and MN2 to the inverting and non-inverting inputs of the operational amplifier, respectively, the "virtual short" characteristic between the inverting and non-inverting inputs of the operational amplifier can be utilized to make the drain voltages of NMOS transistors MN1 and MN2 equal, thereby avoiding the influence of the MOS channel length modulation effect and achieving accurate current replication. Furthermore, the structural design of the voltage unit can provide a stable bias voltage for the gates of NMOS transistors MN1 and MN2. In addition, in the current mirror circuit of this embodiment, each MOS transistor is fabricated using a 12nm FinFET process PDK, which can further improve the accuracy of the output mirror current. When the compensation current I... cal When the current is 1μA, the difference between the compensation current and the input current after being copied by the precision current mirror is within 10nA. Therefore, the compensation current can be accurately added to the current source Iu to be calibrated, improving the accuracy of the current source calibration process.
[0037] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.
Claims
1. A current mirror circuit for compensation of a current source to be calibrated, characterized by: The compensation current source Ical is configured to provide a compensation current to an input terminal of the current mirror; The current mirror is configured to output a corresponding mirror current at an output terminal thereof according to the compensation current output by the compensation current source, and the mirror current is used to compensate the to-be-corrected current source Iu; The voltage unit is configured to provide a bias voltage for the current mirror, and maintain the voltage at the input terminal and the output terminal of the current mirror to be equal. The current mirror comprises an NMOS transistor MN1 and an NMOS transistor MN2; the drain of the NMOS transistor MN1 is electrically connected to the compensation current source Ical as an input terminal of the current mirror, and the drain of the NMOS transistor MN2 is electrically connected to the to-be-corrected current source as an output terminal of the current mirror; the gate of the NMOS transistor MN1 is electrically connected to the gate of the NMOS transistor MN2, and the source of the NMOS transistor MN1 and the source of the NMOS transistor MN2 are both grounded. The NMOS transistor MN1 and the NMOS transistor MN2 are both formed by using a tsmc12nm FinFET process.
2. The current mirror circuit for compensation of a current source to be calibrated according to claim 1, characterized in that: The to-be-corrected current source Iu is defined as an NMOS transistor MN10, the drain of the NMOS transistor MN10 is electrically connected to the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN10 is connected to the bias voltage Vbias0, and the source of the NMOS transistor MN10 is grounded.
3. The current mirror circuit for compensation of a current source to be calibrated according to claim 2, characterized in that: The voltage unit comprises a voltage stabilizing unit and a bias unit, the voltage stabilizing unit is configured to maintain the voltage at the input terminal and the output terminal of the current mirror to be equal, the drain of the NMOS transistor MN1 and the drain of the NMOS transistor MN2 are respectively electrically connected to the voltage stabilizing unit, and the bias unit is configured to provide a working bias voltage for the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2.
4. The current mirror circuit for compensation of a current source to be calibrated according to claim 2, characterized in that: The voltage stabilizing unit is defined as an operational amplifier, the inverting input terminal of the operational amplifier is electrically connected to the drain of the NMOS transistor MN1, the non-inverting input terminal of the operational amplifier is electrically connected to the drain of the NMOS transistor MN2, and the output terminal of the operational amplifier is electrically connected to the bias unit.
5. The current mirror circuit for compensation of a current source to be calibrated according to any one of claims 2 to 4, characterized in that: The operational amplifier comprises a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN5 and an NMOS transistor MN6; the sources of the PMOS transistor MP2 and the PMOS transistor MP3 are both electrically connected to a second bias current source Ibias2, the gate of the PMOS transistor MP2 is electrically connected to the drain of the NMOS transistor MN1 as the inverting input terminal of the operational amplifier; 6. The current mirror circuit for compensation of a current source to be calibrated according to claim 5, characterized in that: the gate of the PMOS transistor MP3 is electrically connected to the drain of the NMOS transistor MN2 as the non-inverting input terminal of the operational amplifier, the drain of the PMOS transistor MP3 is electrically connected to the bias unit as the output terminal of the operational amplifier, and the drain of the PMOS transistor MP3 is also electrically connected to the drain of the NMOS transistor MN6; 7. The current mirror circuit for compensation of a current source to be calibrated according to claim 6, characterized in that: The drain of the PMOS transistor MP2 is electrically connected with the drain of the NMOS transistor MN5, the gate of the NMOS transistor MN5 and the gate of the NMOS transistor MN6 respectively, and the source of the NMOS transistor MN5 and the source of the NMOS transistor MN6 are both grounded.
8. The current mirror circuit for compensation of a current source to be calibrated according to claim 7, characterized in that: The second bias current source Ibias2 comprises a PMOS transistor MP4 and a PMOS transistor MP5, the source of the PMOS transistor MP4 is connected with a power supply voltage VDD, the gate of the PMOS transistor MP4 is connected with a bias voltage Vbias1, and the drain of the PMOS transistor MP4 is electrically connected with the source of the PMOS transistor MP5; the gate of the PMOS transistor MP5 is connected with a bias voltage Vbias2, and the drain of the PMOS transistor MP5 is electrically connected with the source of the PMOS transistor MP2 and the source of the PMOS transistor MP3.
9. The current mirror circuit for compensation of a current source to be calibrated according to claim 6, characterized in that: The bias unit comprises a PMOS transistor MP1, an NMOS transistor MN3, an NMOS transistor MN4 and a first bias current source Ibias1, the drain of the NMOS transistor MN1 is electrically connected with a compensation current source Ical through the NMOS transistor MN3; wherein the drain of the NMOS transistor MN3 is electrically connected with the compensation current source Ical, the gate of the NMOS transistor MN3 is electrically connected with the output terminal of the operational amplifier, and the source of the NMOS transistor MN3 is electrically connected with the drain of the NMOS transistor MN1. The source of the PMOS transistor MP1 is connected with a power supply voltage VDD, and the gate and the drain of the PMOS transistor MP1 are both electrically connected with the drain of the NMOS transistor MN4; the gate of the NMOS transistor MN4 is electrically connected with the drain of the NMOS transistor MN3, the source of the NMOS transistor MN4 is electrically connected with the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2, and the source of the NMOS transistor MN4 is also electrically connected with the first bias current source Ibias1.
10. The current mirror circuit for compensation of a current source to be calibrated according to claim 9, characterized in that: The first bias current source Ibias1 is defined as an NMOS transistor MN7, the drain of the NMOS transistor MN7 is electrically connected with the gate of the NMOS transistor MN1 and the gate of the NMOS transistor MN2, the gate of the NMOS transistor MN7 is connected with a bias voltage Vbias3, and the source of the NMOS transistor MN7 is grounded.