A single-ended voltage-to-differential current circuit with adjustable gain

Abstract

The application discloses a single-ended voltage to differential current circuit with adjustable gain, comprising a single-ended voltage to differential current module and an adjustable gain control module; wherein the single-ended voltage to differential current module adopts a symmetrical structure and converts a single-ended voltage into a differential current by using a cross-connected resistor; the adjustable gain control module provides a static complementary differential current by using a current adder and realizes proportional gain adjustment by means of a proportional current mirror structure; meanwhile, the source-drain voltage of a copy PMOS transistor is fixed by using the constant emitter-base voltage difference of a bipolar transistor, the channel length modulation effect is avoided, and the accuracy of the copy current is further enhanced. The application meets the requirements of low power consumption, high signal noise distortion ratio and high integration of an audio circuit and has a large adjustable gain range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a gain-adjustable single-ended voltage-to-differential current circuit. Background Technology

[0002] Most audio and sensor output signals are single-ended analog signals. Single-ended signal circuits are simple in structure and low in cost, but are susceptible to interference; while dual-ended differential circuits, although complex and larger in area, can avoid the shortcomings of single-ended circuits, effectively improve the performance of analog front-ends, and have advantages such as suppressing common-mode noise, reducing distortion, and increasing the dynamic range of the circuit. When the input is a single-ended signal, the internal circuit usually adopts a differential design to reduce noise. At the same time, current-mode circuits are widely used in gain-adjustable circuits due to their high speed and simple logic. Therefore, single-ended voltage-to-differential current circuits have emerged.

[0003] To achieve single-ended voltage to differential current conversion, two steps are generally used: first, convert the single-ended voltage to a differential voltage, and then convert the differential voltage to a differential current. These two steps mean the circuit is more complex and redundant. Therefore, some researchers have combined the two circuits into one, using bipolar transistors to achieve adjustable gain single-ended voltage to differential current conversion. However, due to the use of a large number of bipolar transistors, the circuit has high power consumption and low integration density. Summary of the Invention

[0004] The purpose of this invention is to provide a gain-adjustable single-ended voltage-to-differential current circuit to solve the problems of high power consumption, high signal-to-noise ratio, and low integration in existing circuits.

[0005] To solve the above-mentioned technical problems, the present invention provides a gain-adjustable single-ended voltage to differential current circuit, comprising: a single-ended voltage to differential current module and an adjustable gain control module; The single-ended voltage to differential current module adopts a symmetrical fully differential structure and its function is to convert single-ended voltage into differential current. The positive input terminal of the single-ended voltage to differential current module is connected to the input voltage Vin, and the reverse input terminal is connected to the reference voltage VREF. The positive output current is Icp, and the reverse output current is Icn. The adjustable gain control module is used to adjust the gain of the output differential current of the single-ended voltage to differential current module. The positive input terminal of the adjustable gain control module is connected to the positive output terminal of the single-ended voltage to differential current module, and the negative input terminal of the adjustable gain control module is connected to the negative output terminal of the single-ended voltage to differential current module. The positive input current is Icp, and the negative input current is Icn. The adjustable gain control module is also connected to the gain control voltage VCT and the adjustable current adder power supply voltage VLDO. The positive output current of the adjustable gain control module is Iop, and the negative output current is Ion.

[0006] In one embodiment, the single-ended voltage to differential current module includes: a first operational amplifier, a second operational amplifier, a first current source, a second current source, a first resistor, a second resistor, a first bipolar transistor, a second bipolar transistor, a first PMOS transistor, and a second PMOS transistor MP2; The first operational amplifier and the second operational amplifier provide sufficient gain to ensure stable and reliable negative feedback in the loop. The output terminal of the first operational amplifier is connected to the gate of the first PMOS transistor, the positive input terminal of the first operational amplifier is connected to the collector of the first bipolar transistor, the first end of the first resistor, and the first end of the first current source, and the inverting input terminal of the first operational amplifier is connected to the input voltage Vin. The output terminal of the second operational amplifier is connected to the gate of the second PMOS transistor, the positive input terminal of the second operational amplifier is connected to the collector of the second bipolar transistor, the second end of the first resistor, and the first end of the second current source, and the inverting input terminal of the second operational amplifier is connected to the reference voltage VREF. The first bipolar transistor, the second bipolar transistor, and the second resistor together determine the emitter voltage of the first bipolar transistor and the second bipolar transistor; the emitter of the first bipolar transistor is connected to the drain of the first PMOS transistor, the base of the first bipolar transistor is connected to the base of the second bipolar transistor, and the first end of the second resistor is connected; the emitter of the second bipolar transistor is connected to the drain of the second PMOS transistor; the first end of the second resistor is connected to the base of the first bipolar transistor and the second bipolar transistor, and the second end of the second resistor is connected to the reference voltage VREF; The first PMOS transistor and the second PMOS transistor function as current mirrors; the first resistor, together with the first current source and the second current source, determines the maximum allowable input swing of the circuit; the source terminals of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage VDD; the other terminals of the first current source and the second current source are connected to ground GND.

[0007] In one embodiment, the adjustable gain control module includes: an adjustable current adder and a gain adjustment module; The adjustable current adder adopts a differential structure to form a static complementary differential current, including: a third current source, a fourth current source, a fifth current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third bipolar transistor, a fourth bipolar transistor, and a third resistor; The fourth NMOS transistor, together with the third resistor and the fifth current source, generates a comparison voltage, which serves as the comparison voltage for the gain control voltage VCT. The gate and drain of the fourth NMOS transistor are connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the first terminal of the fifth current source, the gate of the first NMOS transistor, and the gate of the third NMOS transistor. The second terminal of the fifth current source is connected to the power supply voltage VDD. The third current source, the fourth current source, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the third bipolar transistor, and the fourth bipolar transistor constitute a current adder circuit to provide static complementary currents IXP and INX. The drain of the first NMOS transistor is connected to the collector and base of the third bipolar transistor, the drain of the second NMOS transistor is connected to the collector and base of the fourth bipolar transistor, and the drain of the third NMOS transistor. The gate of the second NMOS transistor is connected to the gain control voltage VCT. The sources of the third and fourth bipolar transistors are both connected to the adjustable current adder power supply voltage VLDO. The first terminal of the third current source is connected to the source of the first and second NMOS transistors, and the first terminal of the fourth current source is connected to the source of the third NMOS transistor. The source of the fourth NMOS transistor, the second terminal of the third current source, and the second terminal of the fourth current source are connected to ground GND.

[0008] In one embodiment, the gain adjustment module adopts a symmetrical proportional current mirror structure to proportionally adjust the output current of the single-ended voltage to differential current module; the gain adjustment module includes: a fifth NMOS transistor and a sixth NMOS transistor, a fifth bipolar transistor, a sixth bipolar transistor, a seventh bipolar transistor, an eighth bipolar transistor, a third PMOS transistor, and a fourth PMOS transistor; The third and fourth PMOS transistors are current mirrors, copying the output differential current of the single-ended voltage to differential current module; the gate of the third PMOS transistor is connected to the output voltage Vcp of the first operational amplifier, and the drain of the third PMOS transistor is connected to the emitter of the fifth and seventh bipolar transistors; the gate of the fourth PMOS transistor is connected to the output voltage Vcn of the second operational amplifier, and the drain of the fourth PMOS transistor is connected to the emitter of the sixth and eighth bipolar transistors. The fifth, sixth, seventh, and eighth bipolar transistors are current mirrors, wherein the fifth and sixth bipolar transistors copy the reverse output current IXN of the adjustable current adder, and the seventh and eighth bipolar transistors copy the forward output current IXP of the adjustable current adder; the bases of the fifth and sixth bipolar transistors are simultaneously connected to the collector and base of the third bipolar transistor in the adjustable current adder, and the bases of the seventh and eighth bipolar transistors are simultaneously connected to the collector and base of the fourth bipolar transistor in the adjustable current adder; The fifth and sixth NMOS transistors form a load circuit, serving to provide a current mirror copy for subsequent circuits. The gate and drain of the fifth NMOS transistor are both connected to the collector of the seventh bipolar transistor, and the gate and drain of the sixth NMOS transistor are both connected to the collector of the eighth bipolar transistor. The sources of the third and fourth PMOS transistors are both connected to the power supply voltage VDD, and the collectors of the fifth and sixth bipolar transistors, as well as the sources of the fifth and sixth NMOS transistors, are all connected to ground GND.

[0009] In one embodiment, the first current source and the second current source are of equal magnitude and have a current value of 10*ISS; the third current source has a current value of 9*ISS, and the fourth current source and the fifth current source have a current value of ISS; where ISS is the unit current of the current mirror copy.

[0010] This invention provides a gain-adjustable single-ended voltage-to-differential current circuit, characterized by low power consumption, high signal-to-noise distortion ratio, and a large gain adjustment range. Compared with existing technologies, this invention has the following advantages: (1) The circuit has low complexity and high integration. It decouples the single-ended voltage to differential current conversion from gain adjustment, resulting in a simpler and more flexible structure. It is designed using BCD technology, which has high integration. (2) Low power consumption, mainly CMOS transistors, achieving a static current of 471μA; (3) High signal-to-noise ratio: The circuit adopts a symmetrical fully differential structure. When the differential current is output at 0.5 times the full amplitude, the signal-to-noise ratio is 79.8dB. (4) Wide range of adjustable gain, using a symmetrical proportional current mirror structure, the adjustable gain range is -20dB~0dB. Attached Figure Description

[0011] Figure 1 This is a block diagram of a gain-adjustable single-ended voltage-to-differential current circuit according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of a single-ended voltage-to-differential current (S2D) circuit according to an embodiment of the present invention.

[0013] Figure 3 This is a schematic diagram of the adjustable gain control VGC circuit according to an embodiment of the present invention.

[0014] Figure 4 The DC simulation results of IXP and IXN as a function of VCT in the adjustable current adder of this embodiment of the invention are shown.

[0015] Figure 5 This is the AC simulation result of the differential current output Iop-Ion varying with VCT in an embodiment of the present invention.

[0016] Figure 6 This is the transient simulation result of the differential current output Iop-Ion as a function of VCT in an embodiment of the present invention.

[0017] Figure 7 The results are Fast Fourier Transform (FFT) analysis of the full-amplitude differential current output Iop-Ion according to an embodiment of the present invention.

[0018] Figure 8 The results are Fast Fourier Transform (FFT) analysis of the 0.5 times full-amplitude differential current output Iop-Ion in this embodiment of the invention. Detailed Implementation

[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the gain-adjustable single-ended voltage-to-differential current circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0020] This invention provides a gain-adjustable single-ended voltage-to-differential current circuit, the principle block diagram of which is shown below. Figure 1 As shown, it mainly includes a single-ended voltage to differential current module S2D and an adjustable gain control module VGC.

[0021] The single-ended voltage to differential current module S2D converts the input voltage Vin into differential currents Icn and Icp; the reference voltage VREF serves as the common-mode voltage of the internal amplifier. In this embodiment, the reference voltage VREF is 1.23V.

[0022] The adjustable gain control module VGC adjusts the gain of the differential currents Icn and Icp, resulting in Iop and Ion after gain adjustment. VCT is the gain control voltage, and VLDO is the power supply voltage for the adjustable current adder of the adjustable gain control module VGC, generated by a low-dropout linear regulator (LDO) circuit. In this embodiment, VLDO is 2V. When the gain control voltage VCT changes from 0V to 3.3V, the adjusted differential currents Iop and Ion are... That is, the gain adjustment range is -20dB to 0dB.

[0023] Figure 2 The circuit schematic for single-ended voltage to differential current (S2D) conversion adopts a symmetrical structure design and mainly includes operational amplifiers OP1 and OP2, a first current source, a second current source, resistors R1 and R2, bipolar transistors Q1 and Q2, and PMOS transistors MP1 and MP2.

[0024] In this embodiment, operational amplifiers OP1 and OP2 provide an open-loop gain of 65dB and a gain-bandwidth product of 880kHz, meeting the bandwidth requirements of the audio circuit while ensuring stable and reliable negative feedback in the loop. Operational amplifiers OP1 and OP2 in this embodiment are designed identically, both using PMOS transistors as input pairs and employing a folded common-source common-gate single-stage operational amplifier structure.

[0025] The first and second current sources provide a constant tail current of equal magnitude. In this embodiment, the current value is 10 * ISS, where ISS is the unit current copied by the current mirror, and its value is 6 μA. The resistor R1 and the current sources (the first and second current sources) determine the maximum allowable input swing of the circuit, which is calculated as resistor R1 value * current source value = R1 * 10 * ISS. In this embodiment, R1 is 8 kΩ, therefore the maximum input swing is limited to 480 mV, meaning the maximum single-ended swing of currents Icp and Icn is 10 * ISS = 60 μA, and the maximum differential current swing is 2 * 10 * ISS = 120 μA.

[0026] In this embodiment, the bipolar transistors Q1 and Q2, and the resistor R2 are appropriately valued so that the emitter voltages Vx3 and Vx4 of the bipolar transistors Q1 and Q2 are fixed at 2V and do not change with the power supply voltage VDD. Where IR2 is the current through resistor R2, and VEB1 is the emitter-base voltage difference of bipolar transistor Q1. Similarly, voltage... VEB2 is the emitter-base voltage difference of bipolar transistor Q2. Bipolar transistors Q1 and Q2 are the same size.

[0027] PMOS transistors MP1 and MP2 have the same width-to-length ratio and act as current mirrors for the adjustable gain control of VGC, copying the currents Icp and Icn.

[0028] Operational amplifier OP1, PMOS transistor MP1, and bipolar transistor Q1 form a negative feedback loop, making voltage Vx1 equal to the input voltage Vin. Operational amplifier OP2, PMOS transistor MP2, and bipolar transistor Q2 form a negative feedback loop, making voltage Vx2 equal to the reference voltage VREF. Simultaneously, the common-mode voltage of the input voltage Vin is equal to the reference voltage VREF, therefore the current through resistor R1 can be obtained. The collector current of bipolar transistor Q1 The collector current of bipolar transistor Q2 .

[0029] Emitter current of bipolar transistor Q1: Emitter current of bipolar transistor Q2: in Let Q1 and Q2 be the amplification factors. Then the differential current... .

[0030] Figure 3 This is the circuit schematic of the adjustable gain control module VGC, which mainly includes an adjustable current adder and a gain adjustment module.

[0031] The adjustable current adder includes a third current source, a fourth current source, a fifth current source, NMOS transistors MN1, MN2, MN3, and MN4, bipolar transistors Q3 and Q4, and a resistor R3.

[0032] In this embodiment, the current of the third current source is 9*ISS, and the currents of the fourth and fifth current sources are ISS. The NMOS transistors MN1 and MN2 have the same width-to-length ratio. The bipolar transistors Q3 and Q4 have the same size as the bipolar transistors Q1 and Q2 in the single-ended voltage to differential current module S2D. The voltage Vx3 = Vx4 = 2V, and does not change with the power supply voltage VDD. The voltage VLDO is the same as Vx3 and Vx4, i.e., VLDO = Vx3 = Vx4 = 2V; Vx3 and Vx4 are the emitter voltages of bipolar transistors Q1 and Q2, respectively.

[0033] The fifth current source ISS, resistor R3, and NMOS transistor MN4 generate a comparison voltage VXM, which in this embodiment is 1.53V. The gain control voltage VCT is a variable voltage, ranging from ground GND = 0V to the power supply voltage VDD = 3.3V.

[0034] The third current source 9*ISS, the fourth current source ISS, NMOS transistors MN1, MN2, and MN3, and bipolar transistors Q3 and Q4 constitute a current adder circuit. Its purpose is to provide static complementary differential currents IXP and INX, such that IXP + IXN = 10*ISS. NMOS transistors MN1 and MN2 are the input pair of the adjustable current adder, with their gates connected to the comparison voltage VXM and the gain control voltage VCT, respectively. When the gain control voltage VCT = 0V, NMOS transistor MN2 is completely off, and the collector current IXP of bipolar transistor Q4 is provided solely by the fourth current source ISS, IXP = ISS. The collector current IXN of bipolar transistor Q3 is provided by the third current source 9*ISS, IXN = 9*ISS. When the gain control voltage VCT = VDD = 3.3V, NMOS transistor MN2 is fully on, and the collector current IXP of bipolar transistor Q4 is provided by the third current source 9*ISS and INX. The fourth current source ISS is provided together, IXP = 9*ISS + ISS = 10*ISS, and the collector current IXN of bipolar transistor Q3 is 0. When the gain control voltage VCT varies between 0V and VDD, the sum of the collector current IXP of bipolar transistor Q4 and the collector current IXN of bipolar transistor Q3 should be equal to the sum of the third current source 9*ISS and the fourth current source ISS, i.e., IXP + IXN = 9*ISS + ISS = 10*ISS. Table 1 is the complementary differential current relationship table of the current adder circuit:

[0035] Table 1: Complementary differential current relationship of current adder circuit The gain adjustment module includes NMOS transistors MN5 and MN6, bipolar transistors Q5, Q6, Q7, Q8, and PMOS transistors MP3 and MP4, and has a proportional shunt structure.

[0036] The PMOS transistors MP3 and MP4 have the same width-to-length ratio as MP1 and MP2 in the single-ended voltage to differential current module D2S; the bipolar transistors Q5, Q6, Q7, and Q8 have the same size as the bipolar transistors Q3 and Q4 in the adjustable current adder, and the bipolar transistors Q1 and Q2 in the single-ended voltage to differential current module S2D.

[0037] PMOS transistors MP3 and MP4 act as current mirrors, copying Icp and Icn from the single-ended voltage-to-differential current conversion module S2D, respectively. In this embodiment, the default common-mode current is 10*ISS=60μA, and the maximum swing of the single-ended currents Icp and Icn is 60μA.

[0038] Bipolar transistors Q5, Q6, Q7, and Q8 are all current mirrors. Q5 and Q6 copy the current IXN of the adjustable current adder, while Q7 and Q8 copy the current IXP of the adjustable current adder. Simultaneously, this circuit ensures that the emitter voltage of bipolar transistors Q5, Q6, Q7, and Q8 is equal to VLDO, which is 2V. This also means that the source-drain voltages of the current mirror PMOS transistors MP3 and MP4 are equal to the source-drain voltages of the PMOS transistors MP1 and MP2 in the single-ended voltage-to-differential current module D2S. This avoids channel length modulation effects and further enhances the accuracy of the copied current.

[0039] As mentioned above, IXN + IXP = 10 * ISS, therefore Ie5 + Ie7 = 10 * ISS, Ie6 + Ie8 = 10 * ISS, where Ie5, Ie6, Ie7, and Ie8 are the emitter currents of bipolar transistors Q5, Q6, Q7, and Q8, respectively. Therefore, we can obtain: IXP is positively correlated with VCT. The value is 0.1~1. When the gain control voltage VCT changes from 0V to 3.3V, the differential current Iop-Ion after gain adjustment is... That is, the gain adjustment range is -20dB to 0dB.

[0040] Figure 4 This presents the DC simulation results of IXP and IXN in the adjustable current adder as a function of VCT. Figure 4 It can be seen that when VCT changes from 0V to 3.3V, the current IXP increases from 5.3μA to 58μA, an amplification of approximately 10.9 times, close to the theoretical value of 10 times in Table 1; the current IXN decreases from 53μA to 0A, consistent with the theory. Here, IXP+IXN=58μA, and remains constant throughout the entire voltage range of VCT, consistent with the theory. The curve IXP / (IXP+IXN) changes from 0.91 to 1, indicating a certain error at low gain, originating from current mirror copying, but within a reasonable range, basically consistent with the theoretical analysis in Table 1. Figure 4 It can be seen that the IXP and IXN curves intersect at 1.53V, which is determined by VXM in the adjustable current adder.

[0041] Figure 5 This presents AC simulation results showing the differential current output Iop-Ion as a function of VCT. Figure 5 It can be seen that the AC voltage of the input voltage Vin is 1V. When VCT changes from 0V to 3.3V, Iop-Ion changes from 27μA to 259μA, a difference of nearly 10 times. From the above, we can conclude that: Where R1 is 8kHz The value is between 0.1 and 1. Therefore, theoretically... The maximum is 250 μA and the minimum is 25 μA. According to the simulation results, the actual value is 27 μA to 259 μA, which is close to the theoretical value.

[0042] Figure 6 The transient simulation results show the differential current output Iop-Ion as a function of VCT. The waveforms, from top to bottom, represent the Iop-Ion curves for the input voltage Vin (full-scale input), VCT=0V, VCT=1.52V, and VCT=3.3V. It can be seen that at full-scale input, when VCT=3.3V, the gain is at its maximum of 1, with an output swing of 119μA; when VCT=0V, the gain is at its minimum of 0.1, with an output swing of 12.5μA; and when VCT=1.52V, the gain is 0.5, with an output swing of 61μA.

[0043] Figure 7 The results are obtained from the Fast Fourier Transform (FFT) analysis of the full-amplitude differential current output Iop-Ion. Figure 7 It can be seen that, under full-scale conditions, the differential current output Iop-Ion swing is 119μA, the FFT analysis samples 65536 points, the signal bandwidth is from 1 to 20kHz, which is the audio bandwidth, and the signal-to-noise ratio (SINAD) is 63.7dB.

[0044] Figure 8 The Fast Fourier Transform (FFT) analysis results are for the Iop-Ion differential current output at 0.5 times the full-scale value. Figure 8 It can be seen that at 0.5 times the full-scale value, the differential current output Iop-Ion swing is 59.4μA. The FFT analysis sampled 65536 points, with a signal bandwidth from 1 to 20kHz (audio bandwidth), and the signal-to-noise ratio (SINAD) was 79.8dB. In summary, when the output approaches full-scale, the output differential current signal-to-noise ratio (SINAD) decreases; exceeding full-scale, the waveform is clipped. In this implementation, the input voltage swing is limited by resistor R1 and the first and second current sources in the single-ended voltage-to-differential current module D2S, with a maximum input swing limited to 480mV and a maximum output differential current swing of 120μA. Therefore, in circuit design, the maximum input voltage swing should be considered in conjunction with the actual application, and a certain margin should be reserved to avoid output current clipping.

[0045] This invention relates to an audio automatic gain control system. The circuit includes a single-ended voltage-to-differential current conversion module and an adjustable gain control module. The single-ended voltage-to-differential current conversion module adopts a symmetrical structure, using a bridging resistor to convert the single-ended voltage into a differential current. The adjustable gain control module uses a current adder to provide a static complementary differential current, and achieves proportional gain adjustment through a proportional shunt structure. Simultaneously, it utilizes the constant emitter-base voltage difference of a bipolar transistor to fix the source-drain voltage of the copying PMOS transistor, avoiding channel length modulation effects and further enhancing the accuracy of the copying current. The circuit ultimately achieves a static current of 471μA, a signal-to-noise distortion ratio of 79.8dB at 0.5 times the full-amplitude output differential current, and an adjustable gain range of -20dB to 0dB.

[0046] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A gain-adjustable single-ended voltage-to-differential current circuit, characterized in that, include: Single-ended voltage to differential current conversion module and adjustable gain control module; The single-ended voltage to differential current module adopts a symmetrical fully differential structure and its function is to convert single-ended voltage into differential current. The positive input terminal of the single-ended voltage to differential current module is connected to the input voltage Vin, and the reverse input terminal is connected to the reference voltage VREF. The positive output current is Icp, and the reverse output current is Icn. The adjustable gain control module is used to adjust the gain of the output differential current of the single-ended voltage to differential current module. The positive input terminal of the adjustable gain control module is connected to the positive output terminal of the single-ended voltage to differential current module, and the negative input terminal of the adjustable gain control module is connected to the negative output terminal of the single-ended voltage to differential current module. The positive input current is Icp, and the negative input current is Icn. The adjustable gain control module is also connected to the gain control voltage VCT and the adjustable current adder power supply voltage VLDO. The positive output current of the adjustable gain control module is Iop, and the negative output current is Ion.

2. The gain-adjustable single-ended voltage-to-differential current circuit as described in claim 1, characterized in that, The single-ended voltage to differential current module includes: a first operational amplifier, a second operational amplifier, a first current source, a second current source, a first resistor, a second resistor, a first bipolar transistor, a second bipolar transistor, a first PMOS transistor, and a second PMOS transistor MP2; The first operational amplifier and the second operational amplifier provide sufficient gain to ensure stable and reliable negative feedback in the loop. The output terminal of the first operational amplifier is connected to the gate of the first PMOS transistor, the positive input terminal of the first operational amplifier is connected to the collector of the first bipolar transistor, the first end of the first resistor, and the first end of the first current source, and the inverting input terminal of the first operational amplifier is connected to the input voltage Vin. The output terminal of the second operational amplifier is connected to the gate of the second PMOS transistor, the positive input terminal of the second operational amplifier is connected to the collector of the second bipolar transistor, the second end of the first resistor, and the first end of the second current source, and the inverting input terminal of the second operational amplifier is connected to the reference voltage VREF. The first bipolar transistor, the second bipolar transistor, and the second resistor together determine the emitter voltage of the first bipolar transistor and the second bipolar transistor; the emitter of the first bipolar transistor is connected to the drain of the first PMOS transistor, the base of the first bipolar transistor is connected to the base of the second bipolar transistor, and the first end of the second resistor is connected; the emitter of the second bipolar transistor is connected to the drain of the second PMOS transistor; the first end of the second resistor is connected to the base of the first bipolar transistor and the second bipolar transistor, and the second end of the second resistor is connected to the reference voltage VREF; The first PMOS transistor and the second PMOS transistor function as current mirrors; the first resistor, together with the first current source and the second current source, determines the maximum allowable input swing of the circuit; the source terminals of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage VDD; the other terminals of the first current source and the second current source are connected to ground GND.

3. The gain-adjustable single-ended voltage-to-differential current circuit as described in claim 2, characterized in that, The adjustable gain control module includes: an adjustable current adder and a gain adjustment module; The adjustable current adder adopts a differential structure to form a static complementary differential current, including: a third current source, a fourth current source, a fifth current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third bipolar transistor, a fourth bipolar transistor, and a third resistor; The fourth NMOS transistor, together with the third resistor and the fifth current source, generates a comparison voltage, which serves as the comparison voltage for the gain control voltage VCT. The gate and drain of the fourth NMOS transistor are connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the first terminal of the fifth current source, the gate of the first NMOS transistor, and the gate of the third NMOS transistor. The second terminal of the fifth current source is connected to the power supply voltage VDD. The third current source, the fourth current source, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the third bipolar transistor, and the fourth bipolar transistor constitute a current adder circuit to provide static complementary currents IXP and INX. The drain of the first NMOS transistor is connected to the collector and base of the third bipolar transistor, the drain of the second NMOS transistor is connected to the collector and base of the fourth bipolar transistor, and the drain of the third NMOS transistor. The gate of the second NMOS transistor is connected to the gain control voltage VCT. The sources of the third and fourth bipolar transistors are both connected to the adjustable current adder power supply voltage VLDO. The first terminal of the third current source is connected to the source of the first and second NMOS transistors, and the first terminal of the fourth current source is connected to the source of the third NMOS transistor. The source of the fourth NMOS transistor, the second terminal of the third current source, and the second terminal of the fourth current source are connected to ground GND.

4. The gain-adjustable single-ended voltage-to-differential current circuit as described in claim 3, characterized in that, The gain adjustment module adopts a symmetrical proportional current mirror structure to proportionally adjust the output current of the single-ended voltage to differential current module; the gain adjustment module includes: a fifth NMOS transistor and a sixth NMOS transistor, a fifth bipolar transistor, a sixth bipolar transistor, a seventh bipolar transistor, an eighth bipolar transistor, a third PMOS transistor, and a fourth PMOS transistor; The third and fourth PMOS transistors are current mirrors, copying the output differential current of the single-ended voltage to differential current module; the gate of the third PMOS transistor is connected to the output voltage Vcp of the first operational amplifier, and the drain of the third PMOS transistor is connected to the emitter of the fifth and seventh bipolar transistors; the gate of the fourth PMOS transistor is connected to the output voltage Vcn of the second operational amplifier, and the drain of the fourth PMOS transistor is connected to the emitter of the sixth and eighth bipolar transistors. The fifth, sixth, seventh, and eighth bipolar transistors are current mirrors, wherein the fifth and sixth bipolar transistors copy the reverse output current IXN of the adjustable current adder, and the seventh and eighth bipolar transistors copy the forward output current IXP of the adjustable current adder; the bases of the fifth and sixth bipolar transistors are simultaneously connected to the collector and base of the third bipolar transistor in the adjustable current adder, and the bases of the seventh and eighth bipolar transistors are simultaneously connected to the collector and base of the fourth bipolar transistor in the adjustable current adder; The fifth and sixth NMOS transistors form a load circuit, serving to provide a current mirror copy for subsequent circuits. The gate and drain of the fifth NMOS transistor are both connected to the collector of the seventh bipolar transistor, and the gate and drain of the sixth NMOS transistor are both connected to the collector of the eighth bipolar transistor. The sources of the third and fourth PMOS transistors are both connected to the power supply voltage VDD, and the collectors of the fifth and sixth bipolar transistors, as well as the sources of the fifth and sixth NMOS transistors, are all connected to ground GND.

5. The gain-adjustable single-ended voltage-to-differential current circuit as described in claim 4, characterized in that, The first current source and the second current source are of equal magnitude, and the current value is 10*ISS; The current value of the third current source is 9*ISS, and the current values ​​of the fourth and fifth current sources are ISS; where ISS is the unit current copied by the current mirror.

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