A differential multi-band cross-voltage domain rejection power noise voltage controlled oscillator

Abstract

This invention relates to the field of high-speed signal transmission technology, specifically to a differential multi-band voltage-domain cross-voltage-domain voltage-controlled oscillator (VCO) for suppressing power supply noise. It includes a frequency and phase detector, a charge pump, a low-pass filter, a VCO_BIAS module, and a voltage-controlled oscillator unit. The charge pump and low-pass filter generate a differential control voltage; the VCO_BIAS module receives the differential control voltage and converts it into a differential current; the voltage-controlled oscillator unit receives the differential current; the VCO_BIAS module integrates a bias structure to suppress power supply noise, reducing the sensitivity of the tail current transistor of the voltage-controlled oscillator unit to power supply noise due to channel length modulation effects, and improving the jitter of the phase-locked loop (PLL) output frequency. In this invention, by constructing a differential structure, a cross-voltage-domain design, and tunable bias and load, a wide frequency range output under low-voltage power supply is achieved, and clock jitter caused by power supply noise is effectively suppressed.

Description

Technical Field

[0001] This invention relates to the field of high-speed signal transmission technology, and more specifically, to a voltage-controlled oscillator for differential multi-band cross-voltage domain suppression of power supply noise. Background Technology

[0002] High-speed signal transmission refers to technologies that transmit data at rates ranging from megabits per second (Mbps) to gigabits per second (Gbps), with transmission rates covering a wide range depending on application requirements. Taking the High Definition Multimedia Interface (HDMI) as an example, its transmission rates vary from 270 Mbps for 480P@60Hz to 5.94 Gbps for 4K@60Hz. According to the HDMI protocol, to meet the diverse application requirements from standard definition to ultra-high definition, the phase-locked loop (PLL) output frequency providing the clock must cover a wide frequency range from 270 MHz to 2.97 GHz. This technology is widely used in modern high-speed serial interfaces, data center interconnects, and high-definition video transmission, and is a key support for achieving high-bandwidth data interaction.

[0003] However, existing technologies face significant challenges in the aforementioned application contexts. In ultra-deep submicron processes (below 90nm), circuits typically operate in a low-voltage supply domain of 0.8–1.2V to reduce power consumption. To meet the requirements of high-speed signal transmission for a wide output frequency range, the voltage-controlled oscillator (VCO) in a traditional phase-locked loop requires a large voltage regulation range to control the oscillation frequency. This fundamentally contradicts the limited voltage swing in the low-voltage supply domain, meaning that traditional architectures struggle to achieve wide frequency coverage at low voltages.

[0004] Furthermore, the channel length modulation effect of MOSFETs in deep submicron processes is significant. Even small fluctuations in the power supply voltage can directly interfere with the stability of the current source transistor, leading to large frequency jitter in the PLL output clock. This degraded clock signal directly affects the accurate recovery of data in high-speed receiving circuits, limits the reliability of the system in complex electromagnetic environments, and reduces its application flexibility across multiple signal transmission standards.

[0005] To address the aforementioned power supply noise issue, existing technologies typically employ external filtering circuits or on-chip low-dropout linear regulators (LDOs) to provide a "clean" power supply voltage for the voltage-controlled oscillator (VCO). However, this approach not only increases chip area and system cost, but the LDO itself also has a limited power supply rejection ratio (PSRR) at high frequencies, resulting in less than ideal suppression of high-frequency power supply noise. More importantly, in wideband applications, traditional single-domain designs cannot simultaneously balance the power consumption advantages of low-voltage logic with the large swing requirements of analog modules. Summary of the Invention

[0006] The purpose of this invention is to address the problems of insufficient bandwidth coverage and worsened clock jitter caused by the limited voltage swing in the low-voltage power domain and the sensitivity to power supply noise in deep submicron processes in existing conventional phase-locked loop architectures, as well as the problems of large area and weak high-frequency suppression capability of existing external voltage regulation methods such as LDOs.

[0007] The purpose of this invention is to provide a differential multi-band voltage-domain suppressed power supply noise voltage-controlled oscillator. By constructing a differential structure, a voltage-domain design, and an integrated tunable bias and load with a negative feedback mechanism within the bias circuit, it achieves wide frequency range output under low voltage power supply and effectively suppresses clock jitter caused by power supply noise from the circuit source.

[0008] To achieve the above objectives, the present invention aims to provide a differential multi-band voltage-domain suppression voltage-controlled oscillator for use in a phase-locked loop (PLL). The PLL includes a frequency and phase detector, a charge pump, a low-pass filter, a VCO_BIAS module, and a voltage-controlled oscillator unit, wherein:

[0009] The charge pump and the low-pass filter are located in the high-voltage power supply domain and are used to generate a pair of differential control voltages with a large adjustment range.

[0010] The VCO_BIAS module is connected to the low-pass filter and is used to receive the differential control voltage and convert it into differential current, while completing the conversion from the high-voltage power domain to the low-voltage power domain.

[0011] The voltage-controlled oscillator unit is connected to the VCO_BIAS module and is located in the low-voltage power supply domain. It is used to receive the differential current and realize multi-band frequency output through adjustable output load capacitor and bias current.

[0012] The VCO_BIAS module integrates a bias structure to suppress power supply noise, which reduces the sensitivity of the tail current transistor of the voltage-controlled oscillator unit to power supply noise due to the channel length modulation effect and improves the jitter of the phase-locked loop output frequency.

[0013] Unlike existing technologies that isolate noise through external voltage regulators (such as LDOs), the noise suppression structure of this invention utilizes a negative feedback mechanism built into the VCO_BIAS module to directly track and compensate for fluctuations in the power supply voltage, thereby reducing the modulation effect of the tail current at its source and achieving superior high-frequency noise suppression capabilities. At the same time, it avoids the use of high-cost components such as inductors, making it more suitable for low-cost, wide-band coverage (such as covering the mid-to-low frequency band from several hundred MHz to 3 GHz) application scenarios.

[0014] As a further improvement to this technical solution, the voltage-controlled oscillator unit includes a ring oscillator composed of multi-stage differential VCO_CELL and an output drive stage VCO_BUF for providing load drive capability.

[0015] As a further improvement to this technical solution, the VCO_CELL includes an input pair of transistors, a cross pair of transistors, a fixed current bias transistor, a differential current bias transistor, a load resistor, and a load capacitor array controlled by an N-bit control code; by selecting different bias current and load capacitor values, multiple frequency bands can be output.

[0016] As a further improvement to this technical solution, the VCO_BIAS module includes a differential voltage to current conversion submodule and a fixed bias current generation submodule.

[0017] The differential voltage to current conversion submodule receives the differential control voltage and generates a differential current signal for controlling the voltage-controlled oscillator unit through a current mirror structure.

[0018] The fixed bias current generation submodule generates a fixed bias current signal and provides a bias voltage for the tail current tube of the voltage-controlled oscillator unit.

[0019] As a further improvement to this technical solution, the fixed bias current generation submodule includes a current transistor with a source connected to a variable resistor array of MOS transistors. The equivalent resistance value of the variable resistor array is controlled by a multi-bit control signal. Through the source negative feedback introduced by the variable resistor, the gate-source voltage of the current transistor is dynamically adjusted to track and suppress power supply noise in the low-voltage power supply domain.

[0020] This structure achieves a high power supply rejection ratio in the low-voltage power domain without the need for a common-source cascode current mirror, overcoming the limitations of traditional suppression methods in deep submicron low-voltage processes.

[0021] As a further improvement to this technical solution, for a specified output frequency band, the eye diagram opening or jitter value of the voltage-controlled oscillator output clock is monitored in real time or offline by on-chip or off-chip monitoring circuits. The control signal of the variable resistor array is iteratively adjusted by software algorithm to adaptively determine the optimal resistance value that maximizes the eye diagram opening or minimizes the jitter value, thereby achieving the optimal noise suppression effect for different process angles, power supply noise spectrum characteristics and temperature changes.

[0022] As a further improvement to this technical solution, the voltage of the high-voltage power supply domain is 3.0 to 3.6V, and the voltage of the low-voltage power supply domain is 0.8 to 1.2V.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] 1. In this differential multi-band cross-voltage domain suppression voltage-controlled oscillator, by adopting a cross-voltage domain structure, the charge pump is placed in the high-voltage domain to generate a differential control voltage with a large adjustment range, and then switched to the low-voltage domain to control the VCO unit. This effectively solves the problem of limited VCO frequency adjustment range under low-voltage power supply, broadens the application flexibility of PLL in the field of high-speed signal transmission, and realizes multi-band frequency output through the adjustable load capacitor and bias current in the VCO unit, which can flexibly cover a variety of application needs from standard definition to ultra-high definition.

[0025] By designing an adjustable source resistor bias structure in the VCO_BIAS module, the modulation of VCO tail current by power supply noise is effectively suppressed by the negative feedback mechanism, significantly reducing the jitter of PLL output frequency, greatly improving the quality of clock signal and system reliability. Furthermore, through software iterative adjustment, the optimal power supply noise suppression parameters can be found for different operating frequency bands and power supply noise characteristics, enhancing the flexibility and adaptability of practical applications.

[0026] 2. In this differential multi-band cross-voltage domain voltage-controlled oscillator for suppressing power supply noise, a ring oscillator structure is adopted, which avoids the use of high-cost inductors. At the same time, power supply noise is suppressed through the bias structure inside the VCO_BIAS module instead of external or on-chip LDOs, realizing a low-cost, highly integrated design solution that can meet the specific requirements of high-speed interface protocols such as HDMI for wide-band coverage (covering the mid-to-low frequency band) and low-voltage domain output.

[0027] This invention achieves excellent power supply noise suppression and wide bandwidth coverage without using an LDO by using the negative feedback bias structure embedded in the VCO_BIAS module and the cross-voltage domain architecture. It is especially suitable for high-speed interface applications such as HDMI that require low-voltage domain output (0.8~1.2V). Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a traditional phase-locked loop;

[0029] Figure 2 This is a schematic diagram of the phase-locked loop structure of the present invention;

[0030] Figure 3 This is a schematic diagram of the VCO unit structure of the present invention;

[0031] Figure 4 This is a schematic diagram of the VCO_CELL circuit structure of the present invention;

[0032] Figure 5 This is a schematic diagram of the differential voltage to current conversion submodule circuit structure of the present invention;

[0033] Figure 6This is a schematic diagram of the circuit structure of the fixed bias current generating submodule of the present invention;

[0034] Figure 7 These are schematic diagrams of two types of noise from the two VCO circuit structures of the present invention.

[0035] Figure 8 Eye diagram comparison of the output frequency of the two VCO circuit structures of this invention. Figure 1 ;

[0036] Figure 9 Eye diagram comparison of the output frequency of the two VCO circuit structures of this invention. Figure 2 . Detailed Implementation

[0037] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] like Figure 1 The diagram shows a block diagram of a traditional phase-locked loop. The input signal CKI and the feedback signal CKF (the output clock is obtained by the frequency divider DIV) enter the phase detector (PFD) to generate phase comparison signals UP and DN. These signals are then converted into a charging and discharging current Icp by the charge pump (CP), and then pass through a low-pass filter (LPF) to generate a control voltage VC, which enters the voltage-controlled oscillator (VCO). Finally, an output clock CK[N:1] with N phases is generated. Depending on the actual application requirements, N can be 2, 4, or 8.

[0039] For high-speed signal transmission, the transmission rate covers a wide range. Taking HDMI as an example, the transmission rate for 480P@60Hz is 270Mbps, and the transmission rate for 4K@60Hz is 5.94Gbps. According to the HDMI protocol, to meet the application requirements from 480P to 4K, the PLL output frequency must be able to cover 270MHz to 2.97GHz.

[0040] For ultra-deep submicron processes (below 90nm), the power supply voltage in the low-voltage power domain is relatively low, typically 0.8V to 1.2V. To meet high-speed transmission rate requirements, Figure 1 In traditional phase-locked loops (PLLs), each module needs to operate in a low-voltage power supply domain (0.8~1.2V). In order to achieve a wide output frequency range for the PLL, the adjustment range of VC is required to be large. This obviously contradicts the low power supply voltage of VCO. That is, the traditional PLL architecture cannot meet the high-speed signal transmission requirements of a wide output frequency range.

[0041] Therefore, please refer to Figures 2-9 As shown, the objective of this invention is to provide a differential multi-band voltage-domain suppressed power supply noise voltage-controlled oscillator. Compared with traditional phase-locked loops, the phase-locked loop of this invention adopts a differential architecture. Figure 1 The VCO_BIAS module has been added to the basic version.

[0042] Among them, the frequency and phase detector (PFD), charge pump (CP), low-pass filter (LPF) and VCO_BIAS module are located in the high voltage power domain (HV_A domain), while the voltage-controlled oscillator (VCO) unit is located in the low voltage power domain (LV_A domain).

[0043] A charge pump and low-pass filter generate a pair of differential control voltages, VCP and VCN, which have a wide adjustment range (e.g., VCP-VCN can reach ±1V). VCP / VCN enters the VCO_BIAS module, which converts them into differential currents and performs the conversion from the high-voltage domain to the low-voltage domain. The differential current is then fed into the VCO unit. The VCO unit achieves multi-band frequency output through adjustable output load capacitance and bias current to meet the wide output frequency range requirements of the PLL.

[0044] Specifically, such as Figure 3 As shown, the VCO unit consists of a ring oscillator composed of four differential VCO_CELL stages. VCO_BUF is the output driver stage, providing appropriate load driving capability to meet the requirements of subsequent circuit modules. CK[8:1] is an 8-phase output clock, and depending on the application requirements, 2 or 4 phases can also be selected for output.

[0045] Furthermore, VCO_CELL includes input transistors M1 and M2, cross transistors M3 and M4, a fixed current bias transistor M5, differential current bias transistors M6 and M7, and load resistors R1 and R2. The load capacitor arrays C11, C12, C1N and C21, C22, C2N are controlled by an N-bit control code S1. <n:1>The capacitor values ​​are controlled by a binary weighted relationship (C11=C0, C12=C0*2, C1N=C0*2N-1). Different bias current and load capacitance values ​​can be selected to achieve multi-band frequency output. For example, if the required output frequency range is 250MHz to 2.5GHz, it can be divided into K frequency bands, such as K=5. The five frequency bands correspond to: 250MHz to 600MHz, 600MHz to 1GHz, 1GHz to 1.5GHz, 1.5GHz to 2GHz, and 2GHz to 2.5GHz, respectively. Different bias current and load capacitance values ​​can be set for each of the five frequency bands. Of course, the frequencies of the five bands can partially overlap, for example: 250MHz to 650MHz, 600MHz to 1GHz, 950MHz to 1.5GHz, 1.45GHz to 2GHz, and 1.95GHz to 2.5GHz, which is also feasible.

[0046] It is worth noting that in practical applications, the bias current of transistor M5, which acts as the tail current transistor of the VCO, is easily affected by the channel length modulation effect. Generally, the NVB voltage is fixed, meaning the gate-source voltage of transistor M5 is fixed. However, LV_A contains power supply noise with multiple frequency components. As the power supply noise in LV_A fluctuates, the voltage at node M0_S also fluctuates accordingly, causing fluctuations in the drain-source voltage of transistor M5. This, in turn, leads to fluctuations in the bias current of transistor M5. In other words, the bias current of transistor M5 is modulated by the power supply noise, thus deteriorating the jitter performance of the PLL output frequency and consequently worsening the performance of subsequent circuit modules.

[0047] In existing technologies, common methods to improve power supply noise suppression include increasing the MOSFET channel length and using a cascode current mirror structure. However, ultra-deep submicron processes limit the upper limit of the low-voltage transistor's channel length, and excessive channel length significantly increases chip area. Therefore, simply increasing the channel length does not effectively mitigate the impact of power supply noise. Furthermore, ultra-deep submicron processes also impose limitations on low-voltage power supplies, typically ranging from 0.8 to 1.2V. Under such low voltage conditions, the cascode current mirror cannot function effectively.

[0048] To address the modulation problem of power supply noise on the VCO tail current transistor M5 under low-voltage power supply domain, this invention proposes a bias structure in VCO_BIAS to suppress power supply noise. For example... Figure 5 , Figure 6 As shown, the VCO_BIAS module includes a differential voltage-to-current submodule ( Figure 5 ) and fixed bias current generation submodule ( Figure 6 ).

[0049] exist Figure 5 In this circuit, the differential voltage-to-current submodule receives the differential control voltage VCP / VCN. Input transistors SM1 and SM2, along with resistor R0, complete the conversion from differential voltage to current. After being precisely mirrored by cascode current mirrors (PM1 to PM8), the current finally flows into the low-voltage domain devices SM5 and SM6, generating currents IBN and IBP (i.e., differential current signals ICKP / ICKN), respectively.

[0050] Specifically, Iref1 is the reference bias current. Iref1 first enters PS0, and then passes through the M-bit signal S0. <m:1>The controlled current mirrors are PS1 to PSM (the size ratio of each PMOS is WPS1:WPS2:WPSM=1:2:2). M-1 The current enters SM7, and then, through a mirror, enters SM8 / SM4 to provide bias current for the differential voltage-to-current conversion module. SM1 / SM2 are the input transistor pair, which, together with resistor R0, complete the differential voltage-to-current conversion operation. VCP / VCN is the output of the differential charge pump. When VCP is greater than VCN, the current in SM1 is greater than the current in SM2, and the current in PM1 is greater than the current in PM2. Through the current mirror, the current in PM3 is greater than the current in PM4, and finally, the current IBN flowing into SM5 is greater than the current IBP flowing into SM6. Similarly, when VCP is less than VCN, the final current IBP flowing into SM6 is greater than the current IBN flowing into SM5. IBN and IBP represent the currents flowing into SM5 and SM6, respectively, indicated by arrows in the diagram. VB1 is the bias voltage. PM5-PM8 and PM1-PM4 form a common-source cascode current mirror, which improves the accuracy of the current mirror and also enhances the power supply noise suppression capability.

[0051] Figure 5 Within the dashed box, SM5 / SM6 are low-voltage domain devices, while the rest are high-voltage domain devices. The current from input transistors SM1 and SM2 is ultimately mirrored to PM3 / PM7 and PM4 / PM8. Since the VCO_CELL operates in the low-voltage domain, all its devices are low-voltage domain devices. Therefore, to achieve accurate current mirroring of SM5 / SM6 / SM7 in the VCO_CELL, the current transistors used for mirroring must also be low-voltage domain devices of the same type. In this way, the current from PM3 / PM7 and PM4 / PM8 enters SM5 / SM6, and the current flows from high-voltage devices to low-voltage devices, thus completing the current conversion from the high-voltage domain to the low-voltage domain and providing accurate differential bias current for SM6 / SM7 in the VCO_CELL.

[0052] exist Figure 6 In the VCO_CELL, the fixed bias current generation submodule is used to generate the bias voltage NVB of the tail current transistor M5. The reference current Iref2 is transmitted through current mirrors PQ0 to PQM (by signal S2). <m:1>After mirroring (control), the current flows into the low-voltage domain device MB1. The drain of MB1 provides the bias voltage NVB. The source of MB1 is connected to a control signal IB controlled by bit L+1. <l:1>A controlled array of variable resistors (MQ0 to MQL) of MOSFETs. These variable resistors utilize the source-drain on-resistance of the MOSFETs to suppress power supply noise through negative feedback.

[0053] Specifically, Iref2 is the reference bias current. Iref2 first enters PQ0, and then passes through the M-bit signal S2. <m:1>The controlled current mirrors PQ1 to PQM (the size ratio of each PMOS is WPQ1:WPQ2:WPQM = 1:2:2) M-1 The current flows into MB1, and the bias current into MB1 is IVCO, indicated by the arrow in the diagram. The corresponding bias voltage for MB1 is NVB, and the bias current is provided by M5 of VCO_CELL via NVB. The source of MB1 is connected to a variable resistor composed of a MOSFET array. This variable resistor utilizes the source-drain on-resistance of the MOSFETs. Through negative feedback adjustment of this variable resistor, the influence of power supply noise is tracked and suppressed. The variable resistor array has L+1 positions (the size ratio of each NMOS is WMQ1:WMQ2:WMQL = 1:2:2). L-1 The dashed box contains low-voltage devices. The gate of MQ0 is connected to the low-voltage power supply LV_A, forming a drain-source path to ground to prevent damage to the low-voltage devices within the dashed box during power-on. The principle is as follows: when the low-voltage power supply LV_A experiences increased noise, the gate voltages of MQ0 to MQL increase, the equivalent resistance of the adjustable resistor array decreases, leading to an increase in the gate-source voltage of MB1 and its drain current, which in turn reduces the NVB voltage. This compensates for the increased current caused by the increased drain voltage (M0_S) of transistor M5 in VCO_CELL, thereby reducing the influence of channel length modulation, suppressing power supply noise in LV_A, and improving the jitter performance of the VCO output frequency. For different operating conditions and noise types, IB can be iteratively adjusted via software. <l:1>The optimal resistance value can be found by monitoring the eye diagram opening or jitter value of the VCO output clock.

[0054] As a specific embodiment of the present invention, a UMC 22nm process is used, with M=3, N=3, L=4, Iref1=Iref2=20uA, unit capacitance C0=10fF, and low-voltage power supply LV_A=0.9V. Under this configuration, the PLL can output a frequency range covering 200MHz to 4GHz, which can be divided into 8 frequency bands, for example: 200MHz~600MHz, 600MHz~1GHz, 1GHz~1.5GHz, 1.5GHz~2GHz, 2GHz~2.5GHz, 2.5GHz~3GHz, 3GHz~3.5GHz, and 3.5GHz~4GHz. By changing S0... <m:1> / S1 <n:1> / S2 <m:1>The control codes can be used to obtain any desired frequency band. For a selected frequency band, the IB can be iteratively adjusted via software. <l:1>This allows us to obtain the optimal MB1 source resistor value for suppressing power supply noise.

[0055] In summary, this invention effectively resolves the contradiction between wide bandwidth coverage and low jitter output in low-voltage PLLs by employing a differential architecture, cross-voltage domain design, tunable VCO units, and a VCO_BIAS module with power supply noise suppression capabilities. This solution improves clock signal quality while expanding its application flexibility in high-speed signal transmission, providing an economical and efficient solution for high-performance phase-locked loop (PLL) design.

[0056] Simulation test example

[0057] To verify the effectiveness of this invention, we will take HDMI protocol 4K (3840x2160)@60Hz as an example. The transmission rate of 4K (3840x2160)@60Hz is 5.94Gbps. The CDR circuit (clock data recovery circuit) after PLL mostly adopts a half-rate interpolation structure, that is, the 8-phase clock of PLL is given to CDR circuit. CDR circuit uses the two edges of the clock to sample data, that is, the clock frequency is half of the transmission rate, which is 2.97GHz.

[0058] Taking the UMC22nm as an example, simulations compare the performance differences of two VCO circuit structures (1#: no VCO_BIAS source resistor, 2#: with VCO_BIAS source resistor) under power supply noise. The VCO output frequency is 2.97GHz. In VCO_CELL, N=3, S1<3:1>=001; in VCO_BIAS, M=3 / L=4, S0<3:1>=101, S2<3:1>=111, IB<4:1>=0001; the typical operating voltage of LV_A is 1.0V.

[0059] First, the power supply rejection ratio (PSRR) of the two VCO circuit structures were compared. The output frequencies were simulated at LV_A=0.9V / 1.0V / 1.1V respectively. In order to make the output frequency close to 2.97GHz at LV_A=1.0V, the VCP / VCN of the two circuits were slightly different. The results are shown in Table 1.

[0060] Table 1. Power supply rejection ratio of two VCO circuit structures

[0061] The PSRR for the two ranges of 0.9–1.0V and 1.0–1.1V is calculated and shown in Table 2.

[0062] Table 2 Power Supply Rejection Ratio of Two VCO Circuit Structures

[0063] In the 0.9–1.0V range, the structure of the present invention can improve PSRR by 5.18dB, and in the 1.0–1.1V range, the structure of the present invention can improve PSRR by 9.53dB, demonstrating a significant effect in suppressing power supply noise.

[0064] Then, the output phase jitter performance of the two VCO circuit structures was compared under two different power supply noise conditions. The first type of noise was triangular wave modulation noise with a frequency of 2MHz and a peak-peak amplitude of 80mV; the second type of noise was random white noise with a peak-peak amplitude of 200mV. The waveforms of the two noises are shown below. Figure 7 As shown.

[0065] Figure 8 , Figure 9 Eye diagrams comparing the output frequencies of two VCO circuit structures (1#: no VCO_BIAS source resistor, 2#: with VCO_BIAS source resistor). Figure 8 , Figure 9 The left side is number 1#, and the right side is number 2#. Figure 8 Corresponding to the first type of noise, Figure 9 Corresponding to the second type of noise, CK_OUT0 in the diagram corresponds to... Figure 3 CK[1].

[0066] from Figure 8 , Figure 9 It can be seen that for the first type of noise, the peak-peak jitter of 1# / 2# is 168ps / 51ps respectively, and for the second type of noise, the peak-peak jitter of 1# / 2# is 49ps / 32ps respectively. That is, the output jitter of the VCO circuit of the present invention is much smaller.

[0067] In summary, the VCO circuit of this invention has significant power supply noise suppression capabilities in terms of both PSRR and jitter.

[0068] In summary, to improve power supply performance, the voltage-controlled oscillator of this invention simply adopts a bias structure with a negative feedback mechanism integrated within the VCO_BIAS module, without using external filtering or an on-chip low-dropout linear regulator (LDO). This not only avoids the problems of increased chip area and limited high-frequency suppression capability caused by using an LDO, but also achieves effective suppression of power supply noise from the circuit's source. Secondly, for the application requirements of high-speed interfaces such as HDMI, the VCO output is required to be in the low-voltage domain (0.8~1.2V) so that it can be directly connected to the subsequent clock data recovery circuit (CDR). Therefore, this invention adopts a cross-voltage domain architecture, setting the charge pump and low-pass filter in the high-voltage power domain to generate a wide range of differential control voltages, which are then converted to the low-voltage domain by the VCO_BIAS module to control the VCO unit, thereby achieving a wide frequency range output in the low-voltage domain.

[0069] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended technical solutions and their equivalents. < / n:1> < / m:1>

Claims

1. A differential multi-band voltage-controlled oscillator for suppressing power supply noise across voltage domains, applied in a phase-locked loop, characterized in that: The phase-locked loop includes a frequency and phase detector, a charge pump, a low-pass filter, a VCO_BIAS module, and a voltage-controlled oscillator unit, wherein: The charge pump and the low-pass filter are located in the first power domain and are used to generate a pair of differential control voltages with adjustable ranges. The VCO_BIAS module is connected to the low-pass filter and is used to receive the differential control voltage and convert it into differential current, while completing the conversion from the first power domain to the second power domain with a voltage value lower than that of the first power domain. The voltage-controlled oscillator unit is connected to the VCO_BIAS module and is located in the second power domain. It is used to receive the differential current and realize multi-band frequency output through adjustable output load capacitor and bias current. The VCO_BIAS module integrates a bias structure based on a negative feedback mechanism to suppress power supply noise. This structure is used to dynamically track and compensate for voltage fluctuations in the second power domain, thereby reducing the sensitivity of the tail current transistor of the voltage-controlled oscillator unit to power supply noise due to the channel length modulation effect and improving the jitter of the phase-locked loop output frequency.

2. The voltage-controlled oscillator for differential multi-band cross-voltage domain noise suppression according to claim 1, characterized in that: The voltage-controlled oscillator unit includes a ring oscillator composed of multi-stage differential VCO_CELL and an output drive stage VCO_BUF for providing load drive capability.

3. The voltage-controlled oscillator for differential multi-band cross-voltage domain noise suppression according to claim 2, characterized in that: The VCO_CELL includes an input pair of transistors, a cross pair of transistors, a fixed current bias transistor, a differential current bias transistor, a load resistor, and a load capacitor array controlled by an N-bit control code; by selecting different bias current and load capacitor values, multiple frequency bands can be output.

4. The voltage-controlled oscillator for differential multi-band cross-voltage domain noise suppression according to claim 1, characterized in that: The VCO_BIAS module includes a differential voltage to current conversion submodule and a fixed bias current generation submodule. The differential voltage to current conversion submodule receives the differential control voltage and generates a differential current signal for controlling the voltage-controlled oscillator unit through a current mirror structure. The fixed bias current generation submodule generates a fixed bias current signal and provides a bias voltage for the tail current tube of the voltage-controlled oscillator unit.

5. The voltage-controlled oscillator for differential multi-band cross-voltage domain noise suppression according to claim 4, characterized in that: The fixed bias current generation submodule includes a current transistor with a source connected to a variable resistor array of MOS transistors. The equivalent resistance of the variable resistor array is controlled by a multi-bit control signal. Through the source negative feedback introduced by the variable resistor, the gate-source voltage of the current transistor is dynamically adjusted to track and suppress power supply noise in the low-voltage power supply domain.

6. The voltage-controlled oscillator for differential multi-band cross-voltage domain noise suppression according to claim 5, characterized in that: For a given output frequency band, the eye diagram opening or jitter value of the voltage-controlled oscillator output clock is monitored in real time or offline by on-chip or off-chip monitoring circuits. The control signal of the variable resistor array is iteratively adjusted by software algorithm to adaptively determine the optimal resistance value that maximizes the eye diagram opening or minimizes the jitter value.

7. The differential multi-band voltage-controlled oscillator for suppressing power supply noise across voltage domains according to any one of claims 1-6, characterized in that: The voltage of the high-voltage power supply domain is 3.0 to 3.6V, and the voltage of the low-voltage power supply domain is 0.8 to 1.2V.

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