A power semiconductor circuit and chip

Abstract

The application provides a power semiconductor circuit and chip, the circuit comprises a chip, a channel is arranged in the chip, the circuit further comprises a flip voltage follower (FVF) used as a voltage buffer to ensure stable current output in the circuit, a compensation unit electrically connected to the two ends of the flip voltage follower (FVF) to ensure loop stability without output capacitor, and a non-inverting gain stage electrically connected to a power input end (VIN), a ground wire (GND) and the flip voltage follower (FVF) respectively to offset the channel length modulation effect during operation of the chip by increasing open-loop gain. The power semiconductor circuit and chip can effectively optimize the structure of the power semiconductor circuit, so that the circuit can meet the condition of no output capacitor and has the characteristics of high stability and high gain.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically, to a power semiconductor circuit and chip with no output capacitor and high stability and high gain. Background Technology

[0002] In 90nm CMOS technology, the capacitorless low-dropout linear regulator (OCL-LDO) has significant drawbacks. Specifically, under this process, the OCL-LDO has a quiescent current as high as 6mA, which can easily reduce the overall stability of the regulator. Therefore, it is necessary to integrate a 0.6nF capacitor for stabilization. However, integrating the capacitor for stabilization increases the area of ​​the integrated OCL-LDO chip to 0.098mm². 2 Furthermore, the chip's load regulation is only 90mV / 50mA. This will severely affect the channel length modulation effect of the components within the chip, thereby reducing the loop gain of the internal circuitry and making it unable to offset the parameter drift caused by the manufacturing process, ultimately leading to a deterioration in the regulator's performance. Summary of the Invention

[0003] In view of this, the present invention aims to propose a power semiconductor circuit and chip to solve the problems of low stability and loop gain of low dropout linear regulators without output capacitors under low power consumption in the prior art. Even with multiple capacitors, the chip area is still easily increased, and the output poles are easily shifted upward and the phase margin is insufficient under low load current. The present invention aims to optimize the structure of the power semiconductor circuit so that it can ensure high stability and high gain without output capacitors.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] This invention relates to a power semiconductor circuit and chip. The power semiconductor circuit includes a chip with a channel within it. The circuit further includes:

[0006] Flip voltage follower (FVF): Used as a voltage buffer to ensure regulated current output within the circuit;

[0007] Compensation unit: Both ends are electrically connected to the flip voltage follower FVF to ensure loop stability without output capacitor;

[0008] Non-inverting gain stage: Electrically connected to the power input VIN, ground GND, and flip voltage follower FVF respectively, used to increase the open-loop gain to counteract the channel length modulation effect during chip operation.

[0009] Furthermore, the flip voltage follower (FVF) includes a common-source differential pair and a power output stage; one end of the common-source differential pair is electrically connected to the compensation unit, the non-inverting gain stage, and the power output stage, respectively; the power output stage is electrically connected to the power input terminal VIN, the non-inverting gain stage, and the compensation unit, respectively; the other end of the common-source differential pair is grounded.

[0010] Furthermore, the flip voltage follower FVF also includes a bias circuit module and an output setting voltage VSET; both ends of the bias circuit module and the output setting voltage VSET are electrically connected to the common source differential pair and the ground GND, respectively; both ends of the bias circuit module are electrically connected to the common source differential pair and the power input terminal VIN, respectively.

[0011] Furthermore, the common-source differential pair consists of a first switch M11 and a second switch M15. Both the first switch M11 and the second switch M15 are MOSFETs.

[0012] Furthermore, the sources of the first switch M11 and the second switch M15 are connected in parallel and then electrically connected to ground GND through the bias circuit module; the gates of the first switch M11 and the second switch M15 are electrically connected to ground GND through the bias circuit module and the output setting voltage VSET, respectively; the drain of the first switch M11 is electrically connected to the compensation unit and the power output stage, respectively; the drain of the second switch M15 is electrically connected to the compensation unit, the non-inverting gain stage, and the bias circuit module, respectively.

[0013] Furthermore, the power output stage uses a core power transistor MP to achieve high-current regulated output in the circuit. The core power transistor MP is a MOS transistor. The gate of the core power transistor MP is electrically connected to the non-inverting gain stage, and the drain of the core power transistor MP is electrically connected to the power input terminal VIN. The source of the core power transistor MP is electrically connected to the drain of the first switching transistor M11 and the compensation unit.

[0014] Furthermore, the bias circuit module includes a first current source IBIAS11, a second current source IBIAS12, and a bias voltage VBIAS; the two ends of the first current source IBIAS11 are electrically connected to the source of the first switching transistor M11 and the ground GND, respectively; one end of the second current source IBIAS12 is electrically connected to the drain of the second switching transistor M15, the compensation unit, and the non-inverting gain stage, respectively, and the other end of the second current source IBIAS12 is electrically connected to the power input terminal VIN; the two ends of the bias voltage VBIAS are electrically connected to the gate of the second switching transistor M15 and the ground GND, respectively.

[0015] Furthermore, the compensation unit uses a Miller capacitor CM. One end of the Miller capacitor CM is electrically connected to the drain of the second switching transistor M15, the non-inverting gain stage, and the second current source IBIAS12, respectively. The other end of the Miller capacitor CM is electrically connected to the source of the core power transistor MP and the drain of the first switching transistor M11, respectively.

[0016] Furthermore, the non-inverting gain stage includes a common-source amplifier M21, a current mirror, and a non-inverting bias current IBIAS2; the drain of the common-source amplifier M21 is electrically connected to the power input terminal VIN; the gate of the common-source amplifier M21 is located between the bias circuit module and the common-source differential pair, and the source of the common-source amplifier M21 is grounded through the current mirror GND; the current mirror is electrically connected to the power input terminal VIN through the non-inverting bias current IBIAS2.

[0017] Furthermore, the current mirror is composed of a first transistor M22 and a second transistor M23. The gate of the first transistor M22 is electrically connected to the drain of the first transistor M22 and the gate of the second transistor M23, respectively. The sources of the first transistor M22 and the second transistor M23 are both grounded to GND. The drain of the second transistor M23 is electrically connected to the non-inverting bias current IBIAS2 and the flip voltage follower FVF, respectively. The drain of the first transistor M22 is electrically connected to the source of the common-source amplifier M21.

[0018] A power semiconductor chip, the chip including the aforementioned power semiconductor circuit, the circuit being integrated onto the chip.

[0019] Compared with the prior art, the power semiconductor circuit and chip of the present invention have the following advantages:

[0020] By configuring the circuit described above, the structure of the power semiconductor circuit can be effectively optimized, enabling it to maintain high stability and high gain even without an output capacitor. Attached Figure Description

[0021] The accompanying drawings, which constitute a part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 This is a schematic diagram of the LDO circuit structure for a traditional FVF.

[0023] Figure 2 This is a schematic diagram of the circuit in this application;

[0024] Figure 3 This is a schematic diagram of the small-signal model corresponding to the circuit schematic in this application.

[0025] Explanation of reference numerals in the attached diagram: 10, compensation unit; 20, non-inverting gain stage; 201, current mirror; 31, common-source differential pair; 32, power output stage; 33, bias circuit module. Detailed Implementation

[0026] The inventive concepts of this disclosure will be described below using terminology commonly used by those skilled in the art to communicate the essence of their work to others skilled in the art. However, these inventive concepts may be embodied in many different forms and should not be construed as limited to the embodiments described herein.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0028] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] This embodiment is for power semiconductor chips. Similar to conventional power semiconductor chips, the overall structure consists of a constant current source and a MOSFET.

[0030] Traditional compensation methods require the use of multiple capacitors for adjustment, such as nested Miller compensation (NMC). However, this approach still tends to increase the chip area. Furthermore, at low load currents, it can easily cause the output poles to shift upwards, leading to frequency peaks and insufficient phase margin.

[0031] Therefore, it is of great significance to study how to achieve stable operation of a low-dropout linear regulator without output capacitor under low power consumption, and to enhance the loop gain in the circuit and improve the regulation performance of the regulator.

[0032] In existing technology, the LDO circuit inside a traditional flip-flop voltage follower (FVF) consists of two constant voltage sources, two constant current sources, two PMOS transistors, and one NMOS transistor (e.g., ...). Figure 1 As shown in the figure, this circuit structure is prone to problems such as poor follower stability and high power consumption.

[0033] To address the issues of low stability and loop gain in existing low-dropout linear regulators without output capacitors under low power consumption, which, even with multiple capacitors, still tend to increase chip area and cause output pole shift and insufficient phase margin under low load current, this embodiment proposes a power semiconductor circuit and chip. The power semiconductor circuit includes a chip with a channel within it, and the circuit further includes:

[0034] Flip voltage follower (FVF): Used as a voltage buffer to ensure regulated current output within the circuit;

[0035] Compensation unit 10: Both ends are electrically connected to the flip voltage follower FVF to ensure loop stability without output capacitor;

[0036] Non-inverting gain stage 20: Electrically connected to the power input terminal VIN, ground GND, and flip voltage follower FVF respectively, and used to increase the open-loop gain to counteract the channel length modulation effect when the chip is working.

[0037] In this embodiment, the non-inverting gain stage 20 and the compensation unit 10 are both integrated inside the flip voltage follower FVF, forming a composite structure of the flip voltage follower FVF containing the gain stage.

[0038] By configuring the circuit described above, the structure of the power semiconductor circuit can be effectively optimized, enabling it to maintain high stability and high gain even without an output capacitor.

[0039] The flip-flop voltage follower (FVF) includes a common-source differential pair 31 and a power output stage 32. One end of the common-source differential pair 31 is electrically connected to the compensation unit 10, the non-inverting gain stage 20, and the power output stage 32, respectively. The power output stage 32 is electrically connected to the power input terminal VIN, the non-inverting gain stage 20, and the compensation unit 10, respectively. The other end of the common-source differential pair 31 is grounded.

[0040] By combining the common-source differential pair 31 and the power output stage 32, the voltage buffer of extremely low impedance can be improved, and the voltage output node VOUT can accurately follow the voltage input terminal VIN. It can respond quickly to large signals and exhibit excellent transient response when dealing with sudden changes in load current.

[0041] The flip voltage follower FVF also includes a bias circuit module 33 and an output setting voltage VSET; both ends of the bias circuit module 33 and the output setting voltage VSET are electrically connected to the common source differential pair 31 and the ground GND, respectively; both ends of the bias circuit module 33 are electrically connected to the common source differential pair 31 and the power input terminal VIN, respectively.

[0042] By setting the bias circuit module 33 and the output setting voltage VSET, the accuracy and stability of the circuit can be effectively improved. Setting the bias circuit module 33 helps ensure that the circuit is in the conducting state, and setting the output setting voltage VSET helps ensure the final output voltage value. The coordinated setting of the two helps ensure the reliability of the voltage output in the circuit.

[0043] The common-source differential pair 31 consists of a first switch M11 and a second switch M15, used to compare the voltage difference between the bias voltage VBIAS and the output setting voltage VEST. Both the first switch M11 and the second switch M15 are MOSFETs. The sources of the first switch M11 and the second switch M15 are connected in parallel and then electrically connected to ground GND through the bias circuit module 33. The gates of the first switch M11 and the second switch M15 are electrically connected to ground GND through the bias circuit module 33, the output setting voltage VEST, and respectively. The drain of the first switch M11 is electrically connected to the compensation unit 10 and the power output stage 32. The drain of the second switch M15 is electrically connected to the compensation unit 10, the non-inverting gain stage 20, and the bias circuit module 33.

[0044] By configuring the common-source differential pair 31, when the voltage output node VOUT increases due to load changes, the output setting voltage VSET increases, and the gate voltage of the first switch M11 is greater than the gate voltage of the second switch M15. This increases the drain current of the first switch M11 and decreases the drain current of the second switch M15. Conversely, the drain current of the first switch M11 decreases and the drain current of the second switch M15 increases. This improves the circuit's anti-interference capability, enhances bias flexibility, and suppresses noise.

[0045] The power output stage 32 uses a core power transistor MP to achieve high-current regulated output in the circuit. The core power transistor MP is a MOSFET. The gate of the core power transistor MP is electrically connected to the non-inverting gain stage 20, and the drain of the core power transistor MP is electrically connected to the power input terminal VIN. The source of the core power transistor MP is electrically connected to the drain of the first switching transistor M11 and the compensation unit 10.

[0046] Preferably, the core power transistor MP and the first switching transistor M11 are both PMOS transistors; the second switching transistor M15 is an NMOS transistor.

[0047] By using the core power transistor MP as the core power transistor, a minimum channel length and multi-finger layout are adopted. The combination of "low on-resistance" and "high current drive capability" enables high-current regulated output, thereby ensuring the stability of the circuit's power output stage 32.

[0048] The bias circuit module 33 includes a first current source IBIAS11, a second current source IBIAS12, and a bias voltage VBIAS. The two ends of the first current source IBIAS11 are electrically connected to the source of the first switching transistor M11 and ground GND, respectively. One end of the second current source IBIAS12 is electrically connected to the drain of the second switching transistor M15, the compensation unit 10, and the non-inverting gain stage 20, respectively, and the other end of the second current source IBIAS12 is electrically connected to the power input terminal VIN. The two ends of the bias voltage VBIAS are electrically connected to the gate of the second switching transistor M15 and ground GND, respectively. The two ends of the output setting voltage VEST are electrically connected to the gate of the first switching transistor M11 and ground GND, respectively.

[0049] By coordinating the first current source IBIAS11, the second current source IBIAS12, and the bias voltage VBIAS, a precise quiescent operating point can be established, injecting quiescent current into the FVF loop in the circuit and ensuring the loop's operational stability. This also improves the power supply rejection ratio, isolates power supply noise, and guarantees the feedback accuracy of the flip-flop voltage follower (FVF). Furthermore, it enhances the circuit's response speed, enabling the FVF to maintain stable performance under various environmental conditions.

[0050] The compensation unit 10 uses a Miller capacitor CM. One end of the Miller capacitor CM is electrically connected to the drain of the second switching transistor M15, the non-inverting gain stage 20, and the second current source IBIAS12, respectively. The other end of the Miller capacitor CM is electrically connected to the source of the core power transistor MP and the drain of the first switching transistor M11, respectively. The connection points of the Miller capacitor CM, the source of the core power transistor MP, and the drain of the first switching transistor M11 are all connected to the voltage output node VOUT.

[0051] By using the Miller capacitor CM in compensation unit 10, the gate parasitic capacitance of the core power transistor MP can be amplified using the "Miller effect," creating a separation between the "dominant pole" and the "non-dominant pole," thereby achieving a phase margin >80°. This helps solve the stability problem of traditional OCL-LDOs without output capacitors. In particular, it resolves the contradiction between circuit stability and the chip area required for the circuit. The compensation strategy using a single Miller capacitor CM can greatly ensure loop stability without output capacitors. Furthermore, the Miller capacitor CM, as a frequency compensation unit, can also effectively improve the structural stability and operational safety of the circuit.

[0052] The non-inverting gain stage 20 includes a common-source amplifier M21, a current mirror 201, and a non-inverting bias current IBIAS2. The drain of the common-source amplifier M21 is electrically connected to the power input terminal VIN; the gate of the common-source amplifier M21 is located between the bias circuit module 33 and the common-source differential pair 31; the source of the common-source amplifier M21 is grounded to GND through the current mirror 201; the current mirror 201 is electrically connected to the power input terminal VIN through the non-inverting bias current IBIAS2.

[0053] Unlike traditional non-gain-enhanced flip-flop voltage followers (FVFs), which cannot solve the problem of poor power module regulation, this application adds a non-inverting gain stage 20. This adjusts the connection relationships of the components within the FVF, enabling the integration of the non-inverting gain stage 20 with the FVF and a low-dropout linear regulator (LDO). This creates a composite structure of "FVF + gain stage" with enhanced gain characteristics. By adding this gain stage, the loop gain of the traditional FVF is improved, and the increased open-loop gain offsets the channel length modulation effect of nanoscale devices.

[0054] The current mirror 201 is composed of a first transistor M22 and a second transistor M23. It serves as the tail current source for the gain stage, providing a stable current and preventing gain drift caused by current fluctuations. The gate of the first transistor M22 is electrically connected to both its drain and the gate of the second transistor M23. The sources of both transistors M22 and M23 are grounded to GND. The drain of the second transistor M23 is electrically connected to the non-inverting bias current IBIAS2 and the gate of the core power transistor MP of the power output stage 32 within the flip voltage follower FVF. The drain of the first transistor M22 is electrically connected to the source of the common-source amplifier M21. Preferably, the common-source amplifier M21 is a PMOS transistor. Both the first transistor M22 and the second transistor M23 are NMOS transistors.

[0055] By optimizing the components within the non-inverting gain stage 20, the gain bottleneck of the traditional flip-flop voltage follower (FVF) can be effectively overcome, thereby improving the stability and reliability of the circuit. Specifically, the common-source amplifier M21 provides high output impedance for the circuit. The output impedances of the common-source amplifier M21 and the first transistor M22 are superimposed to form a high-gain, wide-path circuit. Furthermore, key parameters of the core power transistor MP are optimized. By expanding the dynamic range of the gate voltage of the core power transistor MP, the gate voltage of the core power transistor MP is only slightly higher than ground (GND) (one saturation voltage of the second transistor M23). While ensuring a maximum load current of 100mA, the W / L ratio of the core power transistor MP is reduced, thereby effectively reducing the chip area. Here, W refers to the channel width of the core power transistor MP, and L refers to the channel length of the core power transistor MP.

[0056] Preferably, the first current source IBIAS11, the second current source IBIAS12, the bias voltage VBIAS, and the non-inverting bias current IBIAS2 constitute the bias circuit module 33.

[0057] By setting up various current and voltage sources, a stable bias current and voltage can be provided to the circuit. This ensures that each MOSFET can operate in the saturation region, stabilizing the circuit's DC operating point.

[0058] To address the contradiction between circuit stability and chip area occupied within the power module, a single Miller capacitor CM compensation strategy is adopted. This strategy abandons the traditional NMC multi-capacitor compensation and inserts only one Miller capacitor CM between the voltage output node VOUT and the drain of the newly added gain stage input terminal, namely the second switching transistor M15, to stabilize the loop using the "pole splitting" technique.

[0059] The key to the formula derivation in the compensation strategy for a single Miller capacitor CM includes: constructing a small-signal model after equivalence of the circuit in this application; obtaining the dominant pole p-3dB and non-dominant poles p2 and p3 based on the low-frequency loop gain formula using the second, third, and fourth formulas; and limiting the capacitance C of the Miller capacitor CM using the seventh formula. out The fifth formula ensures that the non-dominant poles are far from the gain-bandwidth product GMW, and the phase margin is >80°. The fifth formula is GBW = gm1 / Cm. The minimum load current, derived from the seventh formula, is 1mA-3mA, which is suitable for the leakage current characteristics of the 90nm process and requires no additional circuitry to compensate for light-load stability.

[0060] The small-signal model includes the first transconductance g m1 Second transconductance g m2 and the third transconductance g mp The power input terminal VIN passes through the first transconductor g in sequence. m1 Second transconductance gm2 Third transconductance g mp It is connected to the power output node VOUT. The small-signal model also includes three equivalent resistors and three equivalent capacitors. The three equivalent resistors are equivalent to a single resistor R. o1 Equivalent two resistors R o2 and equivalent three resistances R OUT Equivalent resistance R o1 Equivalent two resistors R o2 and equivalent three resistances R OUT One end is respectively set in the first transconductor g m1 Second transconductance g m2 and the third transconductance g mp The output terminal is equivalent to a resistor R. o1 Equivalent two resistors R o2 and equivalent three resistances R OUT The other end is grounded. The three equivalent capacitances are equivalent capacitance one Cp1, equivalent capacitance two Cp2, and equivalent capacitance three Cp2, respectively. out Equivalent capacitor Cp1, equivalent capacitor Cp2, and equivalent capacitor Cp3 out One end is located at the first transconductance g m1 Second transconductance g m2 and the third transconductance g mp The output terminal is equivalent to a single capacitor Cp1, a second capacitor Cp2, and a third capacitor Cp1. out The other end is grounded.

[0061] Additionally, the low-frequency loop gain A dc The calculation formula is:

[0062] .

[0063] The second formula is: Where Cm refers to the capacitance of the Miller capacitor CM, i.e., C out .

[0064] The third formula is: .

[0065] The fourth formula is: .

[0066] Loop gain A V(S) The calculation formula is:

[0067] .

[0068] The seventh formula is the capacitance value C of the Miller capacitor CM. out The formula for calculating the size. Specifically, the seventh formula is: .

[0069] The formula for calculating the output current IOUT is:

[0070] .

[0071] A power semiconductor chip, the chip including the aforementioned power semiconductor circuit, the circuit being integrated onto the chip.

[0072] In this invention, any power semiconductor chip may include the power semiconductor circuit structure described in this embodiment. In addition to the Miller capacitor CM and constant voltage source structure and assembly relationship provided in this embodiment, the power semiconductor chip also includes conventional components such as constant current source and MOS transistor. Since these are all prior art, they will not be described in detail here.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A power semiconductor circuit, comprising a chip having a channel therein, characterized in that, The circuit also includes: Flip voltage follower (FVF): Used as a voltage buffer to ensure regulated current output within the circuit; Compensation unit (10): Both ends are electrically connected to the flip voltage follower FVF to ensure loop stability without output capacitor; Non-inverting gain stage (20): Electrically connected to the power input terminal VIN, ground GND, and flip voltage follower FVF respectively, used to increase the open-loop gain to counteract the channel length modulation effect when the chip is working.

2. The power semiconductor circuit according to claim 1, characterized in that, The flip voltage follower FVF includes a common-source differential pair (31) and a power output stage (32); one end of the common-source differential pair (31) is electrically connected to the compensation unit (10), the non-inverting gain stage (20), and the power output stage (32), respectively; the power output stage (32) is electrically connected to the power input terminal VIN, the non-inverting gain stage (20), and the compensation unit (10), respectively; the other end of the common-source differential pair (31) is grounded.

3. A power semiconductor circuit according to claim 2, characterized in that, The flip voltage follower FVF also includes a bias circuit module (33) and an output setting voltage VSET; both ends of the bias circuit module (33) and the output setting voltage VSET are electrically connected to the common source differential pair (31) and the ground GND, respectively; both ends of the bias circuit module (33) are electrically connected to the common source differential pair (31) and the power input terminal VIN, respectively.

4. A power semiconductor circuit according to claim 3, characterized in that, The common-source differential pair (31) consists of a first switch M11 and a second switch M15, both of which are MOS transistors.

5. A power semiconductor circuit according to claim 4, characterized in that, The sources of the first switch M11 and the second switch M15 are connected in parallel and then electrically connected to ground GND through the bias circuit module (33); the gates of the first switch M11 and the second switch M15 are electrically connected to ground GND through the bias circuit module (33) and the output setting voltage VSET, respectively; the drain of the first switch M11 is electrically connected to the compensation unit (10) and the power output stage (32), respectively; the drain of the second switch M15 is electrically connected to the compensation unit (10), the non-inverting gain stage (20), and the bias circuit module (33), respectively.

6. A power semiconductor circuit according to claim 5, characterized in that, The power output stage (32) uses a core power transistor MP to achieve high current voltage regulation output in the circuit. The core power transistor MP is a MOS transistor. The gate of the core power transistor MP is electrically connected to the non-inverting gain stage (20), and the drain of the core power transistor MP is electrically connected to the power input terminal VIN. The source of the core power transistor MP is electrically connected to the drain of the first switching transistor M11 and the compensation unit (10).

7. A power semiconductor circuit according to claim 4, characterized in that, The bias circuit module (33) includes a first current source IBIAS11, a second current source IBIAS12 and a bias voltage VBIAS; the two ends of the first current source IBIAS11 are electrically connected to the source of the first switching transistor M11 and the ground GND respectively; one end of the second current source IBIAS12 is electrically connected to the drain of the second switching transistor M15, the compensation unit (10) and the non-inverting gain stage (20) respectively, and the other end of the second current source IBIAS12 is electrically connected to the power input terminal VIN. The two ends of the bias voltage VBIAS are electrically connected to the gate of the second switching transistor M15 and the ground line GND, respectively.

8. A power semiconductor circuit according to claim 7, characterized in that, The compensation unit (10) uses a Miller capacitor CM. One end of the Miller capacitor CM is electrically connected to the drain of the second switch transistor M15, the non-inverting gain stage (20), and the second current source IBIAS12, respectively. The other end of the Miller capacitor CM is electrically connected to the source of the core power transistor MP and the drain of the first switch transistor M11, respectively.

9. A power semiconductor circuit according to claim 8, characterized in that, The non-inverting gain stage (20) includes a common-source amplifier M21, a current mirror (201), and a non-inverting bias current IBIAS2; the drain of the common-source amplifier M21 is electrically connected to the power input terminal VIN; the gate of the common-source amplifier M21 is located between the bias circuit module (33) and the common-source differential pair (31); the source of the common-source amplifier M21 is grounded to GND through the current mirror (201); the current mirror (201) is electrically connected to the power input terminal VIN through the non-inverting bias current IBIAS2.

10. A power semiconductor circuit according to claim 9, characterized in that, The current mirror (201) is composed of a first transistor M22 and a second transistor M23. The gate of the first transistor M22 is electrically connected to the drain of the first transistor M22 and the gate of the second transistor M23, respectively. The sources of the first transistor M22 and the second transistor M23 are both grounded to GND. The drain of the second transistor M23 is electrically connected to the non-inverting bias current IBIAS2 and the flip voltage follower FVF, respectively. The drain of the first transistor M22 is electrically connected to the source of the common-source amplifier M21.

11. A power semiconductor chip, characterized in that, The chip includes a power semiconductor circuit according to any one of claims 1-10, the circuit being integrated on the chip.

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