A gallium oxide device with a graded gate dielectric structure and a method of fabricating the same

Abstract

This invention discloses a gallium oxide device with a gradient gate dielectric structure and its fabrication method, relating to semiconductor technology, and proposes a solution to address the performance limitations of short-channel devices. A gradient dielectric layer and a gradient gate layer are deposited on a gallium oxide epitaxial layer. The gradient dielectric layer is used to control the electric field distribution under the gate and the gate-channel coupling capability. The dielectric constant of the gradient dielectric layer changes in a piecewise gradient, increasing from the side near the source layer towards the drain layer. The gradient gate layer is used to control the potential distribution on the channel surface. The work function of the gradient gate layer changes in a piecewise gradient, decreasing from the side near the source layer towards the drain layer. Its advantages lie in achieving coordinated control of the channel potential distribution and the electric field distribution under the gate. It can weaken the modulation effect of the drain voltage on the channel barrier, reduce the channel length modulation effect and output conductance, and improve the current saturation characteristics of the device; it reduces the peak electric field at the gate-drain edge and weakens the electric field concentration phenomenon, making it particularly suitable for devices with short-channel dimensions.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more particularly to a gallium oxide device with a gradient gate dielectric structure and its fabrication method. Background Technology

[0002] Existing gallium oxide devices still face several prominent challenges as feature sizes shrink, particularly with short-channel designs. In traditional single-metal gate and single-dielectric gate structures, the channel potential distribution is easily affected by the drain bias, leading to significant electric field concentration at the gate-drain edge. This phenomenon not only increases local electric field stress, affecting the device's breakdown characteristics, but also enhances the drain's modulation effect on the channel, increasing output conductance and deteriorating saturation characteristics. Furthermore, the strong coupling between the gate and drain in traditional uniform gate structures easily generates large gate-drain parasitic capacitances. Larger gate-drain parasitic capacitances exacerbate the Miller effect, thus limiting performance parameters such as current gain, power gain, cutoff frequency, and maximum oscillation frequency. As device dimensions shrink further, these performance constraints become even more pronounced.

[0003] In this invention, short-channel refers to the effective channel length of a radio frequency (RF) device entering the sub-micron or even hundreds of nanometer scale. Specifically, short-channel gallium oxide (GaO) RF devices are those whose gate length, channel length, or the characteristic size of the effective electric field modulation region is less than 1 μm, and in some high-precision devices, it is below 500 nm, or even in the range of 100–300 nm. At this size scale, the device inevitably exhibits significant short-channel effects, electric field concentration effects, and parasitic capacitance enhancement, making it difficult for traditional structures to maintain stable operation while simultaneously achieving high-frequency performance and voltage withstand capability. Summary of the Invention

[0004] The purpose of this invention is to provide a gallium oxide device with a gradient gate dielectric structure and its fabrication method, so as to solve the problems existing in the prior art.

[0005] The gallium oxide device with a gradient gate dielectric structure described in this invention includes a gallium oxide epitaxial layer and a substrate stacked together; the gallium oxide epitaxial layer has a source layer deposited on the source contact region and a drain layer deposited on the drain contact region;

[0006] A gradient dielectric layer is deposited between the source layer and the drain layer on the upper surface of the gallium oxide epitaxial layer; a gradient gate layer is deposited on the gradient dielectric layer; the gradient dielectric layer and the gradient gate layer constitute the gradient gate dielectric structure. The gradient dielectric layer is used to regulate the electric field distribution under the gate and the gate-channel coupling capability; the dielectric constant of the gradient dielectric layer changes in a piecewise gradient, increasing from the side near the source layer to the drain layer. The gradient gate layer is used to regulate the potential distribution on the channel surface; the work function of the gradient gate layer changes in a piecewise gradient, decreasing from the side closer to the source layer to the drain layer.

[0007] The method for fabricating the gallium oxide device includes the following steps: S1. Epitaxial growth of gallium oxide epitaxial layer on substrate; S2. Patterned ion doping is performed on the upper surface of the gallium oxide epitaxial layer to form source contact region and drain contact region respectively; S3. Deposit metal on the source contact region to form an ohmic contact and form a source layer; deposit metal on the drain contact region to form an ohmic contact and form a drain layer; S4. Deposit dielectric material segment by segment on the channel region of the gallium oxide epitaxial layer to form a gradient dielectric layer; S5. Deposit metal material segment by segment on the gradient dielectric layer to form a gradient gate layer.

[0008] The gallium oxide device with a gradient gate dielectric structure and its fabrication method described in this invention have the advantage of achieving synergistic control of the channel potential distribution and the gate electric field distribution by introducing a gradient gate dielectric structure in the gate region. On the one hand, the gradient gate creates a difference in gate control between the source and drain sides, which can weaken the modulation effect of the drain voltage on the channel barrier, thereby reducing the channel length modulation effect and output conductance, and improving the current saturation characteristics of the device. On the other hand, the gradient dielectric can optimize the local electric field distribution on the drain side, reduce the electric field peak at the gate-drain edge, and weaken the electric field concentration phenomenon, thus improving the breakdown characteristics and operational reliability of the device. At the same time, the synergistic effect of the gradient gate and the gradient dielectric can also reduce the gate-drain parasitic capacitance, reduce the Miller effect, and improve the small-signal current gain and power gain of the device. While maintaining the normal conduction capability of the device, it achieves lower output conductance and smaller gate-drain parasitic capacitance, thereby improving the cutoff frequency and maximum oscillation frequency of the device, making it suitable for high-frequency and high-voltage electronic applications. Furthermore, the device structure of this invention is clear, the process method is well-defined, and it is compatible with existing gallium oxide device fabrication processes. It has good feasibility and application prospects, and is especially suitable for semiconductor devices with short channel dimensions. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the gallium oxide device described in this invention.

[0010] Figure 2 This is a schematic diagram of the gradient gate dielectric structure of Embodiment 1 in this invention.

[0011] Figure 3 This is a simulation curve of the transconductance of the gallium oxide device versus the gate-source voltage in Example 1 and the comparative example.

[0012] Figure 4 This is a simulation curve of the drain conductance of the gallium oxide device versus the source-drain voltage in Example 1 and the comparative example.

[0013] Figure 5 This is a simulation curve of the gate-drain parasitic capacitance of the gallium oxide device and the comparative example as a function of frequency in Embodiment 1.

[0014] Figure 6 This is a simulation curve of the gallium oxide device at the maximum transconductance of the comparative example, showing the small signal |h21|.

[0015] Figure 7 This is a simulation curve of the small-signal MSG / MAG at the maximum transconductance of the gallium oxide device in Example 1, compared with that of the comparative example.

[0016] Figure 8 This is a simulation curve of the electric field distribution at 0.05μm under the gate dielectric layer of the gallium oxide device and the comparative example at a drain-source voltage of 100V.

[0017] Figure 9 This is a schematic diagram of the gradient gate dielectric structure in Embodiment 2 of the present invention.

[0018] Figure label: 100-substrate; 200 - Gallium oxide epitaxial layer, 201 - Source contact region, 202 - Drain contact region; 301 - Source layer, 302 - Drain layer; 400 - Gradient dielectric layer, 401 - First dielectric, 402 - Second dielectric, 403 - Third dielectric; 500 - Gradient gate layer, 501 - First metal, 502 - Second metal, 503 - Third metal. Detailed Implementation

[0019] like Figure 1 As shown, the gallium oxide device with a gradient gate dielectric structure described in this invention includes a gallium oxide epitaxial layer 200 and a substrate 100 stacked together. The gallium oxide epitaxial layer 200 has a source layer 301 deposited on the source contact region 201 and a drain layer 302 deposited on the drain contact region 202.

[0020] A gradient dielectric layer 400 is deposited on the upper surface of the gallium oxide epitaxial layer 200 between the source layer 301 and the drain layer 302. A gradient gate layer 500 is deposited on the gradient dielectric layer 400. The gradient dielectric layer 400 and the gradient gate layer 500 constitute the gradient gate dielectric structure.

[0021] The gradient dielectric layer 400 is used to regulate the distribution of the electric field under the gate and the gate-channel coupling capability. The dielectric constant of the gradient dielectric layer 400 changes in a segmented gradient, increasing from the side near the source layer 301 towards the drain layer 302. High dielectric constant materials such as Al2O3, HfO2, SiO2, ZrO2, and Si3N4 can be selected. Since the dielectric constant of the gate dielectric determines the coupling capability of the gate to the channel potential, the distribution of materials with different dielectric constants in different regions of the channel will significantly affect the channel potential and electric field distribution. In this invention, a lower dielectric constant dielectric is used on the source side to appropriately reduce the source-side gate control strength and stabilize the carrier injection process; a higher dielectric constant dielectric is used on the drain side to enhance the gate's control capability over the drain-side channel potential, thereby weakening the modulation effect of the drain voltage on the channel barrier. Simultaneously, the high dielectric constant material can improve the distribution of the electric field under the gate, reducing and homogenizing the local electric field peak on the drain side, thereby improving the device's breakdown characteristics and operational reliability.

[0022] The thickness of the gradient dielectric layer 400 directly affects the gate's ability to control the channel potential and the device's reliability. When the dielectric layer is too thin, quantum tunneling current is easily generated under a higher gate bias, leading to an increase in gate leakage current; while when the dielectric layer is too thick, the gate oxide capacitance decreases, thereby weakening the gate's control over the channel and reducing the device's transconductance. Therefore, this invention controls the thickness of the gradient dielectric layer 400 within the range of 2 nm to 50 nm, preferably 5 nm to 20 nm, to achieve a balance between gate control capability, gate leakage, and device reliability.

[0023] The gradient gate layer 500 is used to regulate the channel surface potential distribution. The work function of the gradient gate layer 500 changes in a piecewise gradient, decreasing from the side closer to the source layer 301 towards the drain layer 302. This forms a stepped gate potential distribution in the channel direction. The high work function gate on the source side can improve the source-side channel barrier and enhance the gate's ability to regulate the carrier injection process; the low work function gate on the drain side causes the channel surface potential to form a gradual distribution along the channel direction, thereby suppressing the channel length modulation effect and reducing the output conductance. The aforementioned stepped potential distribution can improve the current saturation characteristics of the device, while weakening the gate-drain coupling and reducing the gate-drain parasitic capacitance, which is beneficial to improving the device performance.

[0024] The metal material can be a metal or a metal compound. The metal material can be Al, Ti, Ni, Mo, Pt, W, Au, or a combination thereof, and the metal compound can be TiN, TaN, WN, etc. The 500 nm thickness of the gradient gate layer affects the gate resistance and parasitic parameters of the device. When the gate metal is too thin, its resistance increases, leading to an increase in the gate series resistance, thereby reducing the maximum oscillation frequency of the device. When the gate metal is too thick, it may increase the metal step height and affect the photolithography lift-off process, while also increasing the gate-drain overlap area, thereby increasing the gate-drain parasitic capacitance. Therefore, this invention controls the 500 nm thickness within the range of 20 nm to 500 nm, preferably 100 nm to 300 nm, to achieve a balance between reducing gate resistance, ensuring process feasibility, and controlling parasitic capacitance.

[0025] The gallium oxide epitaxial layer 200 has a thickness of 100 nm to 2 μm, more preferably 200 nm to 500 nm. The doping concentration of the source contact region 201 and the drain contact region 202 is 10. 17 cm -3 Up to 10 20 cm -3 More preferably 10 18 cm -3 Up to 10 19 cm -3 The longitudinal depth is 10 nm to 200 nm, more preferably 20 nm to 100 nm.

[0026] The total gate length of the gradient gate dielectric structure is 0.1 μm to 2 μm. The gradient dielectric layer 400 and the gradient gate layer 500 have the same number of segments; preferably, each segment has the same length. In this invention, the gradient gate dielectric structure can be divided into N segments along the channel direction, where N is an integer greater than or equal to 2. When N is 2, the device performance is effectively improved while ensuring the simplest manufacturing process. When N is 3 or higher, the improvement in device performance is smoother and more closely resembles an ideal device.

[0027] Since the gradient gate dielectric structure can be implemented in various ways, the present invention provides, for example... Figure 2 and Figure 9 With the structure shown, those skilled in the art, guided by the two implementation methods, can achieve more segments without creative effort.

[0028] Example 1 like Figure 2As shown, in this embodiment, the gradient gate dielectric structure is segmented into two parts. The first metal 501 and the first dielectric 401 are close to the source layer 301, and the second metal 502 and the second dielectric 402 are close to the drain layer 302. The first dielectric 401 is made of Al2O3, the second dielectric 402 is made of HfO2, the first metal 501 is made of Ni, and the second metal 502 is made of Ti.

[0029] To compare simulation results and demonstrate the technical effects of the present invention, such as Figures 3 to 8 As shown in the table below, the materials selected for the comparative examples are as follows:

[0030] As can be seen from the comparison curves, compared with the traditional single-metal gate single-dielectric structure, the short-channel gallium oxide device with gradient gate dielectric structure proposed in this invention exhibits significant advantages in several key performance aspects. Specifically, from Figure 3 As can be seen, the structure of this invention exhibits a higher peak transconductance, indicating that the synergistic effect of the gradient metal gate and the gradient dielectric enhances the gate's ability to control channel carriers. From Figure 4 It is evident that the structure of this invention has a lower output conductance, indicating that it can effectively reduce the modulation effect of the drain voltage on the channel barrier, thereby suppressing the drain-induced barrier reduction effect and the channel length modulation effect, and improving the current saturation characteristics of the device. Figure 5 It can be seen that the gate-drain parasitic capacitance of the structure of the present invention is smaller, indicating that the structure can weaken gate-drain coupling and suppress the Miller effect. Figure 6 and Figure 7 It can be seen that due to the increased transconductance, decreased output conductance, and reduced gate-drain parasitic capacitance, the small-signal current gain and power gain of the device are both improved, thereby increasing the cutoff frequency f. T and maximum oscillation frequency f MAX He was promoted. Figure 8 It is evident that the structure of this invention can effectively improve the electric field distribution under the gate, reduce the local electric field peak on the drain side, and weaken the electric field concentration phenomenon, thereby improving the breakdown characteristics and operational stability of the device. In summary, this invention, through the synergistic design of a gradient metal gate and a gradient dielectric, achieves comprehensive optimization of the channel potential distribution, electric field distribution, and parasitic parameters, enabling the device to simultaneously achieve higher transconductance, lower output conductance, smaller gate-drain parasitic capacitance, and superior performance under short-channel conditions.

[0031] Example 2 Based on Embodiment 1, this embodiment further extends the dual-gradient metal gate structure to a multi-gradient metal gate structure, and correspondingly extends the dual-gradient dielectric structure to a multi-gradient dielectric structure, in order to obtain a smoother channel potential distribution and electric field distribution, thereby further improving the short-channel effect and performance of the device.

[0032] Specifically, the gradient gate dielectric structure is segmented into three parts. The first metal 501 and the first dielectric 401 are located near the source layer 301, while the third metal 503 and the third dielectric 403 are located near the drain layer 302. The second metal 502 is located between the first metal 501 and the third metal 503; the second dielectric 402 is located between the first dielectric 401 and the third dielectric 403. The first dielectric 401 is SiO2, the second dielectric 402 is Al2O3, and the third dielectric 403 is HfO2. The first metal 501 is Pt, the second metal 502 is Ni, and the third metal 503 is Ti.

[0033] The present invention also provides a method for fabricating the gallium oxide device, comprising the following steps: S1. The substrate 100 can be silicon carbide, and an unintentionally doped gallium oxide epitaxial layer 200 is epitaxially grown on the substrate 100. The gallium oxide epitaxial layer 200 is subsequently used to form the channel region, the source contact region 201, and the drain contact region 202. The formation and location of the channel region are common knowledge to those skilled in the art and will not be described in detail in this invention.

[0034] S2. Based on photolithography, corresponding contact regions are defined in the predetermined source and drain regions on the upper surface of the gallium oxide epitaxial layer 200, and then ion doping is performed to form the source contact region 201 and the drain contact region 202, respectively.

[0035] S3. Metal is deposited on the source contact region 201 to form an ohmic contact, thereby forming the source layer 301, and metal is deposited on the drain contact region 202 to form an ohmic contact, thereby forming the drain layer 302. To improve the contact characteristics between the metal and the semiconductor, further annealing may be performed.

[0036] S4. If the number of segments is set to two: a first dielectric material is deposited on the surface of the channel region between the source layer 301 and the drain layer 302, and the pattern of the first dielectric 401 is defined by photolithography and etching processes, so that the first dielectric material is retained in the predetermined gate under region on the source side to form the first dielectric 401. Then, a second dielectric material is deposited on the surface of the channel region, and the pattern of the second dielectric 402 is defined by photolithography and etching processes, so that the second dielectric material is retained in the predetermined gate under region on the drain side to form the second dielectric 402.

[0037] If the number of segments is set to three or more, based on the principle of two segments, the deposition, photolithography, and etching of the corresponding dielectric material can be continued to obtain the corresponding segmented dielectric.

[0038] S5. If the number of segments is set to two: deposit a first metal 501 on the first medium 401 by magnetron sputtering or electron beam evaporation, and then deposit a second metal 502 on the second medium 402 by magnetron sputtering or electron beam evaporation.

[0039] If the number of segments is set to three or more, based on the principle of two segments, the corresponding segmented metal can be obtained by continuing to perform magnetron sputtering or electron beam evaporation deposition of the corresponding metal.

[0040] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this invention.

Claims

1. A gallium oxide device with a gradient gate dielectric structure, comprising a gallium oxide epitaxial layer (200) and a substrate (100) stacked thereon; wherein the gallium oxide epitaxial layer (200) has a source layer (301) deposited on a source contact region (201) and a drain layer (302) deposited on a drain contact region (202). Its features are, A gradient dielectric layer (400) is deposited on the upper surface of the gallium oxide epitaxial layer (200) between the source layer (301) and the drain layer (302); a gradient gate layer (500) is deposited on the gradient dielectric layer (400); the gradient dielectric layer (400) and the gradient gate layer (500) constitute the gradient gate dielectric structure; The gradient dielectric layer (400) is used to regulate the electric field distribution under the gate and the gate-channel coupling capability; the dielectric constant of the gradient dielectric layer (400) changes in a piecewise gradient manner, increasing from the side near the source layer (301) to the drain layer (302); The gradient gate layer (500) is used to regulate the potential distribution on the channel surface; the work function of the gradient gate layer (500) changes in a piecewise gradient, decreasing from the side closer to the source layer (301) to the drain layer (302).

2. The gallium oxide device with a gradient gate dielectric structure according to claim 1, characterized in that, The total gate length of the gradient gate dielectric structure is 0.1 μm to 2 μm.

3. A gallium oxide device with a gradient gate dielectric structure according to claim 2, characterized in that, The gradient dielectric layer (400) and the gradient gate layer (500) have the same number of segments.

4. A gallium oxide device with a gradient gate dielectric structure according to claim 3, characterized in that, Each segment of the gradient dielectric layer (400) and the gradient gate layer (500) has the same length.

5. A gallium oxide device with a gradient gate dielectric structure according to claim 4, characterized in that... The gradient dielectric layer (400) and the gradient gate layer (500) are divided into two or three segments.

6. A gallium oxide device with a gradient gate dielectric structure according to claim 1, characterized in that, The thickness of the gradient dielectric layer (400) is 2nm to 50nm.

7. A gallium oxide device with a gradient gate dielectric structure according to claim 6, characterized in that, The thickness of the gradient dielectric layer (400) is 5nm to 20nm.

8. A gallium oxide device with a gradient gate dielectric structure according to claim 1, characterized in that, The thickness of the gradient gate layer (500) is 20nm to 500nm.

9. A gallium oxide device with a gradient gate dielectric structure according to claim 8, characterized in that, The thickness of the gradient gate layer (500) is 100nm to 300nm.

10. The method for fabricating a gallium oxide device according to any one of claims 1-9, characterized in that, Includes the following steps: S1. A gallium oxide epitaxial layer (200) is epitaxially grown on a substrate (100). S2. Patterned ion doping is performed on the upper surface of the gallium oxide epitaxial layer (200) to form source contact region (201) and drain contact region (202), respectively. S3. Deposit metal on the source contact region (201) to form an ohmic contact to form a source layer (301); deposit metal on the drain contact region (202) to form an ohmic contact to form a drain layer (302). S4. Dielectric material is deposited segment by segment on the channel region of the gallium oxide epitaxial layer (200) to form a gradient dielectric layer (400). S5. Deposit metal material segment by segment on the gradient dielectric layer (400) to form a gradient gate layer (500).

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