Instruction prediction method and device, electronic equipment, storage medium and product

Abstract

The invention discloses an instruction prediction method and device, electronic equipment, a storage medium and a product. Relates to the technical field of computers. The method comprises the steps that whether the type of a current instruction is an alias type or not is determined, wherein the alias type refers to that a first address, mapped to a BTB based on a first index mode, of the current instruction conflicts with addresses of other instructions; if the current instruction is the instruction of the alias type, it is determined that the current instruction is remapped to a second address in the BTB based on a second index mode, and the second address is different from the first address; and obtaining historical execution information from the second address to obtain a prediction result of the current instruction. According to the scheme, for the instruction with the alias problem, different index modes are adopted to remap the instruction to the new address, the conflict between the instruction and branch addresses of other instructions can be effectively avoided, when the current instruction is identified as the instruction of the alias type, the correct historical execution information can be obtained from the corresponding remapped address, and the operation efficiency is improved. Therefore, the reliability of branch prediction is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer technology, and in particular, to an instruction prediction method and device, electronic equipment, storage medium and product. BACKGROUND

[0002] Branch instructions are a special type of instruction in computer instruction sets, which can be used to change the execution flow of a program, making it jump to different code segments according to specific conditions, thus implementing control structures such as conditional judgment, loops and function calls. Branch target buffer (BTB, or Branch Target Cache, BTC) is a hardware structure used to store the target addresses of branch instructions, which can reduce branch prediction delay and improve pipeline efficiency by recording historical branch information. By recording the addresses of successfully executed branch instructions and branch target addresses in the BTB, the address of the current instruction is compared with the entries, so that it can be determined as early as possible whether the branch of the current instruction can be successful and the target address can be obtained as early as possible. This process is called dynamic branch prediction.

[0003] In high-performance processors, the BTB is a small, high-speed memory similar to a cache. Its working principle is: according to the address (PC) of the current instruction, the historical information (such as whether to jump, target address, etc.) of the past execution of the branch is quickly found and provided. The first step of this search process, which is also crucial, is indexing. Indexing determines which part of the PC information is used to locate a row (or a "set") in the predictor storage array. The goal of designing an indexing scheme is to have different PC addresses as evenly distributed as possible throughout the storage array, in order to minimize conflicts and improve the utilization of storage space.

[0004] The existing indexing scheme currently has the problem of aliasing. For example, in a common programming scenario: inside a loop body, or within a large function, the PC addresses of multiple branch instructions often only differ in the low bits, while the high bits are very close. If two different branch PCs (PC_A and PC_B) happen to be exactly the same in the bit positions used as indexes, they will be mapped to the same entry in the BTB, which means they cannot coexist and will thrash each other, causing the predictor to repeatedly fail on these two branches. This problem is particularly serious in modern software with highly regular program address space layouts.

[0005] In some scenarios, a hash function is introduced in the index scheme, and the core idea is information blending, that is, the information in different parts of the PC address is mixed together to generate a "pseudo-random" index. Based on this, the address locality can be broken: for example, two branches PC_A and PC_B, even if their low part (such as PC[b:a]) is the same, but their high part (such as PC[d:c]) is different with a high probability, after the hash operation, the two branches that would have conflicted are mapped to different positions in the BTB, and the aliasing problem can be effectively alleviated. However, this way may also introduce new conflicts: two PC addresses that do not conflict, after the hash operation, their results may become the same, which is called hash collision.

[0006] In summary, how to effectively avoid the address conflict of the instruction and solve the aliasing problem of branch prediction is a problem to be solved. SUMMARY

[0007] The present application provides an instruction prediction method and device, electronic equipment, storage medium and product, to effectively avoid the conflict of branch address and improve the reliability of branch prediction.

[0008] In a first aspect, the embodiments of the present application provide an instruction prediction method, comprising: determining the type of the current instruction, wherein the type is an alias type or a non-alias type, and the alias type means that the first address in the branch target buffer to which the current instruction is mapped based on a first index mode conflicts with the addresses corresponding to other instructions; In the case where the type of the current instruction is the alias type, determining that the current instruction is remapped to a second address in the branch target buffer based on a second index mode, and the second address is different from the first address; obtaining the historical execution information of the current instruction from the second address to obtain the prediction result of the current instruction.

[0009] In a second aspect, the embodiments of the present application also provide an instruction prediction device, comprising: A determination module is configured to determine the type of the current instruction, wherein the type is an alias type or a non-alias type, and the alias type means that the first address in the branch target buffer to which the current instruction is mapped based on a first index mode conflicts with the addresses corresponding to other instructions; A remapping module is configured to, in the case where the type of the current instruction is the alias type, determine that the current instruction is remapped to a second address in the branch target buffer based on a second index mode, and the second address is different from the first address; The prediction module is configured to obtain historical execution information of the current instruction from the second address, and obtain a prediction result of the current instruction.

[0010] In a third aspect, an electronic device is provided, including: one or more processors; a storage device configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the instruction prediction method according to the first aspect.

[0011] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the instruction prediction method according to the first aspect is implemented.

[0012] In a fifth aspect, a computer program product is provided, which includes a computer program and / or instructions. When the computer program and / or instructions are executed by a processor, the instruction prediction method according to any of the above embodiments is implemented.

[0013] The embodiments of the present application provide an instruction prediction method, device, electronic device, storage medium and product. The instruction prediction method includes: determining a type of a current instruction, wherein the type is an alias type or a non-alias type, and the alias type means that a first address in a branch target buffer to which the current instruction is mapped based on a first index mode conflicts with an address corresponding to another instruction; in a case where the type of the current instruction is the alias type, determining that the current instruction is remapped to a second address in the branch target buffer based on a second index mode, and the second address is different from the first address; and obtaining historical execution information of the current instruction from the second address to obtain a prediction result of the current instruction. The above technical solution remaps the instruction with the alias problem to a new address by using different index modes, which can effectively avoid the conflict of the branch address of the instruction with other instructions. When the current instruction is identified as an alias type instruction, the correct historical execution information can be obtained from the corresponding remapped address, thereby improving the reliability of branch prediction. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and other features, aspects, and advantages of the present disclosure will become more apparent with reference to the following detailed description taken in conjunction with the accompanying drawings. Throughout the drawings, like reference numerals are used to represent like elements. It should be understood that the drawings are schematic and elements are not necessarily to scale.

[0015] Figure 1 A flowchart of an instruction prediction method provided by the embodiments of the present application; Figure 2 An implementation schematic diagram of an instruction prediction mechanism provided for an embodiment; Figure 3 An implementation schematic diagram of an alias marking process provided for an embodiment; Figure 4 A structural schematic diagram of an instruction prediction apparatus provided for an embodiment of the present application; Figure 5 A structural schematic diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0016] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0017] Before the example embodiments are discussed in more detail, it should be mentioned that some of the example embodiments are described as processes or methods depicted as flow charts. While the steps of the processes are depicted as sequential processes, many of the steps can be performed in parallel, concurrently or at the same time. In addition, the order of the steps can be re-arranged. The processes can be terminated when their operations are completed, but can also have additional steps not included in the figure. The processes can correspond to methods, functions, routines, subroutines, subprograms, etc.

[0018] It should be noted that the terms "first", "second", etc. mentioned in the embodiments of the present application are only used to distinguish different apparatuses, modules, units or other objects, and do not limit the functions performed by these apparatuses, modules, units or other objects or the mutual dependency therebetween.

[0019] In addition, the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0020] In the technical solutions of the present application, the acquisition, storage, use, processing, etc. of data all comply with the relevant provisions of national laws and regulations.

[0021] It should be noted that, in the embodiments of the present application, some industry existing schemes of software, components, models, etc. can be mentioned, which should be considered as exemplary, and the purpose is only to illustrate the feasibility of the implementation of the technical solutions of the present application, but does not mean that the applicant has or will necessarily use the relevant content of the scheme.

[0022] The existing index mode mainly includes the following two kinds: Scheme one: direct-mapped indexing (Direct-Mapped Indexing): Index generation: directly take a contiguous low bit field (e.g. PC[11:5], assuming the BTB has 128 entries) from the PC address as the index.

[0023] Lookup process: this index value directly points to a unique entry in the BTB array.

[0024] Tag comparison: take the tag stored in this entry (usually the higher bits of the PC address), and compare it with the corresponding higher bits of the current PC. If they match, it is a hit.

[0025] The biggest problem of this scheme is systematic aliasing.

[0026] Scheme 2: introduce a hash function, e.g. XOR hash. Choose two or more non-overlapping fields from the PC address, usually a low field and a high field.

[0027] Index generation: XOR the two fields bit by bit, and use the result as the final BTB index.

[0028] This scheme can break address locality: e.g. two branch PC_A and PC_B, even if their low parts (e.g. PC[b:a]) are the same, their high parts (e.g. PC[d:c]) are likely to be different. After XOR, PC_A[d:c] ^ PC_A[b:a] is likely to be different from PC_B[d:c] ^ PC_B[b:a].

[0029] But this scheme has a limitation: static nature. It has a fixed mapping: the hash function is determined at the hardware design stage (i.e. which bits of the PC are XORed). Once the chip is manufactured, this mapping never changes; moreover, it can introduce new conflicts: although hash resolves many "natural" conflicts, it itself can introduce new conflicts. Two PC addresses that are not originally conflicting, after XOR, their results can become the same, which is called hash collision; moreover, the system has no way to know whether its current hash function is performing well for the running program. If a certain program or code segment happens to have an address distribution that is not suitable for the hash function, resulting in a large number of new hash collisions, the system is powerless, and since there is no feedback mechanism, it cannot be adjusted.

[0030] To this end, the embodiment of the present application provides an instruction prediction method. For instructions without aliasing problems, an index mode can be used for mapping, and for instructions with identified aliasing problems, another index mode can be used for remapping the instructions to solve the conflicts between the instructions and other addresses.

[0031] Figure 1 A flowchart of an instruction prediction method provided by the embodiment of the present application can be applicable to branch prediction. Specifically, the instruction prediction method can be executed by an instruction prediction device, which can be implemented in software and / or hardware and integrated in an electronic device. The electronic device includes but is not limited to a computer, a smart phone, a host computer or a server, and the like.

[0032] As shown in the method, the method specifically includes the following steps: Figure 1 S110, determining the type of a current instruction, wherein the type is an alias type or a non-alias type, and the alias type means that a first address of the current instruction mapped to a branch target buffer based on a first index mode conflicts with addresses corresponding to other instructions.

[0033] In the embodiment, the BTB is a core storage component of branch prediction, which can be physically divided into a plurality of storage units (Bank) and channels (Way). The main function is to provide a prediction result in the prediction stage according to the address (PC) of the input instruction. The prediction result can be the historical execution information of the corresponding instruction, such as whether to jump and the target address of the jump, and the like. The current instruction and the instruction tracked in the historical execution process of the embodiment of the present application are branch instructions.

[0034] In the embodiment, the BTB supports at least two index modes. The first index mode can be understood as a default or conventional mode, for example, using a specific bit of the PC address to directly index, and the like. The second index mode can be understood as a non-default or unconventional mode for remapping: for example, using a specific bit of the PC address to generate a new index after a fixed mathematical operation (such as XOR), and the like. When branch prediction is performed on the current instruction, the specific index mode to be used can be determined according to the type of the current instruction.

[0035] For example, an instruction is of an alias type, which can be understood as that the instruction has an aliasing problem when mapped to the BTB using the default index mode, that is, it will conflict with the addresses corresponding to other instructions.

[0036] ​In the branch prediction process, for the current instruction taken out by the instruction fetch block, firstly, it is judged whether it is an alias type or a non-alias type, that is, whether it is an instruction with alias problem. It can be judged according to the historical execution process of the current instruction. If the instruction with the same address as the current instruction has one or more address conflicts with other instructions in the historical execution process, the instruction with the address can be marked as an alias type. By comparing whether the address of the current instruction is consistent with the address, it can be judged whether the current instruction is an alias type instruction. If so, the prediction result can be obtained from the correct address corresponding to the second index mode, otherwise, the prediction result can be obtained from the address corresponding to the first index mode.

[0037] S120, in the case where the type of the current instruction is an alias type, determining that the current instruction is remapped to a second address in the branch target buffer based on a second index mode, the second address being different from the first address; Exemplarily, in the historical execution process, the correct execution result obtained according to the actually executed instruction, such as whether the branch of the instruction actually jumps (Taken / Not-Taken), and if it jumps, the correct jump target address (Actual Target PC), etc., can all be recorded as historical execution information. For the instruction identified as an alias type, if it is mapped to the first address in the BTB by using the first index mode, it will conflict with the address corresponding to other instructions. The second index mode can be used to remap it to the BTB to obtain a new address (i.e. the second address). On this basis, when the branch prediction of the current instruction is performed, if it is judged that the current instruction is an alias type instruction, the second address corresponding to the second index mode can be determined, and the correct prediction result can be obtained accordingly.

[0038] S130, obtaining the historical execution information of the current instruction from the second address to obtain the prediction result of the current instruction.

[0039] Exemplarily, if it is judged that the current instruction is an alias type instruction, the second address corresponding to the second index mode is determined, and the historical execution information thereof is read from the second address as the prediction result of the current instruction.

[0040] It can be understood that, in the case that the type of the current instruction is a non-alias type, the current instruction is determined to be remapped to a first address in the branch target buffer based on a first index mode, and the history execution information read from the first address is used as the prediction result of the current instruction. On this basis, for instructions with aliasing problems, different index modes can be used to remap them to new addresses, so that when the current instruction is identified as an alias type instruction, the correct history execution information can be obtained from the corresponding remapped address, effectively avoiding the conflict of the branch address of the instruction with other instructions, thereby improving the reliability of branch prediction.

[0041] In an embodiment, determining the type of the current instruction comprises: determining the type of the current instruction by querying the alias marker; wherein the alias marker is used to identify and mark the type of any instruction according to the remapping of the instruction in the history execution process.

[0042] The alias marker can be understood as a logic for real-time address conflict detection of instructions, which can quickly analyze whether the current instruction has an aliasing problem, thereby guiding the BTB to determine the correct index after remapping.

[0043] For example, if an instruction has address conflict with other instructions one or more times in the history execution process, the instruction can be marked as an alias type by the alias marker, and remapped to a second address of the BTB. On this basis, for the current instruction, the type can be quickly determined by querying the alias marker, thereby improving the efficiency and reliability of prediction.

[0044] In an embodiment, the alias marker is used to mark the following entries: The tag is used to record the second address in the branch target buffer to which the alias type instruction is remapped based on the second index mode; and the valid bit is used to indicate whether the remapping corresponding to the alias type instruction is valid. Determining the type of the current instruction by querying the alias marker comprises: in the case that the value of the valid bit corresponding to the current instruction indicates that the corresponding remapping is valid, determining that the type of the current instruction is an alias type.

[0045] For example, the entries marked in the alias marker include a tag and a valid bit, the tag can be used to record the branch address that causes aliasing (i.e. the second address), and the valid bit is used to indicate whether the content in the second address is valid. In this case, the addresses marked by the alias marker can be considered as prediction addresses that have aliasing, and remapping can be used to generate the index of the table entry.

[0046] When a fetch block fetches a current instruction to start prediction, first, the alias marker is inquired. If the current instruction is marked and the content in the second address corresponding to the current instruction is valid, it is determined that the type of the current instruction is an alias type, and the historical execution information needs to be obtained from the second address. On this basis, the correct prediction result can be quickly obtained, and the efficiency of instruction prediction is improved.

[0047] In an embodiment, the method further comprises: S100, for any instruction, recording the number of times that the first address of the instruction conflicts with the addresses corresponding to other instructions in the execution process by a counter; S102, in the case of saturation of the counter, marking the instruction as an alias type by an alias marker.

[0048] Illustratively, for any instruction, the number of times that the first address of the instruction conflicts with the addresses corresponding to other instructions in the historical execution process is recorded by a counter. Each time the instruction conflicts with the addresses corresponding to other instructions, the number of times of the instruction conflict is increased by 1. When the counter accumulates to saturation, for example, the number of times that the first address of the instruction conflicts with the addresses corresponding to other instructions reaches a set threshold, the instruction is marked as an alias type by an alias marker. It can be understood that for any instruction, long-term behavior tracking of the historical execution process can be performed, and the purpose is to identify long-term or stubborn alias problems. The number of times that a instruction is replaced by a table item (i.e., conflicts) in the historical execution process can be recorded by a counter; when the counter accumulates to saturation, it is determined that the instruction is a long-term victim of alias problems, and the corresponding remapping flag bit is set to valid. At this time, an update request can be initiated to the alias marker, and the second address of the remapping of the instruction is updated into the alias marker.

[0049] On this basis, by using the counter or the set threshold, the instruction that has multiple alias problems in the historical execution process can be marked as an alias type, and the misjudgment of the instruction that is occasionally remapped can be avoided, and the accuracy and reliability of identifying the instruction of the alias type are improved.

[0050] In an embodiment, marking the instruction as an alias type by an alias marker comprises: updating the tag corresponding to the instruction in the alias marker to the second address to which the instruction is remapped to the branch target buffer, and updating the valid bit corresponding to the instruction in the alias marker to valid.

[0051] For example, the process of marking the instruction as an alias type by the alias marker includes writing the second address obtained by remapping the instruction into the tag in the alias marker corresponding to the instruction, and updating the valid bit in the alias marker corresponding to the instruction as valid. On this basis, the addresses marked by the alias marker can be considered as prediction addresses with aliasing, and valid historical execution information can be recorded for these addresses to improve the efficiency of instruction prediction.

[0052] In an embodiment, the number of times of address conflict between the first address of the instruction in the execution process and the addresses corresponding to other instructions is recorded by a counter, including: In the process of executing the instruction each time, the actual execution result of the instruction is compared with the predicted execution result; If the actual execution result is inconsistent with the predicted execution result, the actual execution result is taken as the historical execution information of the instruction, and is written into the branch target buffer corresponding to the first address of the instruction mapped based on the first index mode; If the first address does not hit the branch target buffer, and there is no invalid way in the branch target buffer to replace, the instruction is remapped to the second address in the branch target buffer based on the second index mode, the historical execution information of the instruction is written into the position corresponding to the second address of the instruction remapped in the branch target buffer, and the number of times of address conflict between the first address of the instruction in the execution process and the addresses corresponding to other instructions is increased by 1.

[0053] For example, in the historical execution process, after executing an instruction, the actual result of the instruction is compared with the predicted result. If the two are consistent, the address of the instruction does not need to be updated. If the two are inconsistent, the following process is started: The update information containing the correct execution result is sent to the update cache unit, which can write the information into the corresponding position in the BTB; The update cache unit sends a read request to the BTB, and the BTB feeds back the read information to the update cache unit. If the first address of the instruction to be updated based on the first index mode does not hit the branch target buffer, and at this time there is no invalid way in the branch target buffer to replace, only one valid way can be replaced, which can be considered as an aliasing problem. A branch target buffer is constantly being preempted. In this case, the number of times of address conflict can be increased by 1 by the counter. When the number of times of address conflict is sufficient, the remapping mechanism can be used to update the information into the renaming marker using the second index mode. If the first address of the instruction to be updated hits the branch target buffer, and there is no need to replace the valid way, there is no aliasing problem, and the instruction can be updated to the first address directly.

[0054] Figure 2 An implementation diagram of an instruction prediction mechanism provided by an embodiment is shown in FIG. 1. When predicting a current instruction, it can be determined whether the current instruction is an alias type of instruction by querying the alias marker, based on which an index mode is determined. For example, if the current instruction is not an alias type of instruction, index 0 generation logic (i.e., a first index mode) is used to map to a first address, and if the current instruction is an alias type of instruction, index 1 generation logic (i.e., a second index mode) is used to map to a second address. The correct prediction result is obtained in the corresponding address in the BTB according to the finally determined index. Figure 2

[0055] Figure 3 An implementation diagram of an alias marking process provided by an embodiment is shown in FIG. 2. The branch execution unit is a functional component in the processor pipeline, which is configured to actually execute a branch instruction and obtain the final correct execution result of the branch instruction, including whether the branch actually jumps and the correct jump target address if the branch jumps. The unit is the benchmark of the correctness of the entire prediction system, and the actual result output by the unit is used to verify whether the previous prediction is accurate, and to drive the subsequent update process when the prediction is incorrect. Figure 3

[0056] The branch target buffer storage structure (i.e., BTB) is the core storage component of branch prediction, which can be physically divided into multiple Banks and Ways. The main function of the BTB is to provide a prediction result quickly according to the input instruction address (PC) in the prediction stage. The BTB supports at least two index modes, and the specific index mode used in the prediction is determined by the control signal from the alias marker.

[0057] The update cache unit is a first-in first-out (FIFO) buffer queue. When the branch execution unit detects a prediction error, the related information of the current error prediction (such as the PC of the branch instruction and the correct execution result) can be packaged into an update request and stored in the update cache unit. The function of the update cache unit is to decouple, allowing the branch execution unit to continue to execute subsequent instructions after sending the update request, and the update operation is written into the branch target buffer storage structure at a suitable time later, avoiding the blocking of the update operation on the critical path of the processor.

[0058] ​​The alias record unit is a special memory for long-term behavior tracking of branch instructions. Its internal structure is content addressable, and each entry contains at least: the label of the branch, a saturation counter, and a remapping flag bit, which identifies long-term or persistent alias problems. The counter records the number of times a branch instruction has replaced the table entry in its history. When the counter accumulates to saturation, the unit determines that this branch is a long-term victim of alias problems, and sets the corresponding remapping flag bit to active, and can initiate an update request to the alias marker to update the instruction address to the alias marker.

[0059] The alias marker is a logic for real-time detection of the current instruction stream. It can quickly analyze whether alias problems occur in the current instruction block, thereby guiding the branch target buffer to generate an index.

[0060] The above components work together to upgrade the traditional static and passive alias processing method to a dynamic, active, and intelligent system with learning ability. Specifically, after the branch execution unit executes a branch instruction, it compares the actual result with the predicted result. If the prediction is correct, the process ends, or only a small state update is performed. If the prediction is incorrect, the branch execution unit can send update information containing the correct result to the update cache unit, which will be responsible for writing this information to the corresponding position of the branch target buffer storage structure in the future. The update cache unit sends a read request to the branch target buffer, and the branch target buffer feeds back the read information to the update cache unit. If the instruction address updated by the request does not hit the branch target buffer, and there is no invalid path in the branch target buffer to replace, only one valid path can be replaced, which means that an alias problem has occurred. A branch target buffer is constantly being preempted, and the information is sent to the alias record unit for recording. The unit has a counter that records the number of times the event occurs. When the number of occurrences is too large, it is considered that the remapping mechanism can be used, and the information is updated to the renaming marker.

[0061] It should be noted that the static hashing scheme in the existing indexing scheme has its hash function fixed in the hardware design. It cannot detect and adapt to hash collisions caused by specific program behaviors at runtime. Since there is no feedback mechanism, for a program that does not perform well, it will only continue to use the wrong indexing strategy, resulting in a performance bottleneck. The method in this application, through the introduction of an alias record unit, establishes a feedback and learning mechanism. Specifically, when the update cache unit attempts to update a missed branch and finds that the target set is full and a valid entry must be replaced, this "replacement event" is itself regarded by this invention as a potential alias conflict signal. This signal is sent to the alias record unit, whose internal counter accumulates this event, which is equivalent to identifying that this branch address has been replaced again due to resource constraints. When the counter is saturated, the system no longer considers this replacement to be an accidental event, but makes a data-supported inference: the branch address has fallen into a continuous "preemption-eviction" vicious cycle caused by index conflicts. The branch is in a continuous, high-frequency conflict environment at its regular index position, and continuing to leave it in this position will almost certainly result in continued performance loss. Based on this inference, the system makes a final decision by setting the valid position and updating the alias marker: to permanently switch the branch to the remapping index mode. On this basis, an upgrade from "static blind" to "dynamic intelligent" indexing strategy is achieved, fundamentally solving the adaptability defects of static hashing.

[0062] Figure 4 This is a schematic diagram of the structure of an instruction prediction device provided in an embodiment of this application. Figure 4 As shown, the instruction prediction device provided in this embodiment includes: The determining module 210 is used to determine the type of the current instruction, wherein the type is an alias type or a non-alias type, and the alias type refers to the current instruction's first address mapped to the branch target buffer based on the first index pattern conflicting with the address corresponding to other instructions; Remapping module 220 is used to determine, when the type of the current instruction is an alias type, that the current instruction is remapped to a second address in the branch target buffer based on a second index mode, wherein the second address is different from the first address; The prediction module 230 is used to obtain the historical execution information of the current instruction from the second address and obtain the prediction result of the current instruction.

[0063] This device effectively avoids conflicts between the branch addresses of instructions with aliasing issues by remapping them to new addresses using different indexing patterns. When the current instruction is identified as an aliasing instruction, the correct historical execution information can be obtained from the corresponding remapped address, thereby improving the reliability of branch prediction.

[0064] Based on any of the above embodiments, the determining module 210 is specifically used to: determine the type of the current instruction by querying the alias marker; wherein, the alias marker is used to identify and mark the type of the instruction for any instruction based on the remapping situation of the instruction during historical execution.

[0065] Based on any of the above embodiments, the alias tagger is used to tag the following entries: A tag is used to record the instruction of the alias type being remapped to a second address in the branch target buffer based on a second index pattern; The valid bit is used to indicate whether the remapping corresponding to the instruction is valid; The step of determining the type of the current instruction by querying the alias marker includes: If the value of the valid bit corresponding to the current instruction indicates that the corresponding remapping is valid, the type of the current instruction is determined to be an alias type.

[0066] Based on any of the above embodiments, the device further includes: a recording module, used to record, for any instruction, the number of times the first address of the instruction conflicts with the address corresponding to other instructions during the execution process using a counter; and an identification module, used to mark the instruction as an alias type using an alias marker when the counter accumulates to saturation.

[0067] Based on any of the above embodiments, the identification module is specifically used to: update the tag corresponding to the instruction in the alias tagger to the second address of the instruction remapped to the branch target buffer, and update the valid bit corresponding to the instruction in the alias tagger to valid.

[0068] Based on any of the above embodiments, the recording module is specifically used for: During each execution of the instruction, the actual execution result of the instruction is compared with the predicted execution result; If the actual execution result is inconsistent with the predicted execution result, the actual execution result is used as the historical execution information of the instruction and written into the branch target buffer at the position corresponding to the first address obtained by mapping the instruction based on the first index pattern. If the first address does not hit the branch target buffer, and there are no invalid paths to replace it in the branch target buffer, then the instruction is remapped to the second address in the branch target buffer based on the second index pattern, and the historical execution information of the instruction is written to the position corresponding to the second address in the branch target buffer where the instruction is remapped, and the number of times the first address of the instruction conflicts with the address corresponding to other instructions during the execution process is increased by 1.

[0069] The instruction prediction apparatus provided in this application embodiment can be used to execute the instruction prediction method provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0070] Figure 5 A schematic diagram of an electronic device 10, which can be used to implement embodiments of this application, is shown. The electronic device 10 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 10 may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, user equipment, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0071] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0072] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks and wireless networks.

[0073] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above.

[0074] In some embodiments, the methods described above can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the methods of any of the embodiments described above by any other suitable means (e.g., by means of firmware).

[0075] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0076] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0077] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0078] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device 10, which includes: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device 10. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0079] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0080] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0081] This application also provides a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the instruction prediction method as described in any of the above embodiments.

[0082] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0083] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An instruction prediction method, characterized by, The method comprises the following steps: determining the type of the current instruction, wherein the type is an alias type or a non-alias type, the alias type indicating that the current instruction conflicts with addresses corresponding to other instructions based on a first index mode mapping to a first address in a branch target buffer; in the case that the type of the current instruction is the alias type, determining that the current instruction is remapped to a second address in the branch target buffer based on a second index mode, the second address being different from the first address; obtaining the historical execution information of the current instruction from the second address to obtain a prediction result of the current instruction.

2. The method of claim 1, wherein, The step of determining the type of the current instruction comprises the following steps: determining the type of the current instruction by querying an alias marker; wherein the alias marker is used to identify and mark the type of any instruction according to the remapping of the instruction in the historical execution process.

3. The method of claim 2, wherein, The alias marker is used to mark the following entries: a label used to record that the instruction of the alias type is remapped to the second address in the branch target buffer based on the second index mode; a valid bit used to indicate whether the remapping corresponding to the instruction is valid; The step of determining the type of the current instruction by querying the alias marker comprises the following steps: in the case that the value of the valid bit corresponding to the current instruction indicates that the corresponding remapping is valid, determining that the type of the current instruction is the alias type.

4. The method of claim 2, wherein, The method further comprises the following steps: for any instruction, recording the number of times that the first address of the instruction conflicts with addresses corresponding to other instructions in the execution process by using a counter; in the case that the counter accumulates to saturation, marking the instruction as the alias type by using the alias marker.

5. The method of claim 4, wherein, The step of marking the instruction as the alias type by using the alias marker comprises the following steps: updating the label corresponding to the instruction in the alias marker to the second address to which the instruction is remapped in the branch target buffer, and updating the valid bit corresponding to the instruction in the alias marker to valid.

6. The method of claim 4, wherein, The step of recording the number of times that the first address of the instruction conflicts with addresses corresponding to other instructions in the execution process by using the counter comprises the following steps: in the process of executing the instruction each time, comparing the actual execution result of the instruction with a predicted execution result; if the actual execution result is inconsistent with the predicted execution result, writing the actual execution result as the historical execution information of the instruction into a position in the branch target buffer corresponding to the first address obtained by mapping the instruction based on the first index mode; if the first address does not hit the branch target buffer, and there is no invalid path in the branch target buffer to replace, remapping the instruction to the second address in the branch target buffer based on the second index mode, writing the historical execution information of the instruction into a position corresponding to the second address to which the instruction is remapped in the branch target buffer, and increasing the number of times that the first address of the instruction conflicts with addresses corresponding to other instructions in the execution process by 1.

7. An instruction prediction apparatus characterized by comprising: The method comprises the following steps: determining a type of a current instruction, wherein the type is an alias type or a non-alias type, the alias type indicating that the current instruction conflicts with addresses corresponding to other instructions based on a first index pattern mapping to a first address in a branch target buffer; remapping, when the type of the current instruction is the alias type, the current instruction based on a second index pattern to a second address in the branch target buffer, the second address being different from the first address; obtaining, from the second address, historical execution information of the current instruction to obtain a prediction result of the current instruction.

8. An electronic device, comprising: comprising: at least one processor; a memory connected with the at least one processor in communication; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the instruction prediction method according to any one of claims 1-6.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the instruction prediction method according to any one of claims 1-6.

10. A computer program product comprising computer programs and / or instructions, characterized in that, The computer program and / or instructions are executed by the processor to implement the instruction prediction method according to any one of claims 1-6.

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