Memory system and information processing system

Abstract

Provided are a memory system and an information processing system capable of verifying whether a parity for data recovery is correct. A memory system according to an embodiment is configured to generate a first parity bit based on first data stored in a first memory system and second data stored in a second memory system, write the first parity bit to a non-volatile memory, receive third data, which is update data of the first data, from a host, receive the first data from the first memory system, and write the first parity bit to the second memory system. The first parity is read from the non-volatile memory, a second parity is generated on the basis of the first parity, the first data, and the third data, first restored data is generated on the basis of the second parity, the first parity, and the first data, and the first restored data is compared with the third data.

Description

Technical Field

[0001] The implementation methods described herein generally relate to memory systems and information processing systems. Background Technology

[0002] Regarding existing technical literature:

[0003] In recent years, memory systems with non-volatile memory and information processing systems with host and multiple memory systems have become widespread. As one such memory system, solid-state drives (SSDs) with NAND flash memory are known. SSDs are used as the main storage devices in various computing devices.

[0004] To improve the fault tolerance of information processing systems, Redundant Arrays of Inexpensive (or Independent) Disks (RAID) are sometimes used. RAID is a technique that distributes data across multiple storage systems to improve the redundancy and access performance of the stored data. For example, in RAID-5, the data and parity bits for the data are distributed across multiple storage systems. An example of parity bits is Error Correction Code (ECC). Thus, even if a storage system storing certain data fails, the data stored in the failed storage system can be recovered by using other data stored in other storage systems and the parity bits. As another example of RAID, RAID-6, which stores two parity bits for the data, is known.

[0005] Although parity bits are generated based on the data, the data cannot be restored if the generated parity bits are incorrect. Summary of the Invention

[0006] The purpose of this invention is to provide a memory system and an information processing system capable of verifying the correctness of parity bits used for data recovery.

[0007] The memory system according to the implementation includes: an interface circuit capable of communicating with a host and multiple external memory systems; non-volatile memory; and a controller. The controller is configured to: generate a first parity bit based on first data stored in a first memory system among the multiple external memory systems and second data stored in a second memory system among the multiple external memory systems; write the first parity bit to the non-volatile memory; receive third data as updated data of the first data from the host via the interface circuit; receive the first data from the first memory system via the interface circuit; read the first parity bit from the non-volatile memory; generate a second parity bit based on the first parity bit, the first data, and the third data; generate first restored data based on the second parity bit, the first parity bit, and the first data; and compare the first restored data with the third data received from the host. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating an example of the configuration of an information processing system involved in the implementation method.

[0009] Figure 2 This is a block diagram illustrating an example of the configuration of a memory system involved in an implementation.

[0010] Figure 3 This is a diagram illustrating an example of a RAID-6 configuration based on the memory system described in the implementation.

[0011] Figure 4 This is a diagram illustrating an example of a partial update processing sequence involved in an implementation method.

[0012] Figure 5 This is a diagram illustrating an example of the processing sequence for Full Stripe Write as described in the implementation method.

[0013] Explanation of reference numerals in the attached figures:

[0014] 2…Host, 3…Memory System, 4…Switch, 5…NAND Flash Memory, 7…Controller, 11…Host I / F, 141…Command Control Unit, 142…Read Control Unit, 143…XOR Calculation Unit, 144…Write Control Unit Detailed Implementation

[0015] The embodiments are described below with reference to the accompanying drawings. The following description illustrates apparatus or methods for embodying the technical concept of the embodiments. The technical concept of the embodiments is not limited to the structure, shape, arrangement, material, etc., of the constituent elements described below. Variations readily conceived by those skilled in the art are naturally included within the scope of this disclosure. To make the description clearer, the size, thickness, planar dimensions, or shape of each element are sometimes shown schematically relative to the actual elements. In multiple drawings, elements with different dimensional relationships or ratios are sometimes included. In multiple drawings, the same reference numerals are sometimes applied to corresponding elements, and repeated descriptions are sometimes omitted. Sometimes several elements are given multiple names, but these examples are merely illustrative and do not preclude the possibility of giving these elements other names. Elements not given multiple names are not excluded from being given other names. "Connection" includes not only direct connections but also connections via other elements. Unless the number of elements is specified as multiple, the element can be a single element or multiple elements.

[0016] (Example of an information processing system)

[0017] Figure 1 This is a diagram illustrating an example of the configuration of the information processing system 1 according to the embodiment. The information processing system 1 includes a host device 2, multiple memory systems 3, and a switch 4.

[0018] The host device 2 can be a storage server that stores large amounts of diverse data on multiple storage systems 3, or it can be a server or a personal computer. In this specification, the host device 2 is referred to as host 2.

[0019] Multiple memory systems 3 can be configured into RAID-5 or RAID-6. RAID-5, storing one parity bit of data, includes at least three memory systems. RAID-6, storing two parity bits of data, includes at least four memory systems. This specification illustrates the case of multiple memory systems 3 configured into RAID-6. Figure 1 In this document, the multiple memory systems 3 refer to the case where there are 5 memory systems 3-1, 3-2, 3-3, 3-4, and 3-5. In this specification, one of the multiple memory systems 3 is sometimes referred to as memory system 3.

[0020] Memory system 3 is a semiconductor storage device configured to write data to and read data from non-volatile memory. Memory system 3 is also referred to as a storage device. An example of memory system 3 is a solid-state drive (SSD). An example of non-volatile memory is NAND flash memory. Memory system 3 can be used as a storage device for host 2. Memory system 3 can be built into host 2 or connected to host 2 via cable or network.

[0021] Switch 4 is a device that interconnects host 2 and multiple memory systems 3. Switch 4 has a control circuit (not shown) that controls the communication between host 2 and multiple memory systems 3.

[0022] The interface used to connect host 2 to multiple memory systems 3 via switch 4 conforms to PCI Express. TM (PCIe TM ), NVM Express TM (NVMe TM Specifications such as ) are available. In this manual, switch 4 is also referred to as PCIe switch 4.

[0023] The following describes the configuration examples of host 2 and memory system 3.

[0024] (Example of host 2 configuration)

[0025] The host 2 may also have a central processing unit (CPU) 21 and random access memory (RAM) 22.

[0026] CPU 21 is at least one processor. CPU 21 controls the operation of various components within host 2. CPU 21 controls communication between host 2 and memory system 3. CPU 21 sends various commands to memory system 3. Examples of commands sent to memory system 3 include read commands and write commands. Host 2 may also include a control circuit (interface) (not shown) that controls communication between host 2 and memory system 3. CPU 21 communicates with memory system 3 via this control circuit.

[0027] RAM22 is, for example, volatile memory. RAM22 can also be dynamic random access memory (DRAM) or static random access memory (SRAM). The storage area of ​​RAM22 can also be allocated as a buffer area for temporary data storage. In the buffer area, data to be written to memory system 3 and data to be read from memory system 3 can also be stored.

[0028] (Example of memory system 3)

[0029] Figure 2This is a block diagram illustrating an example of the configuration of the memory system 3 involved in the implementation method.

[0030] The memory system 3 may also include non-volatile memory 5, volatile memory 6, and controller 7.

[0031] An example of non-volatile memory 5 is NAND flash memory. In this specification, non-volatile memory 5 is referred to as NAND flash memory 5. An example of volatile memory 6 is DRAM or SRAM. In this specification, volatile memory 6 is referred to as DRAM 6.

[0032] NAND flash memory 5 includes multiple blocks BLK0, BLK1, BLK2, ..., BLK(m-1). Each of the multiple blocks BLK0, BLK1, BLK2, ..., BLK(m-1) includes multiple pages PG0, ..., PG(n-1). In this specification, an unspecified block among the multiple blocks is sometimes referred to as a block BLK. An unspecified page among the multiple pages is sometimes referred to as a page PG. The block BLK functions as the smallest unit for data deletion operations. The block BLK is sometimes also referred to as a "deleted block" or a "physical block." Each of the multiple pages PG0, ..., PG(n-1) includes multiple memory cells commonly connected to a single word line. The page PG functions as the unit for data write and data read operations. A word line can also function as the unit for data write and data read operations.

[0033] In DRAM6, there may also be a firmware storage area, a logical / physical address translation table 31 cache area, and a temporary data storage buffer area.

[0034] Firmware is a program used to control the operation of controller 7. Firmware can also be loaded from NAND flash memory 5 to DRAM 6 when memory system 3 boots up.

[0035] The logical / physical address translation table 31 manages the mapping between logical addresses and physical addresses of the NAND flash memory 5. Logical addresses are addresses used by the host 2 to assign addresses to storage areas of the memory system 3. An example of a logical address is the logical block address (LBA).

[0036] The controller 7 functions as a memory controller configured to control the NAND flash memory 5. The controller 7 may be configured as a system-on-a-chip (SoC).

[0037] In one program / erase cycle (P / E cycle), only one data write to one page of the NAND flash memory 5 can be performed. Therefore, for updated data corresponding to a certain logical address, the controller 7 does not write to the physical storage location that stores the previous data corresponding to that logical address, but writes to another physical storage location. The controller 7 updates the logical / physical address translation table 31 to establish an association between the logical address and the other physical storage location, thereby invalidating the previous data. The data referenced from the logical / physical address translation table 31 (i.e., the data associated with the logical address) is called valid data. On the other hand, data that is not associated with any logical address is called invalid data. Valid data is data for which there is a possibility of subsequent requests to read it from the host 2. Invalid data is data for which there is no longer a possibility of requests to read it from the host 2.

[0038] The controller 7 may also include a host interface circuit (host I / F) 11, a NAND interface circuit (NAND I / F) 12, a DRAM interface circuit (DRAM I / F) 13, and a CPU 14. The aforementioned host I / F 11, NAND I / F 12, DRAM I / F 13, and CPU 14 may also be connected via bus 10.

[0039] The host I / F11 functions as a circuit that receives various commands and data from the host 2 via the PCIe switch 4. The host I / F11 can also function as a circuit that receives various commands, data, and responses to commands from other memory systems 3 via the PCIe switch 4. The host I / F11 forwards the received commands, data, and responses to one of the NAND I / F12, DRAM I / F13, or CPU 14.

[0040] The host I / F11 also functions as a circuit that sends responses to commands and data to the host 2 via the PCIe switch 4. The host I / F11 can also function as a circuit that sends commands, data, and responses to commands to another memory system 3 via the PCIe switch 4. The host I / F11 receives commands, data, and responses to be sent from one of the NAND I / F12, DRAM I / F13, and CPU 14.

[0041] NAND I / F12 electrically connects controller 7 to NAND flash memory 5. NAND I / F12 corresponds to interface specifications such as ToggleDDR and Open NAND Flash Interface (ONFI).

[0042] The NAND I / F12 functions as a NAND control circuit that controls the NAND flash memory 5. The NAND I / F12 can also be connected to multiple memory chips within the NAND flash memory 5 via multiple channels. By driving multiple memory chips in parallel, the bandwidth for accessing the NAND flash memory 5 can be increased.

[0043] DRAM I / F13 functions as a DRAM control circuit that controls access to DRAM6.

[0044] CPU 14 is a processor configured to control host I / F 11, NAND I / F 12, and DRAM I / F 13. CPU 14 performs various processes by executing firmware loaded from NAND flash memory 5 into DRAM 6. The firmware is a control program containing a set of commands for causing CPU 14 to perform various processes. CPU 14 is capable of command processing, etc., for processing various commands from host 2. The operation of CPU 14 is controlled by the firmware executed by CPU 14.

[0045] The functions of each part within controller 7 can be implemented either by dedicated hardware within controller 7 or by firmware executed by CPU 14.

[0046] CPU 14 can also function as command control unit 141, read control unit 142, XOR calculation unit 143, and write control unit 144. CPU 14 can also function as each of the above-mentioned parts by executing firmware.

[0047] Command control unit 141 receives commands sent from host 2 or other memory system 3. Based on the received commands, command control unit 141 controls read control unit 142, XOR calculation unit 143 and write control unit 144.

[0048] If the command control unit 141 receives a read command, it instructs the read control unit 142 to read data from the NAND flash memory 5. If the command control unit 141 receives a parity bit generation command, it instructs the XOR calculation unit 143 to perform an XOR operation on two or more data. The result of the XOR operation on two or more data is the parity bit for the two or more data. Hereinafter, the XOR operation result will be referred to as the parity bit.

[0049] If the command control unit 141 receives a write command, it instructs the write control unit 4 to write data to the NAND flash memory 5.

[0050] Command control unit 141 sends a response to the command to the host 2 or memory system 3 that sent the command. Command control unit 141 may also send commands and data to other memory systems 3. Command control unit 141 may also perform comparisons of more than two pieces of data.

[0051] The read control unit 142 reads data from the NAND flash memory 5 in response to the instruction of the command control unit 141.

[0052] In response to the instruction from the command control unit 141, the XOR calculation unit 143 performs an XOR operation on two or more data points to generate a parity bit.

[0053] The write control unit 144 writes data to the DRAM 6 or the NAND flash memory 5 in response to the instruction of the command control unit 141.

[0054] (An example of RAID)

[0055] Figure 3 This diagram illustrates an example of a RAID-6 configuration comprised of the memory systems 3 described in the embodiment. In RAID-6, parity bits are generated for each piece of data (referred to as stripe data) of a certain size stored in the multiple memory systems 3. In RAID-6, two parity bits, P and Q, are generated. Figure 3 In the example shown, RAID-6 is constructed using three memory systems 3-1, 3-2, and 3-3 for data storage, a memory system 3-4 for parity bit P, and a memory system 3-5 for parity bit Q. Memory system 3-1 stores data segment D0. Memory system 3-2 stores data segment D1. Memory system 3-3 stores data segment D2. Host 2 or memory system 3-4 generates parity bit P based on the striped data, including data segments D0, D1, and D2 stored in memory systems 3-0, 3-1, and 3-2 respectively. Memory system 3-4 stores parity bit P. Host 2 or memory system 3-5 generates parity bit Q based on the striped data, including data segments D0, D1, and D2 stored in memory systems 3-0, 3-1, and 3-2 respectively. Memory system 3-5 stores parity bit Q.

[0056] (Summary of the partial update)

[0057] Host 2 sometimes writes data with different values ​​to a logical address range (e.g., LBA range) of a data segment (i.e., overwrites). This overwriting is called a data segment update. This describes an update (partial update) of a portion of the data stripe stored in a part of the memory system that constitutes the RAID-6 memory system (in this case, data segment D2 stored in memory system 3-3). Data segments D0 and D1 are not updated.

[0058] If data segment D2 is updated, the parity bits P and Q are also updated. The parity bit Old P before the update is represented by Equation 1 using data segments D0 and D1 and the original data segment Old D2.

[0059] Old P = D0 ⊕ D1 ⊕ Old D2 Equation 1

[0060] Here, "⊕" represents the XOR symbol.

[0061] The updated parity bit New P is represented by Equation 2, using data segments D0, D1, and the updated data segment New D2.

[0062]

[0063] Equation 3 represents the parity check bit Old Q before the update.

[0064]

[0065] Here, "·" represents multiplication in the Galois domain.

[0066] Equation 4 represents the updated parity check bit New Q.

[0067]

[0068] The updated parity check bit New Q is given by the following transformation of Equation 4.

[0069]

[0070] Similar to Equations 5 and 6, in the case of partial updates to data D2, Equation 2 for finding the updated parity bit New P is transformed as follows.

[0071]

[0072] As shown in Equations 5 and 6, in the case of a partial update of data segment D2, the updated parity bit New Q is generated using the intermediate data New Q', the updated data segment New D2, and the coefficient g2. The intermediate data New Q' is generated based on the parity bit Old Q before the update and the data segment Old D2 before the update.

[0073] As shown in Equations 7 and 8, in the case of a partial update of data segment D2, the updated parity bit New P is generated using the intermediate data New P' and the updated data segment New D2. The intermediate data New P' is generated based on the parity bit Old Q before the update and the data segment Old D2 before the update.

[0074] Verify that the updated parity bits New P and New Q are correct. If both New P and New Q are correct, the updated data segment New D2 is written to memory system 3-3, the updated parity bit New P is written to memory system 3-4, and the updated parity bit New Q is written to memory system 3-5.

[0075] In the case of a partial update to data segment D2, the logical address ranges of the data segment Old D2 before the update and the data segment New D2 after the update are the same, but the data values ​​of these data segments are different. Similarly, in the case of a partial update to data segments D0 or D1, the logical address ranges of the data segments Old D0 and D1 before the update and the data segments New D0 and D1 after the update are the same, but the data values ​​of these data segments are different.

[0076] (Summary of full stripe write)

[0077] This describes a complete update (whole stripe write) of the data stripes stored in all memory systems that constitute the RAID-6 memory system. Data segments D0, D1, and D2 are updated.

[0078] If data segments D0, D1, and D2 are updated, then parity bits P and Q are also updated. The parity bits Old P before the update are represented by Equation 9, using the original data segments OldD0, OldD1, and OldD2.

[0079]

[0080] The updated data segments New D0, New D1, and New D2 are used, and the updated parity bit NewP is represented by Equation 10.

[0081]

[0082] Equation 11 represents the parity check bit Old Q before the update.

[0083]

[0084] The parity check bit New Q is updated according to Equation 12.

[0085]

[0086] The updated parity check bit New Q is given by the following transformation of Equation 12.

[0087]

[0088]

[0089] Similar to Equations 13 and 14, in the case of writing the entire line, Equation 10 for finding the updated parity bit New P is transformed as follows.

[0090]

[0091] [Mathematical Expression 16]

[0092]

[0093] As shown in Equations 13 and 14, in the case of writing the entire data, the updated parity bit New Q is generated using the intermediate data New Q", the updated data segment NewD2, and the coefficient g2. The intermediate data New Q is generated based on the updated data segment New D0, the updated data segment NewD1, and the coefficients g0 and g1.

[0094] As shown in Equations 15 and 16, in the case of writing the entire data, the intermediate data "New P" and the updated data segment NewD2 are used to generate the updated parity bit New P. The intermediate data "New P" is generated based on the updated data segment New D0 and the updated data segment New D1.

[0095] In the case of writing the entire data segment, the updated parity bits New P and New Q are also verified to be correct. If both New P and New Q are verified to be correct, the updated data segment New D0 is written to memory system 3-1, New D1 is written to memory system 3-2, New D2 is written to memory system 3-3, the updated parity bit New P is written to memory system 3-4, and the updated parity bit New Q is written to memory system 3-5.

[0096] The above description pertains to the verification of the parity bit update during data updates, but the initial parity bit generated during the first data write is also verified. During the first data write, new data segments are written to memory systems 3-1, 3-2, and 3-3, thus the description of a full write operation applies.

[0097] (Summary of parity check)

[0098] In the case of partial updates, as shown in Equation 5, the updated parity bit New Q is generated based on the intermediate data New Q', the updated data segment New D2, and the coefficient g2. Therefore, as shown in Equation 17, memory system 3-5 can restore the updated data segment New D2 to the restored data segment Rebuild D2(Q) based on the updated parity bit New Q, the intermediate data New Q', and the coefficient g2.

[0099]

[0100] Here, " / " represents division in the Galois domain.

[0101] As shown in Equation 6, intermediate data New Q' is generated based on the parity check bit Old Q before the update, the data segment Old D2 before the update, and the coefficient g2.

[0102] If the restored data segment Rebuild D2(Q) based on Equation 17 is consistent with the updated data segment New D2, then the updated parity bit New Q is determined to be correct.

[0103] In the case of partial updates, as shown in Equation 7, the updated parity bit New P is generated based on the intermediate data New P' and the updated data segment New D2. Therefore, as shown in Equation 18, memory system 3-4 can restore the updated data segment New D2 to the restored data segment Rebuild D2(P) based on the updated parity bit New P and the intermediate data New P'.

[0104]

[0105] As shown in Equation 8, intermediate data New P' is generated based on the parity bit Old P before the update and the data segment Old D2 before the update.

[0106] If the restored data segment Rebuild D2(P) restored using Equation 18 based on the updated parity bit New P is consistent with the updated data segment New D2, then the updated parity bit New P is judged to be correct.

[0107] The above description of partial updates applies to the case where data segment D2 is updated. In the case of a partial update where data segments D0 or D1 are updated, memory system 3-5 restores the updated data segment New D0 or D1 to the original data segment Rebuild D0(Q) or D1(Q) as shown in Equation 17, and compares it with the updated data segment New D0 or D1 to determine whether the updated parity bit New Q is correct. Similarly, memory system 3-4 restores the updated data segment New D0 or D1 to the original data segment Rebuild D0(P) or D1(P) as shown in Equation 18, and compares it with the updated data segment New D0 or D1 to determine whether the updated parity bit New P is correct.

[0108] In the case of a full write operation, as shown in Equation 13, the updated parity bit New Q is generated based on the intermediate data New Q”, the updated data segment New D2, and the coefficient g2. Therefore, as shown in Equation 19, the memory system 3-5 can restore the updated data segment New D2 to the restored data segment Rebuild D2(Q) based on the updated parity bit New Q, the intermediate data New Q”, and the coefficient g2.

[0109]

[0110] As shown in Equation 14, intermediate data NewQ is generated based on the updated data segments New D0 and New D1 and the coefficients g0 and g1.

[0111] If the restored data segment Rebuild D2(Q) based on Equation 17 is consistent with the updated data segment New D2, then the updated parity bit New Q is determined to be correct.

[0112] In the case of a full write operation, as shown in Equation 15, the updated parity bit New P is generated based on the intermediate data New P” and the updated data segment New D2. Therefore, as shown in Equation 20, memory system 3-4 can restore the updated data segment D2 to the restored data segment Rebuild D2(P) based on the updated parity bit New P and the intermediate data New P”.

[0113]

[0114] As shown in Equation 16, intermediate data New P is generated based on the updated data segments New D0 and New D1.

[0115] If the restored data segment Rebuild D2(P) after using the updated parity bit New P is consistent with the updated data segment New D2, then the updated parity bit New P is judged to be correct.

[0116] Alternatively, instead of restoring data segment D2, the updated parity bit can be verified by restoring data segment D0 or D1 in the case of a full write operation. That is, memory system 3-5 restores the updated data segment New D0 or D1 to the restored data segment Rebuild D0(Q) or D1(Q) as shown in Equation 19, and compares it with the updated data segment New D0 or D1 to determine if the updated parity bit New Q is correct. Similarly, memory system 3-4 restores the updated data segment New D0 or D1 to the restored data segment Rebuild D0(P) or D1(P) as shown in Equation 20, and compares it with the updated data segment New D0 or D1 to determine if the updated parity bit New P is correct.

[0117] (Partial update processing)

[0118] Figure 4 This is a diagram illustrating an example of a partial update processing sequence involved in an implementation method. Figure 4 This illustrates an example where data segment D2 stored in memory system 3-3 is updated, while data segments D0 and D1 stored in memory systems 3-1 and 3-2, respectively, are not updated. For simplicity, let's start from... Figure 4 The explanation of the generation, verification, and updating of the parity bit P is omitted.

[0119] In the case of updating data segment D2, host 2 sends the updated data segment New D2 to memory system 3-5 (#12) in order to store the updated data segment New D2 in DRAM6 of memory system 3-5.

[0120] Host 2 sends a read command (#14) to memory system 3-3 to read the pre-update data segment Old D2. The read command includes an instruction to forward the read pre-update data segment Old D2 to memory system 3-5.

[0121] The read control unit 142 of memory system 3-3 reads the old data segment Old D2 from NAND flash memory 5. The command control unit 141 of memory system 3-3 sends the old data segment Old D2 to memory system 3-5 (#16) in order to store it in DRAM 6 of memory system 3-5. The command control unit 141 of memory system 3-3 sends a read response indicating that the read is complete to host 2 (#18).

[0122] Host 2 sends a read command (#20) to memory systems 3-5 to read the parity bit Old Q before the update. The read command includes an instruction to store the read parity bit Old Q before the update into DRAM 6.

[0123] The read control unit 142 of the memory system 3-5 reads the parity bit Old Q before the update from the NAND flash memory 5. The read control unit 142 of the memory system 3-5 stores the read parity bit Old Q before the update into the DRAM 6. The command control unit 141 of the memory system 3-5 sends a read response indicating that the read is complete to the host 2 (#22).

[0124] Host 2 sends the parity bit Q generation command to memory system 3-5 (#24). The parity bit Q generation command specifies coefficients g0, g1, and g2.

[0125] The XOR calculation unit 143 of the memory system 3-5 uses the parity bit Old Q before the update, the data segment OldD2 before the update, and the coefficient g2 to generate intermediate data New Q' (#26) for generating the parity bit New Q after the update based on Equation 6.

[0126] The XOR calculation unit 143 of the memory system 3-5 generates the updated parity bit New Q(#28) based on Equation 5, using intermediate data New Q', updated data segment NewD2 and coefficient g2.

[0127] The XOR calculation unit 143 of the memory system 3-5 generates the restored data segment Rebuild D2(Q)(#30) based on Equation 17, using the updated parity bit New Q, intermediate data New Q' and coefficient g2.

[0128] The command control unit 141 of the memory system 3-5 compares the generated restored data segment Rebuild D2(Q) with the updated data segment New D (#32). If they match, the command control unit 141 of the memory system 3-5 determines that the generation of the parity bit Q was successful. If they do not match, the command control unit 141 of the memory system 3-5 determines that the generation of the parity bit Q failed.

[0129] The command control unit 141 of memory system 3-5 sends a parity bit generation response (#34) to host 2, indicating whether the generation of parity bit Q was successful or failed. Upon receiving a response indicating generation failure, host 2 may resend the parity bit generation command to memory system 3-5, notify the user of the error, or stop writing to memory system 3-3.

[0130] Upon receiving a response indicating successful generation, host 2 sends a write command (#36) to memory system 3-5 to write the updated parity bit NewQ. The write control unit 144 of memory system 3-5 writes the updated parity bit NewQ to NAND flash memory 5.

[0131] The command control unit 141 of the memory system 3-5 sends a write response indicating that the write is complete to the host 2 (#38).

[0132] Host 2 sends a write command (#40) to memory system 3-3 to write the updated data segment New D2. This write command includes an instruction to receive the updated data segment New D2 from memory system 3-5. Command control unit 141 of memory system 3-3 reads the updated data segment New D2 stored in DRAM 6 of memory system 3-5. The updated data segment New D2 is sent from memory system 3-5 to memory system 3-3 (#42). Write control unit 144 of memory system 3-3 writes the updated data segment New D2 to NAND flash memory 5. Alternatively, host 2 may forward the updated data segment New D2 along with the write command (#40) to memory system 3-3. In this case, it is not necessary to read the updated data segment New D2 from memory system 3-5 or send the updated data segment New D2 (#42) to memory system 3-3.

[0133] The command control unit 141 of the memory system 3-3 sends a write response indicating that the write is complete to the host 2 (#44).

[0134] Similarly, host 2 sends a parity bit generation command to memory system 3-4 for parity bit P, just like parity bit Q, to verify and update.

[0135] (Processing of writing the entire line)

[0136] Figure 5 This is a diagram used to illustrate an example of the entire write processing sequence. Figure 5 This illustrates an example where data segments D0, D1, and D2, stored in memory systems 3-1, 3-2, and 3-3 that constitute striped data, are updated, respectively. For simplicity, from... Figure 5 The explanation of the generation, verification, and updating of the parity bit P is omitted.

[0137] When data segments D0, D1, and D2 are updated, host 2 sends the updated data segments New D0, New D1, and New D2 to memory system 3-5 (#62, #64, #66) in order to store them in DRAM6 of memory system 3-5.

[0138] Host 2 sends the parity bit Q generation command to memory system 3-5 (#68). The parity bit Q generation command specifies coefficients g0, g1, and g2.

[0139] The XOR calculation unit 143 of the memory system 3-5 uses the updated data segments New D0, New D1 and coefficients g0, g1 to generate intermediate data New Q (#70) for generating the updated parity bit New Q based on Equation 14.

[0140] The XOR calculation unit 143 of the memory system 3-5 generates the updated parity bit New Q(#72) based on Equation 13, using the intermediate data New Q”, the updated data segment New D2 and the coefficient g2.

[0141] The XOR calculation unit 143 of the memory system 3-5 generates the restored data segment Rebuild D2(Q)(#74) based on Equation 19, using the updated parity bit New Q, intermediate data New Q” and coefficient g2.

[0142] The command control unit 141 of the memory system 3-5 compares the generated restored data segment Rebuild D2(Q) with the updated data segment New D2 (#76). If they match, the command control unit 141 of the memory system 3-5 determines that the generation of the parity bit Q was successful. If they do not match, the command control unit 141 of the memory system 3-5 determines that the generation of the parity bit Q failed.

[0143] The command control unit 141 of memory system 3-5 sends a parity bit generation response (#78) to host 2, indicating whether the generation of parity bit Q was successful or failed. Upon receiving a response indicating generation failure, host 2 may resend the parity bit generation command to memory system 3-5, notify the user of the error, or stop writing to memory systems 3-1, 3-2, and 3-3.

[0144] Upon receiving a response indicating successful generation, host 2 sends a write command (#80) to memory system 3-5 to write the updated parity bit NewQ. The write control unit 144 of memory system 3-5 writes the updated parity bit NewQ to NAND flash memory 5.

[0145] The command control unit 141 of the memory system 3-5 sends a write response indicating that the write is complete to the host 2 (#82).

[0146] Host 2 sends write commands (#84, #90, #96) to memory systems 3-1, 3-2, and 3-3 respectively, for writing updated data segments New D0, New D1, and New D2. These write commands include instructions to receive updated data segments New D0, New D1, and New D2 from memory system 3-5 respectively. Command control units 141 of memory systems 3-1, 3-2, and 3-3 read the updated data segments New D0, New D1, and New D2 stored in DRAM 6 of memory system 3-5 respectively. Updated data segments New D0, New D1, and New D2 are sent from memory system 3-5 to memory systems 3-1, 3-2, and 3-3 respectively (#86, #92, #98). Write control units 144 of memory systems 3-1, 3-2, and 3-3 write the updated data segments New D0, New D1, and New D2 to NAND flash memory 5 respectively. Alternatively, host 2 may forward the updated data segments New D0, New D1, and New D2, along with write commands (#84, #90, #96) for writing the updated data segments New D0, New D1, and New D2, to memory systems 3-1, 3-2, and 3-3 respectively. In this case, it is unnecessary to read the updated data segments New D0, New D1, and New D2 from memory system 3-5 to memory systems 3-1, 3-2, and 3-3, or to send the updated data segments New D0, New D1, and New D2 (#86, #92, #98) to memory systems 3-1, 3-2, and 3-3 respectively.

[0147] The command control units 141 of memory systems 3-1, 3-2, and 3-3 respectively send write responses indicating that the write is complete to host 2 (#88, #94, #100).

[0148] Similarly, host 2 sends a generation command to memory system 3-4 for parity bit P, just like parity bit Q, to verify and update.

[0149] Figure 5 This illustrates an example of three updated data segments being updated sequentially according to time sequence, but it is not limited to this; the three updated data segments can also be updated simultaneously in parallel.

[0150] The above description illustrates a RAID-6 configuration using multiple storage systems 3, but the same applies to a RAID-5 configuration using multiple storage systems 3. RAID-5 includes storage systems 3-1, 3-2, and 3-3 for data storage, and storage system 3-4 for parity bit P storage.

[0151] According to at least one embodiment described above, the memory system can verify whether the generated parity bit is correct. This improves the reliability of the information processing system comprising the memory system described in the embodiments.

[0152] According to at least one embodiment described above, the memory system 3-4 or 3-5 includes an interface circuit 11 capable of communicating with the host 2 and multiple external memory systems 3-1, 3-2, and 3-3, a NAND flash memory 5 as non-volatile memory, and a controller 7. The controller 7 generates a first parity bit Old Q based on the first data Old D2 stored in the first memory system 3-3 and the second data Old D1 stored in the second memory system 3-2, and writes the first parity bit Old Q to the NAND flash memory 5. In the partial update where the first data Old D2 is updated to the third data New D2, the controller 7 is configured to receive the third data New D2, which is the update data of the first data Old D2, from the host 2 via the interface circuit 11; receive the first data Old D2 from the first memory system 3-3 via the interface circuit 11; read the first parity bit Old Q from the NAND flash memory 5; generate the second parity bit New Q based on the first parity bit Old Q, the first data Old D2, and the third data New D2; generate the first restored data Rebuild D2(Q) based on the second parity bit New Q, the first parity bit Old Q, and the first data Old D2; and compare the first restored data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0153] In the entire write operation where the first data Old D2 is updated to the third data New D2 and the second data Old D1 is updated to the fourth data New D1, the controller 7 is further configured to receive the fourth data New D1, which is the update data of the second data Old D1, from the host 2 via the interface circuit 11, generate a third parity bit New Q based on the third data New D2 and the fourth data New D1, generate a second recovery data Rebuild D2(Q) based on the third parity bit New Q and the fourth data New D1, and compare the second recovery data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0154] During the first data writing, the controller 7 is further configured to receive the first data Old D2 from the host 2 via the interface circuit 11, receive the second data Old D1 from the host 2 via the interface circuit 11, generate the first parity bit Old Q based on the first data Old D2 and the second data Old D1, generate the third recovery data Rebuild D2(Q) based on the first parity bit Old Q and the second data Old D1, and compare the third recovery data Rebuild D2(Q) with the first data Old D2 received from the host 2.

[0155] According to at least one embodiment described above, the information processing system 1 includes a host 2 and multiple memory systems 3, each including a NAND flash memory 5 as non-volatile memory and a controller 7 electrically connected to the NAND flash memory 5. The multiple memory systems 3 include at least a first memory system 3-3, a second memory system 3-2, and a third memory system 3-5. The first controller 7, serving as the controller 7 of the first memory system 3-3, is configured to store first data Old D2 in the first NAND flash memory 5 of the first memory system 3-3. The second controller 7, serving as the controller 7 of the second memory system 3-2, is configured to store second data Old D1 in the second NAND flash memory 5 of the second memory system 3-2. The third controller 7, which is the controller 7 of the third memory system 3-5, is configured to generate a first parity bit Old Q based on the first data Old D2 and the second data OldD1, and to store the first parity bit Old Q in the third NAND flash memory 5, which is the NAND flash memory 5 of the third memory system 3-5. In the partial update where the first data Old D2 is updated to the third data New D2, the third controller 7 is configured to receive the third data New D2 as the update data of the first data Old D2 from the host 2, receive the first data Old D2 from the first controller 7, read the first parity bit Old Q from the third NAND flash memory 5, generate the second parity bit New Q based on the first parity bit Old Q, the first data Old D2 and the third data New D2, generate the first restored data Rebuild D2(Q) based on the second parity bit NewQ, the first parity bit Old Q and the first data Old D2, and compare the first restored data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0156] In the entire write operation where the first data Old D2 is updated to the third data New D2 and the second data Old D1 is updated to the fourth data New D1, the third controller 7 of the third memory system 3-5 is further configured to receive the fourth data New D1 as the update data of the second data Old D1 from the host 2, generate a third parity bit New Q based on the third data New D2 and the fourth data New D1, generate a second recovery data Rebuild D2(Q) based on the third parity bit New Q and the fourth data New D1, and compare the second recovery data Rebuild D2(Q) with the third data New D2 received from the host 2.

[0157] During the first data writing, the third controller 7 of the third memory system 3-5 is further configured to receive the first data Old D2 from the host 2, receive the second data Old D1 from the host 2, generate the first parity bit Old Q based on the first data Old D2 and the second data Old D1, generate the third recovery data RebuildD2(Q) based on the first parity bit Old Q and the second data Old D1, and compare the third recovery data RebuildD2(Q) with the first data Old D2 received from the host 2.

[0158] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A memory system, wherein, Possessing: an interface circuit capable of communicating with a host and a plurality of external memory systems; a non-volatile memory; and a controller, the controller configured to: generate a first parity based on first data stored in a first memory system among the plurality of external memory systems and second data stored in a second memory system among the plurality of external memory systems, and write the first parity to the non-volatile memory, receive third data that is update data of the first data from the host via the interface circuit, receive the first data from the first memory system via the interface circuit, read out the first parity from the non-volatile memory, generate a second parity based on the first parity, the first data, and the third data, generate first restoration data based on the second parity, the first parity, and the first data, compare the first restoration data with the third data received from the host.

2. The memory system according to claim 1, wherein the controller is further configured to: in a case where the first restoration data is identical to the third data received from the host, write the second parity to the non-volatile memory.

3. The memory system according to claim 2, wherein the controller is further configured to: in a case where the first restoration data is identical to the third data received from the host, transmit a first response indicating success of generation of the second parity to the host via the interface circuit, in a case where the first restoration data is not identical to the third data received from the host, transmit a second response indicating failure of generation of the second parity to the host via the interface circuit.

4. The memory system according to claim 1, wherein the controller is configured to: obtain an exclusive OR of the first data and the second data, thereby generating the first parity.

5. The memory system according to claim 4, wherein the controller is configured to: obtain an exclusive OR among the first parity, the first data, and the third data, thereby generating the second parity.

6. The memory system according to claim 1, wherein the controller is further configured to: receive fourth data that is update data of the second data from the host via the interface circuit, generate a third parity based on the third data and the fourth data, generate second restoration data based on the third parity and the fourth data, compare the second restoration data with the third data received from the host.

7. The memory system according to claim 6, wherein the controller is further configured to: in a case where the second restoration data is identical to the third data received from the host, write the third parity to the non-volatile memory.

8. The memory system according to claim 7, wherein the controller is further configured to: ​ in a case where the second restored data is identical to the third data received from the host, a third response indicating success of generation of the third parity bit is transmitted to the host via the interface circuit, in a case where the second restored data is not identical to the third data received from the host, a fourth response indicating failure of generation of the third parity bit is transmitted to the host via the interface circuit.

9. The memory system according to claim 1, wherein the controller is further configured to: receive the first data from the host via the interface circuit, receive the second data from the host via the interface circuit, generate the first parity bit based on the first data and the second data, generate third restored data based on the first parity bit and the second data, compare the third restored data with the first data received from the host.

10. The memory system according to claim 1, wherein the controller is further configured to: transmit the third data received from the host to the first memory system via the interface circuit.

11. An information processing system, wherein, A host, and a plurality of memory systems each including a nonvolatile memory and a controller electrically connected to the nonvolatile memory, the plurality of memory systems including at least a first memory system, a second memory system, and a third memory system, a first controller as the controller of the first memory system is configured to cause a first nonvolatile memory as the nonvolatile memory of the first memory system to store first data, a second controller as the controller of the second memory system is configured to cause a second nonvolatile memory as the nonvolatile memory of the second memory system to store second data, a third controller as the controller of the third memory system is configured to: generate a first parity bit based on the first data and the second data, cause a third nonvolatile memory as the nonvolatile memory of the third memory system to store the first parity bit, receive third data as update data of the first data from the host, receive the first data from the first controller, read out the first parity bit from the third nonvolatile memory, generate a second parity bit based on the first parity bit, the first data, and the third data, generate first restored data based on the second parity bit, the first parity bit, and the first data, compare the first restored data with the third data received from the host.

12. The information processing system according to claim 11, wherein the third controller transmits a first response indicating success of generation of the second parity bit to the host in a case where the first restored data is identical to the third data received from the host, the host transmits a first write command requesting writing of the second parity bit to the third memory system in accordance with a case where the first response is received, The third controller is further configured to write the second parity bit to the third nonvolatile memory based on receiving the first write command.

13. The information processing system according to claim 11, wherein The third controller is further configured to: in a case where the first restoration data and the third data received from the host do not coincide with each other, transmit a second response indicating a failure of generation of the second parity bit to the host.

14. The information processing system according to claim 11, wherein The third controller is configured to: obtain an exclusive OR of the first data and the second data, thereby generating the first parity bit, obtain an exclusive OR among the first parity bit, the first data, and the third data, thereby generating the second parity bit.

15. The information processing system according to claim 11, wherein The third controller is further configured to: receive, from the host, fourth data that is update data of the second data, generate a third parity bit based on the third data and the fourth data, generate second restoration data based on the third parity bit and the fourth data, compare the second restoration data and the third data received from the host.

16. The information processing system according to claim 15, wherein The third controller is configured to, in a case where the second restoration data and the third data received from the host coincide with each other, transmit a third response indicating a success of generation of the third parity bit to the host, The host is configured to, based on receiving the third response, transmit a second write command that requests writing of the third parity bit to the third memory system, The third controller is further configured to write the third parity bit to the third nonvolatile memory based on receiving the second write command.

17. The information processing system according to claim 11, wherein The third controller is further configured to: receive the first data from the host, receive the second data from the host, generate the first parity bit based on the first data and the second data, generate third restoration data based on the first parity bit and the second data, compare the third restoration data and the first data received from the host.

18. The information processing system according to claim 11, wherein The third controller is further configured to: transmit the third data received from the host to the first controller.

19. The information processing system according to claim 11, wherein The plurality of memory systems further include a fourth memory system, A fourth controller that is the controller of the fourth memory system is configured to: generate a fourth parity bit based on the first data and the second data, cause a fourth nonvolatile memory that is the nonvolatile memory of the fourth memory system to store the fourth parity bit, receive the third data from the host, receive the first data from the first controller, generating a fifth parity bit based on the fourth parity bit, the first data, and the third data, generating fourth recovered data based on the fifth parity bit, the fourth parity bit, and the first data, comparing the fourth recovered data with the third data received from the host.

20. The information processing system according to claim 19, wherein the fourth controller is configured to: generate the fourth parity bit by calculating an exclusive OR of the first data and the second data using a coefficient different from the coefficient used in the generation of the first parity bit, generate the fifth parity bit by calculating an exclusive OR among the fourth parity bit, the first data, and the third data using a coefficient different from the coefficient used in the generation of the second parity bit.

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