A management engine detection reset method and electronic device

Abstract

The application discloses a kind of management engine detection reset method and electronic equipment, it is related to equipment hardware management technical field, can realize the full-scene automation processing of management engine exception, greatly improve equipment stability and operation efficiency.Power-on stage, management controller receives start signal and executes power-on, according to processor power supply ready signal confirmation power-on result;When consecutive failure reaches the set number, send self-check command to management engine, repeat self-check if not as expected, trigger power-on if as expected, terminate test if retry upper limit is exceeded, avoid power-on obstruction and balance troubleshooting efficiency.Operation stage, continuously monitor on-off state, device is verified engine state after delay after power-on to power-off, confirm hang-up and device is still off, reset engine by hardware level power-off, reduce abnormal influence.No manual intervention is needed throughout the process, covers key scenarios, shortens fault recovery duration, reduces operation and maintenance costs, ensures the stability of the entire life cycle of the device, and reduces downtime risks.

Description

Technical Field

[0001] This invention relates to the field of device hardware management technology, and in particular to a management engine detection and reset method and an electronic device. Background Technology

[0002] In electronic device hardware architecture, the Management Engine (ME) is a critical component responsible for the underlying management of the system, and its operational status directly affects the device's boot process and operational stability. In practical applications, the management engine may malfunction due to firmware defects, hardware interference, or other reasons, leading to problems such as device boot failure and system interruption. Handling management engine malfunctions typically relies on manual intervention, which is not only costly to maintain but also has poor fault recovery timeliness, severely impacting the availability and reliability of the device. Summary of the Invention

[0003] This invention provides a management engine detection and reset method and electronic device, which can overcome the shortcomings of management engine exception handling that relies on manual intervention and is inefficient.

[0004] This invention provides a management engine detection reset method for a management controller, comprising:

[0005] After receiving the device start-up trigger signal, the device performs a power-on operation and confirms the device's power-on result based on the processor's power-ready signal.

[0006] When the device fails to power on a set number of times consecutively, a self-test command is sent to the management engine to obtain the feedback data returned by the management engine and to check the operating status of the management engine.

[0007] If the operating status of the management engine is found to be inconsistent with expectations, the step of sending a self-test command to the management engine is repeated; if the operating status of the management engine is found to be consistent with expectations during the repetition, the device is powered on; if the number of repetitions reaches the set limit and the status is still inconsistent with expectations, the test is terminated.

[0008] During equipment operation, the system monitors the power-on / off status of the equipment. After detecting that the equipment has switched from the power-on state to the power-off state, the system checks the operating status of the management engine after a delay. If it is determined that the management engine is stuck and the equipment is still in the power-off state, the system performs a reset of the management engine using a hardware-level power-off operation.

[0009] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described management engine detection and reset methods when executing the computer program.

[0010] The management engine detection and reset method provided by this invention can effectively automate the handling of management engine anomalies across all scenarios, significantly improving equipment operational stability and maintenance efficiency. During the device startup phase, the startup result is determined by real-time monitoring of the processor power-ready signal. After a set number of failed attempts, the management engine self-check is automatically triggered. Combined with a repetitive check mechanism, the engine anomaly is accurately located and attempted to be repaired. If the expected result is met, the startup process is restarted, avoiding startup obstruction due to engine problems. Simultaneously, the check is terminated with a set limit on the number of attempts, balancing troubleshooting efficiency and resource consumption. During the device operation phase, the power-on / off status is continuously monitored. After the device transitions from power-on to power-off, the engine status is checked with a delay. If the engine is confirmed to be stuck and the device is still powered off, a hardware-level power-off reset is performed to quickly restore normal engine operation, reducing the impact of anomalies on subsequent device startups. The entire process requires no manual intervention, covering both startup and operation, and shortens fault recovery time through automated diagnosis, retries, and resets, reducing manual maintenance costs. It also ensures stable operation throughout the device's entire lifecycle, reducing the risk of downtime due to management engine anomalies and improving the device's startup success rate and operational stability.

[0011] In addition, the present invention also provides a corresponding electronic device for the management engine detection and reset method, which has the same or corresponding technical features as the management engine detection and reset method mentioned above, and has the same effect. Attached Figure Description

[0012] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart of the management engine detection and reset method provided in this embodiment of the invention;

[0014] Figure 2 This is a schematic diagram of the device startup phase management engine retry process provided in an embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of the device operation phase management engine hang reset process provided in an embodiment of the present invention;

[0016] Figure 4 This is a schematic diagram of the management engine detection and reset device provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0018] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0019] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] The specific application environment architecture or specific hardware architecture on which the execution of the management engine detection reset method depends is described here.

[0021] The embodiments of the present invention provide a management engine detection and reset method, and the method is described in detail in conjunction with the execution flow of the management engine detection and reset method. Figure 1 A flowchart of the management engine detection and reset method provided in this embodiment of the invention is shown below. Figure 1 As shown, this method is used to manage the controller and includes:

[0022] S101. After receiving the device start-up trigger signal, perform the power-on operation and confirm the device's power-on result based on the processor power-ready signal.

[0023] It should be noted that the device startup trigger signal is the instruction signal that triggers the device to begin the power-on and boot-up process. This can originate from a power button press, a remote wake-up command, or a hardware reset signal, and is the initial trigger condition for the device startup process. The processor power-ready signal is the level signal output by the processor after receiving a stable power supply and completing initialization. It is used to report to the management controller that its power supply and initial state are normal, and is a hardware indicator for determining whether the device booted up successfully. In practical applications, the processor power-ready signal can be the Central Processing Unit Power Good (CPU PWRGD) signal.

[0024] In step S101, the management controller uses the device startup trigger signal as the starting point for its actions. It first drives the power-on operation to ensure the hardware receives basic power, and then verifies the startup effect through the processor's power-ready signal, avoiding the loophole of relying solely on the power-on command while ignoring the actual power supply effect. This operation realizes the linkage between the management controller, the power control module, and the processor: the power control module is responsible for executing the power-on action, the processor provides feedback on the status by outputting a ready signal, and the management controller undertakes the role of overall scheduling and result judgment. The cooperation of the three ensures that the initial stage of device startup is traceable and verifiable, providing accurate status information for subsequent power-on processes or abnormal handling (such as accumulated power-on failures).

[0025] S102. When the device fails to power on a set number of times consecutively, a self-test command is sent to the management engine to obtain the feedback data returned by the management engine and to verify the operating status of the management engine.

[0026] It should be noted that the self-test command is a standardized instruction sent by the management controller to the management engine to detect whether its hardware status and operating functions are normal. It may include parameters such as status read address and response timeout time, and judge whether there is an abnormality in the management engine by feedback data (such as status code and register value).

[0027] In implementation, the management controller can send self-test commands to the management engine via the Inter-Integrated Circuit (I2C) bus. In other words, the communication link between the management controller and the management engine can be the I2C bus.

[0028] In step S102, the self-test is initiated based on a set number of consecutive failed power-on attempts, rather than on a single failure. This avoids erroneous operations caused by occasional signal fluctuations while promptly capturing persistent faults, balancing fault response sensitivity and stability. The management controller targets the management engine, a critical component, by sending a self-test command and then verifies its status through feedback data, rather than blindly checking all hardware, significantly improving fault location efficiency. Simultaneously, the introduction of feedback data (such as status codes and register values) provides clear hardware-based evidence for the verification results, ensuring more accurate judgment of the management engine's operating status and providing reliable decision support for subsequent retry repairs or termination of the verification.

[0029] S103. If the running status of the management engine is found to be unsatisfactory, the step of sending a self-test command to the management engine is repeated. If the running status of the management engine is found to be satisfactory during the repetition, the device is powered on. If the repetition count reaches the set limit and the status is still unsatisfactory, the test is terminated.

[0030] In step S103, if the management engine's status does not meet expectations, the self-test command can be repeatedly sent to provide the engine with multiple opportunities to recover to a normal state (such as dealing with temporary signal interference or brief functional lag), thus increasing the probability of automatic repair. Once the engine status is found to be in line with expectations during the retry period, the device is immediately powered on, achieving a seamless connection between the anomaly repair and power-on process and reducing fault handling time. Setting an upper limit on the number of repetitions can prevent the self-test operation from looping infinitely due to continuous engine anomalies, avoiding excessive consumption of hardware resources (such as management controller computing power and communication link bandwidth), ensuring that the device can terminate invalid diagnostics in a timely manner, and reserving resources and space for subsequent possible manual intervention or other fault handling processes.

[0031] S104. Monitor the power-on / off status of the equipment during operation. After detecting that the equipment has switched from the power-on state to the power-off state, check the running status of the management engine after a delay. If it is determined that the management engine is stuck and the equipment is still in the power-off state, use hardware-level power-off operation to reset the management engine.

[0032] Step S104 continuously tracks the device's power-on / off status, capturing the state transition from power-on to power-off in real time to ensure no fault triggering is missed. Furthermore, a delayed verification mechanism is introduced to avoid misjudgments caused by unstable states during device shutdown (such as brief signal fluctuations), making the management engine status verification more accurate. This invention performs a double confirmation of both the management engine being stuck and the device still being powered off before executing a hardware-level power-off reset. This avoids unnecessary operations affecting normal hardware and directly clears the abnormal engine state through underlying hardware operations.

[0033] It should be noted that the management controller of the present invention can be a Baseboard Management Controller (BMC) or other management controllers, and no limitation is made here.

[0034] The management engine detection and reset method provided in this invention can effectively automate the handling of management engine anomalies across all scenarios, significantly improving device operational stability and maintenance efficiency. During device startup, the startup result is determined by real-time monitoring of the processor power-ready signal. After a set number of failed attempts, the management engine self-check is automatically triggered. Combined with a repetitive check mechanism, the engine anomaly is accurately located and attempted to be repaired. If the expected result is met, the startup process is restarted, avoiding startup obstruction due to engine problems. Simultaneously, the check is terminated with a set limit on the number of attempts, balancing troubleshooting efficiency and resource consumption. During device operation, the power-on / off status is continuously monitored. After the device transitions from power-on to power-off, the engine status is checked with a delay. If the device is confirmed to be stuck and still powered off, a hardware-level power-off reset is performed to quickly restore normal engine operation, reducing the impact of anomalies on subsequent device startups. The entire process requires no manual intervention, covering both startup and operation, and shortens fault recovery time through automated diagnosis, retries, and resets, reducing manual maintenance costs. It also ensures stable operation throughout the device's entire lifecycle, reducing downtime risks caused by management engine anomalies and improving device startup success rate and operational stability.

[0035] Furthermore, in a specific implementation, in the management engine detection and reset method provided in the embodiments of the present invention, step S101 performs a power-on operation and confirms the device's power-on result based on the processor power-ready signal. Specifically, this may include: sending a power-on operation command to the power control module of the device motherboard (MB) to trigger the power supply startup of the device hardware; sequentially connecting the device hardware to power supply according to a preset hardware timing sequence, and monitoring the processor power-ready signal generated by the processor power supply module; determining the device's power-on result based on the processor power-ready signal; if the processor power-ready signal is at the first level, the device is determined to have successfully powered on; if the processor power-ready signal is at the second level and reaches the preset monitoring duration, the device is determined to have failed to power on; the second level is lower than the first level.

[0036] Figure 2 This is a schematic diagram of the device startup phase management engine retry process provided in an embodiment of the present invention. Figure 2As shown, this invention executes the power-on operation of the management controller to initiate the device startup process. Specifically, the power-on operation command first triggers the power control module to start supplying power, and then the device hardware is powered on sequentially according to a preset timing sequence. This avoids hardware damage caused by disordered power supply and ensures the safety and stability of the power supply process. Based on the power-ready signal generated by the processor power supply module, the distinction between the first level (high level) and the second level (low level), combined with a preset monitoring duration to eliminate signal fluctuation interference, provides objective hardware indicators to support the determination of successful or failed startup. A high level processor power-ready signal indicates that the device is currently powered on; a low level signal that has reached the preset monitoring duration indicates that the device is currently powered off. This effectively reduces false judgments and ensures the safety of the device startup phase and the reliability of the result determination.

[0037] Furthermore, in specific implementation, in the management engine detection and reset method provided in the embodiments of the present invention, step S102 involves sending a self-test command to the management engine when the device fails to power on a set number of times consecutively, obtaining feedback data returned by the management engine, and verifying the operating status of the management engine, such as... Figure 2 As shown, this can specifically include: accumulating the number of device startup failures; when the accumulated number reaches a set number, sending a self-test command to the management engine; opening a response waiting window of a set duration, receiving feedback data returned by the management engine during the response waiting window period; and verifying the operating status of the management engine based on the feedback data returned by the management engine.

[0038] In implementation, the management controller can detect power-on results in real time and accumulate the number of failures, rather than initiating diagnosis upon a single failure. This not only eliminates accidental errors caused by power fluctuations, signal interference, and other occasional factors, but also accurately identifies persistent power-on failures that may be caused by management engine anomalies by setting a set number of failures (e.g., 8), preventing early-stage failures from being overlooked. Once the set number of failures is reached, the management controller first sends a self-test command to specifically investigate the management engine. Then, by opening a response waiting window of a set duration, it allows reasonable time for the engine to provide feedback data, preventing misjudgments due to response delays, and avoiding indefinite waiting that consumes hardware resources. Finally, it verifies the engine status based on the feedback data, providing clear data support for the diagnostic results and ensuring that the management engine is accurately identified as the cause of the power-on failure, providing a reliable basis for subsequent repair operations.

[0039] Furthermore, in specific implementation, in the above steps, the operating status of the management engine is checked based on the feedback data returned by the management engine. Specifically, this may include: after receiving feedback data during the response waiting window, matching the status identifier in the feedback data with a preset hardware benchmark; if the match is successful, it is confirmed that the operating status of the management engine meets expectations; if the match fails or the response waiting window ends but no feedback data is received, it is determined that the operating status of the management engine does not meet expectations.

[0040] In implementation, status identifiers refer to specific data (such as binary codes or status codes) returned by the management engine after receiving a self-test command, used to characterize its own hardware status or functional operation. Preset hardware benchmarks refer to standard data (such as standard status codes or hardware parameter thresholds) pre-stored in the management controller to determine whether the management engine's status is normal.

[0041] This invention matches the status identifier in the feedback data with a preset hardware benchmark. For example, the status identifier might be an 8-bit binary status code returned by the management engine (e.g., "00000001" represents a normal core circuit, and "00000010" represents a communication module malfunction). The preset hardware benchmark is a standard set of statuses pre-written into the management controller (e.g., only "00000001" is considered a normal benchmark). By comparing the two, it is possible to directly determine whether the core function of the engine is normal. In addition to cases of matching failure, the failure to receive feedback data at the end of the response waiting window is considered an unexpected status, effectively capturing severe anomalies such as a complete lack of response from the management engine (e.g., engine crash leading to inability to return data). This avoids overlooking extreme fault scenarios due to reliance solely on data matching, further improving the completeness of the verification logic.

[0042] Furthermore, in a specific implementation, in the management engine detection and reset method provided in the embodiments of the present invention, if step S103 detects that the operating status of the management engine meets expectations during the repetition period, the device is triggered to power on. Figure 2 As shown, specifically, it may include: after each completion of the management engine test, determining whether the test result indicates that the management engine's operating status meets expectations; if the test result indicates that the management engine's operating status meets expectations, then stopping the step of sending self-test commands to the management engine and reading the processor power ready signal; confirming whether the device is in a power-off state based on the processor power ready signal; if the processor power ready signal is at the second level, confirming that the device is in a power-off state, sending a power-on command to the logic devices on the device's motherboard to drive the device to perform power-on initialization, until the processor power ready signal switches to the first level, marking the completion of the power-on operation.

[0043] In implementation, a Complex Programmable Logic Device (CPLD) can be selected as the logic device. This invention can immediately stop sending self-test commands after the test results meet expectations, avoiding resource waste and quickly transitioning to the power-on preparation phase, demonstrating efficient linkage between fault repair and device startup. Then, by reading the processor power-ready signal (the second level represents power-off), the device status is confirmed a second time, preventing accidental power-on commands from being sent when the device is already powered on, and avoiding potential hardware risks from repeated startups. After sending the power-on command to the logic device, the processor power-ready signal switching to the first level serves as a marker for power-on completion, ensuring that the device can smoothly complete initialization from the power-off state and reach a stable operating state.

[0044] Furthermore, in a specific implementation, in the above-described management engine detection and reset method provided in the embodiments of the present invention, before executing step S103 of repeatedly executing the step of sending a self-test command to the management engine, it may also include: initializing a repeat count counter.

[0045] Correspondingly, if step S103 fails to meet expectations even after reaching the set upper limit for the number of repetitions, the test is terminated. Figure 2 As shown, specifically, it may include: after each inspection action, if it is determined that the running status of the management engine does not meet expectations, the value of the repetition count counter is incremented; when the value of the repetition count counter reaches the set upper limit, the step of stopping sending self-test commands to the management engine is stopped.

[0046] In implementation, this invention first initializes the retry counter (initial value 0) and sets a limit, such as 60 times. This provides the management engine with ample recovery opportunities through multiple loops (e.g., to handle temporary communication interference, brief functional delays, and other self-healing anomalies). Furthermore, the rule of recording anomalies when the count exceeds or equals the limit avoids infinite looping that consumes I2C communication link bandwidth and management controller computing power, thus achieving reasonable resource management. Each test can send a self-test command via the I2C link, using normal status codes to determine if the engine is normal, unresponsive, or if there are abnormal status codes (covering scenarios such as hangs and abnormal modes), ensuring accurate status judgment. In case of an anomaly, a pause operation can be performed for a set number of seconds (e.g., 1 second) to pause, then increment the counter and return to the loop. This provides the engine with a short recovery time and avoids excessively frequent testing operations through fixed intervals. Upon returning to normal, the device status judgment and boot process can be directly initiated, achieving seamless integration between anomaly repair and boot startup, further ensuring the efficiency of the device from fault diagnosis to recovery.

[0047] Furthermore, in a specific implementation, in the management engine detection and reset method provided in the embodiments of the present invention, step S104, monitoring the power-on / off state of the device during device operation, may specifically include: after the device is powered on, creating a Power Button Override (PBO) monitoring thread; using the Power Button Override monitoring thread to cyclically read the processor power ready signal at a preset monitoring interval; after each reading of the processor power ready signal, comparing the level of the currently read processor power ready signal with the level of the previously read processor power ready signal; if the level of the currently read processor power ready signal is lower than the level of the previously read processor power ready signal, it is determined that the device has switched from the power-on state to the power-off state.

[0048] In implementation, the power button forced operation monitoring thread refers to a background program that runs continuously in the device and is used to capture forced operations on the power button (such as long-pressing the power button) in real time and to monitor changes in the device's power on / off status. It can provide the basis for subsequent determination of the management engine status and execution of hardware-level power-off reset.

[0049] Figure 3 This is a schematic diagram illustrating the hang-up and reset process of the device operation phase management engine provided in an embodiment of the present invention. Figure 3 As shown, after the device completes its power-on initialization, the management controller immediately creates a power button forced operation monitoring thread. This thread runs independently and is continuously active, monitoring the device's power-on / off state and the management engine's operating state. This ensures the thread covers the entire device operation phase and responds in real-time to possible state changes. The power button forced operation monitoring thread can read the processor's power-ready signal in real-time through a hardware interface, using the signal level as the basis for determining the device's power-on / off state: a high signal indicates the device is powered on; a low signal indicates the device is powered off. The power button forced operation monitoring thread can cyclically read the processor's power-ready signal at preset high-frequency intervals (e.g., milliseconds), comparing the level read each time with the previous level to capture whether the signal changes from high to low in real-time, thus determining whether the device has transitioned from powered on to powered off. If no change in signal level is detected, the thread continues to cyclically read; if a change from high to low is detected, the thread triggers a subsequent delayed operation; if a change from low to high is detected, the device's power-on state record is updated, and the cyclic monitoring continues. This allows for the construction of dynamic monitoring logic for device power-on / off state switching, ensuring that the thread startup timing matches the device's operating rhythm, and accurately capturing state changes through level comparison.

[0050] Furthermore, in specific implementation, in the management engine detection and reset method provided in the embodiments of the present invention, after detecting that the device has switched from the power-on state to the power-off state, step S104 delays the verification of the management engine's operating status, such as... Figure 3 Specifically, this may include: when the power button forced operation monitoring thread detects that the device has switched from the power-on state to the power-off state, performing a pause (Sleep) operation of a preset duration; after the preset duration pause operation, sending a self-test command to the management engine; opening a response waiting window of a set duration, and receiving feedback data returned by the management engine during the response waiting window; if feedback data is received during the response waiting window and the status code in the feedback data meets the preset hardware benchmark, then it is determined that the management engine is not hanging; if the status code in the feedback data does not meet the preset hardware benchmark, or if the response waiting window ends but no feedback data is received, then it is determined that the management engine is hanging.

[0051] In implementation, this invention can monitor the device's transition from power-on (processor power-ready signal high level) to power-off (signal low level) and then perform a pause operation for a preset duration (e.g., 20 seconds). This effectively avoids misjudgments caused by brief fluctuations in the signal level and incomplete hardware stability during system shutdown, allowing sufficient time for subsequent testing to stabilize and ensuring the accuracy of the testing starting point. After the delay, a self-test command is sent to specifically investigate the management engine. The response waiting window provides feedback on the reception time limit, and non-response or abnormal status codes can be used as criteria for determining a dead state. This covers both extreme anomalies where the engine has no interaction and situations where there is feedback but the status is abnormal, providing a more comprehensive judgment. The entire detection process comprehensively covers engine anomaly scenarios, significantly improving the accuracy of management engine dead state determination.

[0052] Furthermore, in specific implementation, in the management engine detection and reset method provided in the embodiments of the present invention, if step S104 determines that the management engine is stuck and the device is still in a powered-off state, a hardware-level power-off operation is used to reset the management engine, such as... Figure 3 As shown, specifically, it may include: after determining that the management engine is hanging, reading the processor power ready signal again; based on the reread processor power ready signal, if it is determined that the device is still in a power-off state, sending a power-off button forced operation command to the logic device on the device motherboard, so that the logic device performs a hardware-level power-off operation and forcibly resets the management engine by switching the management engine power supply circuit.

[0053] In implementation, hardware-level power-off operation refers to the operation where the logic devices on the device's motherboard control the on / off state of the management engine's power supply circuit, forcibly clearing the management engine's hang by cutting off and restoring power through low-level hardware actions. After determining that the management engine is hang, the management controller of this invention can immediately read the processor power-ready signal again to confirm whether the current signal is still low (i.e., the device is still in a power-off state). If the signal turns high (the device leaves the power-off state), the reset operation is terminated, and the loop monitoring phase of the power button forced operation monitoring thread is returned. If it is confirmed that the processor power-ready signal is still low (the device remains in a power-off state), the management controller sends a power-off power button forced operation command to the logic devices on the device's motherboard. This command may include setting hardware operation parameters. After receiving the command, the logic devices execute the hardware-level power-off operation: according to a preset mechanism, the power button forced operation action is executed to activate the management engine, while maintaining the device in the S5 (Soft OffState) state (this power-off operation can only be performed in this state), achieving a forced reset by cutting off the management engine's power supply circuit. This ensures the effectiveness of the reset through hardware-level operation, guarantees the necessity and safety of the reset operation, ensures accurate matching of repair needs in different scenarios, and further guarantees the rigor and reliability of the device hardware operation.

[0054] It should be noted that this invention can achieve closed-loop management of fault tracing and continuous monitoring through structured log recording and thread state reset mechanisms, while ensuring operational traceability and long-term operational stability of the equipment. For example, if the inspection result shows that the management engine status meets expectations, the management controller can record the hardware log indicating that the management engine status meets expectations and mark the fault repair node. If the inspection is terminated (the number of repetitions reaches the set limit and the engine status still does not meet the standard), the local hardware log module records the result that the repeated inspection has reached the set limit and the management engine status does not meet expectations, and simultaneously retains the cumulative number of inspections and details of each feedback (such as no response, data mismatch, etc.). This log data can directly provide accurate historical operational basis for subsequent hardware fault location, greatly reducing the difficulty of manual troubleshooting. After the logic device completes the hardware-level power-off reset of the management engine, it can send a reset completion signal to the management controller. After receiving the signal, the controller immediately records the hardware log indicating that the management engine reset is complete, and then triggers the power button to force the operation monitoring thread to reset to the initial state. This ensures that the power button forced operation monitoring thread can quickly resume loop monitoring and continuously track the device power-on / off status and the management engine running status, avoiding monitoring blind spots caused by thread interruption. If the management engine is not stuck or the device has been removed from the shutdown state, the thread will directly return to the monitoring process without additional reset operations. This reduces the time spent on invalid processes and ensures the continuity of monitoring. The overall design further enhances the device's ability to control management engine anomalies throughout the entire lifecycle through the integrity of logs and the high availability of threads.

[0055] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0056] Embodiments of the present invention also provide a management engine detection reset device. Figure 4 This is a schematic diagram of the management engine detection and reset device provided in an embodiment of the present invention. This embodiment is based on the perspective of functional modules, such as… Figure 4 As shown, the device includes:

[0057] The power-on result confirmation module 10 is used to receive the device start-up trigger signal, perform the power-on operation, and confirm the power-on result of the device based on the processor power-ready signal.

[0058] The self-test command sending module 11 is used to send a self-test command to the management engine when the device fails to start up a set number of times in a row, obtain feedback data returned by the management engine, and check the running status of the management engine.

[0059] The power-on trigger module 12 is used to repeatedly execute the step of sending a self-test command to the management engine if the running status of the management engine is not as expected; if the running status of the management engine is as expected during the repetition, the device is triggered to power on; if the number of repetitions reaches the set limit and the running status is still not as expected, the test is terminated.

[0060] The management engine reset module 13 is used to monitor the power-on and power-off status of the device during operation. After detecting that the device has switched from the power-on state to the power-off state, it checks the running status of the management engine after a delay. If it is determined that the management engine is stuck and the device is still in the power-off state, the management engine is reset by using hardware-level power-off operation.

[0061] In the management engine detection and reset device provided in this embodiment of the invention, the interaction of the four modules effectively achieves full-scenario automated handling of management engine anomalies, significantly improving equipment operational stability and maintenance efficiency: During the equipment startup phase, the startup result is determined by real-time monitoring of the processor power-ready signal. After a set number of failures, the management engine self-check is automatically triggered. Combined with a repetitive check mechanism, the engine anomaly is accurately located and attempted to be repaired. If the expected result is met, the startup process is restarted, avoiding startup obstruction caused by engine problems. At the same time, the check is terminated with a set limit of the number of attempts, balancing fault diagnosis efficiency and resource consumption. During the equipment operation phase, the power-on and power-off status is continuously monitored. After the equipment switches from power-on to power-off, the engine status is checked with a delay. If it is confirmed to be stuck and the equipment is still off, a hardware-level power-off reset is performed to quickly restore the normal operation of the engine, reducing the impact of anomalies on subsequent equipment startups. The entire process requires no manual intervention, covering both the two key scenarios of startup and operation. It shortens the fault recovery time through automated diagnosis, retries, and resets, reducing manual maintenance costs, while ensuring stable operation throughout the entire equipment lifecycle, reducing the risk of downtime due to management engine anomalies, and improving the startup success rate and operational stability of the equipment.

[0062] Since the embodiments of the management engine detection and reset device and the management engine detection and reset method correspond to each other, the descriptions of the features in the embodiments corresponding to the management engine detection and reset device can be found in the relevant descriptions of the embodiments corresponding to the management engine detection and reset method, and will not be repeated here. Furthermore, it has the same beneficial effects as the management engine detection and reset method mentioned above.

[0063] Furthermore, in a specific implementation, in the management engine detection and reset device provided in the embodiments of the present invention, the power-on result confirmation module 10 can be specifically used to send a power-on operation command to the power control module of the device motherboard to trigger the power supply start of the device hardware; according to the preset hardware timing sequence, power is sequentially supplied to the device hardware, and the processor power ready signal generated by the processor power supply module is monitored; based on the processor power ready signal, the power-on result of the device is determined; if the processor power ready signal is at the first level, the device is determined to have successfully powered on; if the processor power ready signal is at the second level and reaches the preset monitoring time, the device is determined to have failed to power on; the second level is lower than the first level.

[0064] Furthermore, in a specific implementation, in the management engine detection and reset device provided in the embodiments of the present invention, the self-test command sending module 11 can be used to accumulate the number of times the device fails to start up, and when the accumulated number reaches a set number, send a self-test command to the management engine; open a response waiting window of a set duration, and receive feedback data returned by the management engine during the response waiting window; and check the running status of the management engine based on the feedback data returned by the management engine.

[0065] Furthermore, in a specific implementation, in the management engine detection and reset device provided in the embodiments of the present invention, the power-on trigger module 12 can be specifically used to determine whether the current test result indicates that the operating state of the management engine meets expectations after each completion of the management engine test; if the current test result indicates that the operating state of the management engine meets expectations, then the step of sending a self-test command to the management engine is stopped, and the processor power ready signal is read; based on the processor power ready signal, it is confirmed whether the device is in a power-off state; if the processor power ready signal is at the second level, then it is confirmed that the device is in a power-off state, and a power-on command is sent to the logic device on the device motherboard to drive the device to perform power-on initialization until the processor power ready signal switches to the first level, marking the completion of the power-on operation. The power-on trigger module can also be used to initialize a repetition count counter; after each test action, if it is determined that the operating state of the management engine does not meet expectations, then the value of the repetition count counter is incremented; when the value of the repetition count counter reaches a set upper limit, the step of sending a self-test command to the management engine is stopped.

[0066] Furthermore, in a specific implementation, in the management engine detection and reset device provided in the embodiments of the present invention, the management engine reset module 13 can be specifically used to create a power button forced operation monitoring thread after the device is powered on; use the power button forced operation monitoring thread to cyclically read the processor power ready signal at a preset monitoring interval; after each reading of the processor power ready signal, compare the level of the currently read processor power ready signal with the level of the previously read processor power ready signal; if the level of the currently read processor power ready signal is lower than the level of the previously read processor power ready signal, it is determined that the device has switched from the power-on state to the power-off state. The management engine reset module can also be used to perform a preset-duration pause operation when the power button forced operation monitoring thread detects that the device has switched from the power-on state to the power-off state. After the preset-duration pause operation, a self-test command is sent to the management engine. A response waiting window of a set duration is opened, during which feedback data returned by the management engine is received. If feedback data is received during the response waiting window and the status code in the feedback data meets the preset hardware benchmark, it is determined that the management engine is not hanged. If the status code in the feedback data does not meet the preset hardware benchmark, or if the response waiting window ends but no feedback data is received, it is determined that the management engine is hanged. The management engine reset module can also be used to, after determining that the management engine is hanged, read the processor power-ready signal again. Based on the reread processor power-ready signal, if it is determined that the device is still in the power-off state, a power-off forced operation command is sent to the logic devices on the device motherboard to cause the logic devices to perform a hardware-level power-off operation, thereby forcibly resetting the management engine by switching the management engine power supply circuit.

[0067] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described management engine detection reset method embodiments.

[0068] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described management engine detection reset method embodiments when running.

[0069] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0070] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described management engine detection and reset method embodiments.

[0071] Embodiments of the present invention also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described management engine detection and reset method embodiments.

[0072] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0073] The above provides a detailed description of the management engine detection and reset method and electronic device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for resetting a management engine, characterized in that, Used to manage controllers, including: After receiving the device start-up trigger signal, the device performs a power-on operation and confirms the device's power-on result based on the processor's power-ready signal. When the device fails to power on a set number of times consecutively, a self-test command is sent to the management engine to obtain the feedback data returned by the management engine and to check the operating status of the management engine. If the operating status of the management engine is found to be inconsistent with expectations, the step of sending a self-test command to the management engine is repeated; if the operating status of the management engine is found to be consistent with expectations during the repetition, the device is powered on; if the number of repetitions reaches the set limit and the status is still inconsistent with expectations, the test is terminated. The device monitors the device's power-on / off status during operation. When the device switches from power-on to power-off, a pause operation of preset duration is performed. After the preset pause operation, a self-test command is sent to the management engine. A response waiting window of preset duration is opened, and feedback data returned by the management engine is received during the response waiting window. If feedback data is received during the response waiting window and the status code in the feedback data meets the preset hardware benchmark, it is determined that the management engine is not hanged. If the status code in the feedback data does not meet the preset hardware benchmark, or if the response waiting window ends but no feedback data is received, it is determined that the management engine is hanged. If it is determined that the management engine is hanged and the device is still in the power-off state, the management engine is reset using a hardware-level power-off operation.

2. The management engine detection and reset method according to claim 1, characterized in that, Perform a power-on operation and confirm the device's startup result based on the processor's power-ready signal, including: Send a power-on command to the power control module of the device motherboard to trigger the power supply start of the device hardware; According to the preset hardware timing, power is supplied to the device hardware in sequence, and the processor power ready signal generated by the processor power supply module is monitored. Based on the processor power-ready signal, determine the device's power-on result; If the processor power-ready signal is at the first level, the device is determined to have powered on successfully. If the processor power-ready signal is at the second level and reaches the preset monitoring time, the device is determined to have failed to power on; the second level is lower than the first level.

3. The management engine detection and reset method according to claim 1, characterized in that, When the device fails to power on a set number of times consecutively, a self-test command is sent to the management engine to obtain feedback data returned by the management engine and to verify the operating status of the management engine, including: The number of device startup failures is accumulated, and when the accumulated number reaches a set number, a self-test command is sent to the management engine; Open a response waiting window of a set duration, and receive feedback data returned by the management engine during the response waiting window period; The operating status of the management engine is checked based on the feedback data returned by the management engine.

4. The management engine detection and reset method according to claim 3, characterized in that, Based on the feedback data returned by the management engine, the operating status of the management engine is checked, including: After receiving feedback data during the response waiting window, the status identifier in the feedback data is matched with a preset hardware benchmark. If the match is successful, it confirms that the operating status of the management engine is as expected; If the matching fails or the response waiting window ends but no feedback data is received, it is determined that the operating status of the management engine does not meet expectations.

5. The management engine detection and reset method according to claim 2, characterized in that, If the operating status of the management engine is found to be as expected during the repetition period, the device is triggered to power on, including: After each inspection of the management engine is completed, determine whether the inspection result indicates that the operating status of the management engine meets expectations. If the result of this test is that the operating status of the management engine is as expected, then stop sending the self-test command to the management engine and read the processor power ready signal; The processor power-ready signal is used to confirm whether the device is in a power-off state. If the processor power ready signal is at the second level, the device is confirmed to be in a power-off state. A power-on command is sent to the logic devices on the device motherboard to drive the device to perform power-on initialization until the processor power ready signal switches to the first level, marking the completion of the power-on operation.

6. The management engine detection and reset method according to claim 2, characterized in that, Before repeatedly executing the step of sending a self-test command to the management engine, the method further includes: Initialize the repetition count counter; If the expected result is not achieved even after reaching the set limit for the number of repetitions, the test will be terminated, including: After each inspection action is performed, if it is determined that the running status of the management engine does not meet expectations, the value of the repetition count counter is incremented. When the value of the repetition count counter reaches the set upper limit, the step of stopping the sending of self-test commands to the management engine is stopped.

7. The management engine detection and reset method according to claim 1, characterized in that, Monitoring the on / off status of the equipment during operation includes: After the device is powered on, create a monitoring thread that forces operation via the power button; The power button is used to force the monitoring thread to read the processor power ready signal cyclically at a preset monitoring interval; After each reading of the processor power ready signal, the level of the currently read processor power ready signal is compared with the level of the previously read processor power ready signal; If the level of the processor power ready signal currently read is lower than the level of the processor power ready signal read previously, it is determined that the device has switched from the power-on state to the power-off state.

8. The management engine detection and reset method according to claim 1, characterized in that, If it is determined that the management engine is stuck and the device is still powered off, a hardware-level power-off operation is used to reset the management engine, including: After confirming that the management engine is hanging, read the processor power ready signal again; Based on the processor power-ready signal read again, if it is determined that the device is still in the power-off state, a power-off forced operation command is sent to the logic device on the device motherboard to cause the logic device to perform a hardware-level power-off operation and forcibly reset the management engine by switching the management engine power supply circuit.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the management engine detection reset method as described in any one of claims 1 to 8 when executing the computer program.

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