Hardware test item generation method and device, electronic equipment and storage medium

Abstract

The invention provides a hardware test item generation method and device, electronic equipment and a storage medium, and the method comprises the steps: generating a record of each pin in a to-be-tested single board based on the product design information of the to-be-tested single board, and the record comprises the description information of the pin and the description information of the connected component and network. And based on the record of each pin, predicting a test item corresponding to each pin of the to-be-tested single board through a trained model.

Description

Technical Field

[0001] This specification relates to the field of hardware testing technology, and in particular to methods, apparatuses, electronic devices, and storage media for generating test items for hardware. Background Technology

[0002] In the research and development and production of digital products (such as servers, switches, and customized GPU cards), single boards are prone to defects such as short circuits, open circuits, and logic errors due to differences in materials and process deviations.

[0003] Therefore, experts need to have a deep understanding of the circuit schematics and consult a vast amount of chip documentation to comprehend the working principle of the board. This allows them to generate a test list for the board, which will list the test items for different functions of the board. Testers then design corresponding test scripts based on the descriptions of the test items in the test list to test the board and discover hardware defects.

[0004] However, designing test items based on a manual understanding of the circuit board's operating principles, which focuses on functional levels, can easily lead to overlooking the role of certain pins due to insufficient experience, resulting in inadequate test coverage. Furthermore, the sheer number of pins (tens of thousands) on a single circuit board further complicates the analysis, making the DFT (Design for Testability) analysis cycle for that board lengthy. In summary, this approach cannot meet the demands of end-to-end quality control and efficient production. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this specification provides methods, apparatus, electronic devices, and storage media for generating hardware test items.

[0006] According to a first aspect of the embodiments of this specification, a method for generating test items for hardware is provided, the method comprising: Based on the product design information of the board under test, a record is generated for each pin of the board under test. The record includes the description information of the pin and the description information of the components and networks connected to it. Based on the record of each pin, the test item corresponding to each pin of the board under test is predicted by the trained model.

[0007] According to a second aspect of the embodiments of this specification, a hardware test item generation apparatus is provided, the apparatus comprising: The pin record generation module is used to generate a record for each pin in the board under test based on the product design information of the board under test. The record includes the description information of the pin and the description information of the components and networks connected to it. The test item prediction module is used to predict the test item corresponding to each pin of the board under test based on the records of each pin and through a trained model.

[0008] According to a third aspect of the embodiments of this specification, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method as described in the first aspect.

[0009] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method as described in the first aspect.

[0010] The technical solutions provided in the embodiments of this specification may include the following beneficial effects: In this embodiment of the specification, firstly, regarding the input data for building the model, this solution generates a record of each pin in the board under test based on the product design information of the board under test. Then, using the trained model, based on the record of each pin, it predicts the test item corresponding to each pin of the board under test.

[0011] As can be seen, this solution refines test items from the manually designed functional level down to the pin level. Since each pin corresponds to a test item, it can cover every pin on the board under test, thereby improving test coverage and avoiding test blind spots. Furthermore, generating test items at the pin level supports testing at different hardware levels (such as board-level and system-level), thus improving testing efficiency.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0014] Figure 1 This is a flowchart illustrating a method for generating test items for hardware according to an exemplary embodiment of this specification.

[0015] Figure 2 This is a schematic diagram illustrating the training process of a model according to an exemplary embodiment of this specification.

[0016] Figure 3 This is a schematic diagram illustrating the application of a knowledge base and knowledge enhancement technology according to an exemplary embodiment of this specification.

[0017] Figure 4 This is a schematic diagram illustrating the process of generating test items for hardware according to an exemplary embodiment of this specification.

[0018] Figure 5 This is a schematic diagram of the structure of an electronic device according to an exemplary embodiment of this specification.

[0019] Figure 6 This is a block diagram of a hardware test item generation apparatus according to an exemplary embodiment of this specification. Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0021] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0022] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0023] In existing technologies, hardware testing commonly employs a functional-level testing strategy. This method typically involves experts in the field manually defining several "key functional modules" (such as power management, clock distribution, high-speed interfaces, reset control, etc.) based on their understanding of the overall working principle of the board, and designing corresponding test items around these modules.

[0024] For example, the content of any record in this test list is: However, functional partitioning relies on human abstraction, while modern single-board computers are highly integrated (often containing hundreds of chips and tens of thousands of pins), with extremely complex internal signal interactions. Experts can often only cover known critical paths or historical high-frequency failure points, easily overlooking peripheral functions, low-frequency usage scenarios, and cross-module coupling behaviors. For example, many non-core but critical pins are systematically ignored in the test list because they are not associated with any "functional module," creating structural testing blind spots and failing to meet end-to-end quality control requirements.

[0025] Furthermore, whenever a new board with a revised hardware architecture is introduced, experts need to study entirely new circuit schematics and consult vast amounts of chip documentation to manually analyze pin signal flow and functional dependencies in order to compile a test list. This lengthy analysis process cannot meet the demands of efficient production.

[0026] To address the aforementioned technical problems, this disclosure provides a method for generating hardware test items. For example... Figure 1 As shown, steps 101-102 are included: Step 101: Based on the product design information of the board under test, generate a record for each pin of the board under test. The record includes the description information of the pin and the description information of the components and networks connected to it.

[0027] Step 102: Based on the record of each pin, predict the test item corresponding to each pin of the board under test using the trained model.

[0028] In this embodiment, firstly, regarding the input data for building the model, this solution generates a record of each pin in the board under test based on the product design information of the board under test. Then, using the trained model, based on the record of each pin, it predicts the test item corresponding to each pin of the board under test.

[0029] As can be seen, this solution refines test items from the manually designed functional level down to the pin level. Since each pin corresponds to a test item, it can cover every pin on the board under test, thereby improving test coverage and avoiding test blind spots. Furthermore, generating test items at the pin level supports testing at different hardware levels (such as board-level and system-level), thus improving testing efficiency.

[0030] The number of boards to be tested can be one or more. If there are multiple boards to be tested, the applicable scenario is to test a device composed of multiple boards. Specifically, based on the product design information of multiple boards to be tested, a record of each pin in each board to be tested is generated.

[0031] When there are multiple boards, the traditional approach is to design test items for each board at the functional level, lacking collaborative testing between boards. Because this solution refines test items to the pin level, compared to designing test items based on board functions, by inputting the pin records of multiple boards from the same device into the model, the test scenario can be expanded to test the entire device.

[0032] In one embodiment, the product design information of the board under test may include a Bill of Materials (BOM), a netlist, and component description information. The BOM records the manufacturing material information for the board under test, including components and their connected pins. The netlist records the network connections between component pins. The component description information may include a symbol table, component classification information, and functional descriptions of the components extracted from component datasheets. For example, the symbol table records the component code, all pins of the component, and pin names. The component classification information indicates the category to which the component belongs, the name of that category, and a functional description of that category. The component datasheet records the functional descriptions of the components.

[0033] Therefore, each pin in the board under test and the components it connects to can be determined based on the BOM (Bill of Materials). For each pin, the network to which the pin is connected can be determined from the netlist. The description information of each component is extracted from the component description information. A record for each pin in the board under test is generated through a join table lookup. Specifically, the record includes the description information of the board under test, the description information of the pin, the description information of the network to which the pin is connected, and the description information of the component to which the pin is connected.

[0034] Based on the records for each pin, a trained model can predict the test item corresponding to each pin on the board under test. This test item can include a test category and test sub-items; the same test category can include multiple test sub-items.

[0035] It should be noted that if multiple pins correspond to the same test item, it indicates that the test item is a functional test of the module composed of the components and networks connected to those multiple pins.

[0036] In the above embodiments, the record for each pin includes the pin's description information and the description information of the components and networks it is connected to. However, in practice, the applicant has found that relying solely on the description information of the components and networks directly connected to the pin is insufficient for the model to fully grasp the functional role of the pin in the overall circuit. To improve the accuracy of the model in designing test items, the description information of adjacent objects within the same connectivity domain as the pin and the description information of adjacent pins of those adjacent objects can be further introduced into the pin's record. This allows the model to more accurately infer the function it performs in the entire electrical path by associating the context information of the pin with other components and networks within its connectivity domain, thereby further improving the accuracy of test item design.

[0037] For example, for each pin, adjacent objects within the same connectivity domain as that pin can be identified from the component connectivity graph. These adjacent objects include networks and components. Description information of the identified adjacent objects and description information of the adjacent pins connected to those adjacent objects are determined and added to the record for that pin.

[0038] A component connectivity diagram is a topology diagram that describes all components on a single board and their electrical connections. A pin of any component on the board is defined as a node. This component has multiple pins, and these pins are connected via a network.

[0039] The network description information can include the network name, and the component description information can include the component category, component name, and component function description. The adjacent pin description information can include the pin name and pin number.

[0040] A connected component is a group of nodes that are directly or indirectly connected through a network. For example, pin 11 of component 1 is connected to pin 21 of component 2 through network a, and pin 22 of component 2 is also connected to pin 31 of component 3 through the same network a. Therefore, for pin 11 of component 1, its adjacent objects within the same connected component can be determined as component 2, component 3, and network a. The adjacent pins 21, 22, and 31 of component 2 are also connected to it.

[0041] For the identified adjacent objects, determine the description information of these adjacent objects and the description information of the adjacent pins connected to the adjacent objects, and add them to the record of pin 11.

[0042] In one embodiment, for each pin, when identifying adjacent objects within the same connected component in the component connectivity graph, the graph structure of the connected component can be converted into a tree structure. Using the pin as the root node, adjacent objects adjacent to the pin are searched. It is determined whether the adjacent objects meet the addition criteria. If the addition criteria are met, the currently searched adjacent objects and their corresponding adjacent pins are added to the search results set. The search stops if a network from a preset network set or a component from a first preset component set is found; or if the number of added adjacent objects exceeds a preset number.

[0043] The search method can be breadth-first search, but other search algorithms can also be used. This specification does not impose any restrictions on this.

[0044] The search results collection can store the identifiers of adjacent objects and the adjacent pins used to connect adjacent objects in the connected domain.

[0045] In one embodiment, when determining whether an adjacent object meets the addition conditions, if the currently searched component does not belong to the components in the second preset component set and has not been added to the search results set, then the component is determined to meet the addition conditions.

[0046] For example, the components in the second preset component set may include capacitors, resistors, diodes, fuses, inductors, transistors, switches, and transformers.

[0047] For example, the networks in the preset network set may include networks that conform to a specific naming rule. For instance, the preset network set may include networks such as VCC, VDD, VCC_, VDD_, GND, P3V3_, VIN_12V, FAN_12V, VDDH_3V3, 3V3_PG, 1V1_PG, VDDL_1V, VIN, VOUT, DVDD, SVDD, AGND, PS4V, and 12V.

[0048] For example, the first preset set of components may include components of the following types: integrated circuits, connectors, composite identifiers, jumpers or jumper sockets, motors or instruments, crystals or oscillators.

[0049] For example, the preset quantity can be set to 5.

[0050] In one embodiment, the model predicting the test item corresponding to the record of each pin can be trained in the following manner: The model is trained based on a labeled dataset. The labeled dataset includes records of pins on at least one board as input data, and the test item corresponding to each pin as a label.

[0051] Identify erroneous predictions from the model's predictions, and for each erroneous prediction, sample the records of several corresponding pins as input data to retrain the model.

[0052] like Figure 2 As shown, the training process can be divided into two stages: pre-training and fine-tuning. In the pre-training stage, a large amount of labeled dataset can be used to train the model. Once the model's prediction accuracy meets the requirements for deployment, the labeled dataset generated from newly added cases can be input into the model, and labeled data can be sampled from the model's incorrect predictions. The model can then be retrained using this labeled data. The sampling method can involve dividing the incorrect predictions into different test items, and selecting one labeled data point for each test item.

[0053] In this embodiment, the active sampling strategy based on error prediction can specifically enrich the model's understanding of uncommon pins and fill knowledge gaps.

[0054] To fill in the missing information and improve the robustness and scalability of the model, this solution establishes a knowledge base.

[0055] In one embodiment, chip data is acquired, and the recorded functional information of the chip is extracted from the chip data. Corresponding pin-level test cases are generated based on the functional test cases, and the pin-level test cases are represented by the records and test items for each pin. The functional information and pin-level test cases are input into a knowledge base, which is used to enhance the model's reasoning ability.

[0056] For example, existing test lists record test items corresponding to each function. In this solution, test items are recorded for each pin. So, assuming function A, the functional modules implementing function A include component 1, component 2, and component 3, as well as pins 11 and 12 of component 1, pin 21 of component 2, and pin 31 of component 3, and the network within the functional module. Records for each pin can correspond to the same test item. This solution does not restrict the way test items corresponding to each function are broken down into test items corresponding to each pin. Different functional test cases may describe the same test item differently; these different descriptions can be standardized into a single description. For example, clustering can be used to find test items with different descriptions but actually the same test item.

[0057] For examples of the application of knowledge bases and knowledge enhancement technologies in this solution, please refer to [link / reference]. Figure 3 .like Figure 3As shown, knowledge sources can include relevant information about components collected online, historical test cases, and components excluded from model prediction. In terms of data processing, multimodal processing tools can be used to integrate and clean the data. For example, knowledge graph technology can be used to extract structured information, build vector indexes, and complete missing component information. The final knowledge base can include a knowledge graph, a database, and vector indexes. During the model inference stage, historical test item retrieval and matching can be performed based on the DFT experience database, component attribute knowledge can be enhanced through the component database, and existing knowledge can be searched and correlated through the knowledge graph for multi-granularity value completion, error correction, and policy generation.

[0058] In one embodiment, such as Figure 4 As shown, a practical example is provided. Suppose the user's business goal is to generate corresponding test items for each pin of board A. In a real-world application scenario, a page can be provided to the user with input boxes for uploading BOM (Bill of Materials) and netlists. The user can input the BOM and netlist files into these input boxes to submit them to the backend. The backend can parse the BOM and netlist files to obtain records `net_list` (containing the networks connected to the pins) and `BOM_list` (containing the pins and their connected components). By performing a join query between `net_list`, `BOM_list`, and basic data tables (e.g., symbol tables, component classification information, and functional descriptions of components extracted from component manuals), a record for each pin can be obtained. This record can include the description information of the board under test, the pin's description, the description information of the network connected to the pin, and the description information of the component connected to the pin. Furthermore, the description information of any adjacent objects found and the description information of the adjacent pins connected to those adjacent objects can also be added to the pin's record.

[0059] Ultimately, the recorded content for each pin can specifically include {board description information, description information of the component connected to the pin, description information of the network connected to the pin, pin description information, description information of each adjacent object in the adjacent object set, and description information of the adjacent pins}. Specifically, the board description information can include the board's identifier, the identifier of the device to which the board resides, and the tag number of the device to which the board resides. The component description information can include the component's identifier, component type, functional description information of the component type, and functional description information of the component. The pin description information can include the pin's tag number and pin name. The description information of each adjacent object in the adjacent object set and the description information of the adjacent pins can include {the adjacent object's functional description, the adjacent object's name, the adjacent object's tag number, the adjacent object's type, the tag number of the adjacent pin connected to the adjacent object, and the adjacent pin's identifier}.

[0060] In step 2, the pin records generated in step 1 can be input into the model. The model predicts the test items corresponding to each pin, and the records and test items for each pin are then entered into the database after expert review. If there are new records for a new board, they can also be standardized and entered into the database.

[0061] Corresponding to the embodiments of the foregoing methods, this specification also provides embodiments of the apparatus and the terminal to which it is applied.

[0062] Figure 5 This is a schematic diagram illustrating the structure of an electronic device according to an exemplary embodiment. Figure 5 As shown, at the hardware level, the electronic device 500 includes a processor 502, an internal bus 504, a network interface 506, memory 508, and non-volatile memory 510, and may also include other hardware required for business operations. One or more embodiments of this specification can be implemented in software, for example, the processor 502 reads the corresponding computer program from the non-volatile memory 510 into memory 508 and then runs it. Of course, in addition to software implementation, one or more embodiments of this specification do not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution subject of the following processing flow is not limited to each logic module, but can also be hardware or logic devices.

[0063] Figure 6 This is a block diagram illustrating a hardware test item generation apparatus according to an exemplary embodiment of this specification. Figure 6 As shown, this device can be applied to, for example Figure 5 The electronic device 500 shown implements the technical solution of this specification. The device includes: The pin record generation module 602 is used to generate a record for each pin of the board under test based on the product design information of the board under test. The record includes the description information of the pin and the description information of the components and networks connected to it.

[0064] The test item prediction module 604 is used to predict the test item corresponding to each pin of the board under test based on the record of each pin and through a trained model.

[0065] Optionally, the product design information includes a BOM (Bill of Materials), a netlist, and component description information. The pin record generation module 602 is specifically used to determine each pin in the board under test and the components connected to it based on the BOM; for each pin, determine the network connected to the pin from the netlist; extract the description information of each component from the component description information; and generate a record for each pin in the board under test. The record specifically includes the description information of the board under test, the description information of the pin, the description information of the network connected to the pin, and the description information of the component connected to the pin.

[0066] Optionally, the pin record generation module 602 is further configured to, for each pin, identify adjacent objects in the same connectivity domain as the pin from the component connectivity graph, the adjacent objects including networks and components; determine the description information of the identified adjacent objects and the description information of the adjacent pins connected to the adjacent objects, and add them to the record of the pin.

[0067] Optionally, the pin record generation module 602 is further configured to convert the graph structure of the connected component into a tree structure, using the pin as the root node, search for adjacent objects adjacent to the pin, determine whether the adjacent objects meet the addition conditions, and add the currently searched adjacent objects and their corresponding adjacent pins to the search results set if the addition conditions are met; stop searching if a network in the preset network set or a component in the first preset component set is found; or stop searching if the number of added adjacent objects is greater than a preset number.

[0068] Optionally, the pin record generation module 602 is further configured to determine that the component meets the addition conditions if the currently searched component does not belong to the second preset component set and has not been added to the search results set.

[0069] Optionally, the model is obtained by training the model as follows: training the model based on a labeled dataset; wherein the labeled dataset includes records of pins on at least one board as input data, and test items corresponding to each pin as labels; identifying erroneous prediction results from the model's prediction results, and sampling records of several corresponding pins as input data for the erroneous prediction results, and retraining the model.

[0070] Optionally, the device further includes a knowledge base construction module, used to acquire chip data and extract the recorded chip functional information from the chip data; generate corresponding pin-level test cases based on functional test cases, wherein the pin-level test cases are represented by records and test items for each pin; input the functional information and the pin-level test cases into the knowledge base; the knowledge base is used to enhance the reasoning ability of the model.

[0071] The specific implementation process of the functions and roles of each module in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0072] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0073] This specification also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for generating test items for any of the aforementioned hardware provided in this application.

[0074] Specifically, computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0075] This specification also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the method for generating test items for any of the aforementioned hardware.

Claims

1. A method of generating a test item of hardware, characterized by, The method comprises: generating a record of each pin in the single board to be tested based on product design information of the single board to be tested, the record comprising description information of the pin and description information of components and networks connected to the pin; predicting, based on the record of each pin, a test item corresponding to each pin of the single board to be tested by a trained model.

2. The method of claim 1, wherein, The product design information comprises a BOM table, a netlist and component description information, and the generating of the record of each pin in the single board to be tested based on the product design information of the single board to be tested comprises: determining each pin in the single board to be tested and components connected to the pin based on the BOM table; for each pin, determining a network connected to the pin from the netlist; extracting description information of each component from the component description information; generating the record of each pin in the single board to be tested; wherein the record specifically comprises description information of the single board to be tested, description information of the pin, description information of the network connected to the pin and description information of the components connected to the pin.

3. The method of claim 1, wherein, The method further comprises: for each pin, identifying, from a component connectivity graph, an adjacent object in the same connectivity domain as the pin, the adjacent object comprising a network and a component; determining description information of the identified adjacent object and description information of an adjacent pin connected to the adjacent object, and adding the information to the record of the pin.

4. The method of claim 3, wherein, The identifying, for each pin, of the adjacent object in the same connectivity domain as the pin from the component connectivity graph comprises: converting a graph structure of the connectivity domain into a tree structure, taking the pin as a root node, searching for an adjacent object adjacent to the pin, determining whether the adjacent object meets an adding condition, and adding the adjacent object and an adjacent pin corresponding to the adjacent object to a search result set in the case where the adjacent object meets the adding condition; stopping the search in the case where a network in a preset network set or a component in a first preset component set is searched; or stopping the search in the case where a number of added adjacent objects is greater than a preset number.

5. The method of claim 4, wherein, The determining of whether the adjacent object meets the adding condition comprises: if a currently searched component does not belong to a component in a second preset component set and is not added to the search result set, determining that the component meets the adding condition.

6. The method of claim 1, wherein, The model is obtained by a training method as follows: training the model based on a labeled data set; wherein the labeled data set comprises records of pins on at least one single board as input data, and a test item corresponding to each pin as a label; determining an incorrect prediction result from a prediction result of the model, and retraining the model by sampling records of a plurality of pins corresponding to the incorrect prediction result as input data.

7. The method of claim 6, wherein, The method further comprises: obtaining chip data, and extracting functional information of a chip recorded in the chip data; generating a pin-level test case based on a functional test case, the pin-level test case being represented by the record of each pin and the test item; inputting the function information and the pin-level test cases into a knowledge base; the knowledge base is used to enhance inference ability of the model.

8. A test item generation apparatus of hardware, characterized by comprising: The device comprises: a pin record generation module configured to generate a record of each pin in a single board to be tested based on product design information of the single board to be tested, the record comprising description information of the pin and description information of a component and a network connected to the pin; a test item prediction module configured to predict a test item corresponding to each pin of the single board to be tested respectively based on the record of each pin by using a trained model.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the steps of the method of any one of claims 1-7 when executing the program.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the steps of the method of any one of claims 1-7.

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