Hard disk lighting control method, mainboard, server and medium

Abstract

The invention provides a lighting control method of a hard disk, a mainboard, a server and a medium. According to the embodiment of the invention, the SGPIO lighting signals at the mainboard end are uniformly converted into the first format which is the same as that of the RAID card, each new lighting signal is ensured to completely contain the data segment of the hard disk controlled by the corresponding SlimSAS interface, the data source judgment or format conversion does not need to be carried out when the backboard is analyzed, the analysis mode is simplified, and the analysis efficiency is improved. Therefore, the universality of the backboard is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method for controlling the LEDs of a hard disk, a motherboard, a server, and media. Background Technology

[0002] In traditional servers, the PCH chip (integrated southbridge chip) is the data source for generating the hard drive LED signals on the motherboard. The PCH chip sends SGPIO LED signals via the SGPIO (Serial General Purpose Input / Output) bus. These signals are transmitted directly to the hard drive backplane through a dedicated interface, where the control chip on the backplane parses them and executes the corresponding LED operation. RAID (Redundant Array of Independent Disks) cards, as independent storage controllers, also have the ability to send LED signals to the backplane. However, the signal data format they use differs from that of the PCH chip.

[0003] Faced with situations involving different signal sources and inconsistent data formats, the backplane control chip first needs to accurately determine whether the received LED signal originates from the motherboard PCH chip or the RAID card. This determination process typically requires additional pins for signal source identification. After identifying the signal source, the backplane also needs to employ different parsing strategies for different LED signal formats to ensure correct control of the corresponding hard drive status LEDs.

[0004] Each backplane requires customized development for the signal source configuration and hard drive layout of a specific server project. When the motherboard design changes, the backplane often cannot be directly reused and its signal processing logic needs to be redesigned or modified. Summary of the Invention

[0005] In view of this, the present disclosure provides a method for controlling the LEDs of a hard drive, a motherboard, a server, and media to address the shortcomings of related technologies.

[0006] According to a first aspect of the present invention, a method for controlling the illumination of a hard disk is provided, wherein the hard disk is placed on the backplane of a server; the server further includes a motherboard and a RAID card, the motherboard is equipped with a programmable logic chip and at least one SlimSAS interface, each SlimSAS interface being bound to a group of hard disks; each group of hard disks includes at least one hard disk; the RAID card is used to send an illumination signal of a first format to the backplane; the illumination control method is applied to the programmable logic chip, comprising: Obtain the SGPIO LED signal from the motherboard; The SGPIO LED signal is parsed into several data segments, and each data segment is used to control the status LED of one of the hard drives. The data segments corresponding to the same SlimSAS interface are grouped together as a data segment group, and the data segments in the data segment group are combined into a new lighting signal, wherein the new lighting signal is in the first format. Each new LED signal is sent to the backplane via the corresponding SlimSAS interface to control the status LEDs of each hard drive in the hard drive group bound to that SlimSAS interface.

[0007] According to a second aspect of the present invention, a motherboard is provided, the motherboard having a programmable logic chip and at least one SlimSAS interface, the programmable logic chip being used to execute the lighting control method described in the first aspect.

[0008] According to a third aspect of the present invention, a server is provided, including a backplane, a motherboard, and a RAID card; the backplane is provided with a hard disk; the motherboard is equipped with a programmable logic chip; The RAID card is used to send a first-format LED signal to the backplane; The programmable logic chip is used in the lighting control method described in the first aspect to send a new lighting signal of the first format to the backplane. The backplane is used to control the status lights of the hard drive based on the new light signal of the first format.

[0009] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, it implements the lighting control method described in the first aspect.

[0010] This embodiment converts the SGPIO LED signals on the motherboard into the same first format as the RAID card, and ensures that each new LED signal fully contains the data segment of the hard drive controlled by its corresponding SlimSAS interface. The backplane does not need to perform data source judgment or format conversion during parsing, and the parsing method is simplified, thereby improving the reusability of the backplane. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a server architecture illustrated by way of example according to this specification; Figure 2 This is a schematic diagram illustrating a hard disk light control method according to an embodiment of this specification; Figure 3 This is a schematic diagram illustrating an example of a server application according to this specification; Figure 4 This is a schematic diagram illustrating another example of a server application according to this specification; Figure 5This is a schematic diagram of a motherboard according to an embodiment of this specification; Figure 6 This is a schematic diagram illustrating a server according to an embodiment of this specification. Detailed Implementation

[0012] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0013] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0014] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0015] In traditional server implementations, the PCH chip (integrated southbridge chip) is the data source for generating the hard drive LED signals on the motherboard. The PCH chip sends LED control signals via the SGPIO (Serial General Purpose Input / Output) bus, hereinafter referred to as SGPIO LED signals. These LED control signals follow a specific data encapsulation format; a complete signal data frame contains twenty-four bits. Following the standard of three bits controlling one hard drive, a single signal set can completely control the status indication of eight hard drives. These signals are transmitted directly to the hard drive backplane via a dedicated interface, where the control chip on the backplane parses them and executes the corresponding LED operation.

[0016] RAID (Redundant Array of Independent Disks) cards, as independent storage controllers, also have the ability to send LED signals to the backplane. However, the signal data format they use differs from that of the PCH chip. RAID card LED signal data packets typically contain twelve bits, and following the same encoding rules, a single signal can only control the status indication of four hard drives. This format mismatch leads to complexity during server integration.

[0017] In application scenarios with multiple signal sources and inconsistent data formats, traditional solutions require adaptation processing at the hard drive backplane. The backplane's control chip first needs to accurately determine whether the received LED signal comes from the motherboard PCH chip or the RAID card. This determination process usually requires additional general-purpose input / output pins for signal source identification. After identifying the signal source, the backplane needs to employ different parsing strategies for different LED signal formats to ensure they are correctly mapped to the corresponding hard drive status LEDs.

[0018] This signal adaptation mechanism leads to complex backplane hardware design and logic development. Each backplane product requires customized development for the signal source configuration and hard drive layout of a specific server project. When the motherboard design changes, the backplane often cannot be directly reused and must be redesigned or at least its signal processing logic modified. This lack of universality in design not only prolongs the product development cycle and increases R&D costs, but also limits the optimization and rapid iteration efficiency of servers.

[0019] Figure 1 This is a schematic diagram of a server architecture exemplarily illustrated in this specification. The server includes a backplane 11, a motherboard 10, and a RAID card 12. The hard drives are mounted on the server's backplane 11 and can be SAS or SATA hard drives. The backplane 11 provides physical support and power supply for the hard drives and integrates a chip responsible for parsing the indicator lights and controlling the hard drive status lights accordingly. Specifically, the hard drive status lights are visual indicators mounted on the backplane 11 corresponding to each hard drive. These hard drive status lights are not controlled by the hard drives themselves but are driven by the backplane 11. A control chip 110 can be integrated on the backplane 11. This control chip 110 is responsible for receiving and parsing the indicator light command signals from the motherboard 10 or the RAID card 12. Exemplarily, the control chip 110 can be a CPLD chip or an FPGA chip.

[0020] The motherboard 10 is equipped with a PCH chip 100 and a programmable logic chip 101. The PCH chip 100 is used to generate raw hard disk status control commands, i.e., SGPIO LED signals. The SGPIO LED signals are sent to the programmable logic chip 101 in the form of serial universal input / output LED signals. The programmable logic chip 101 acts as the signal processing center on the motherboard 10, performing specific processing on the SGPIO LED signals to generate new LED signals, and sending the new LED signals to the backplane 11. For example, the programmable logic chip 101 can be a CPLD chip or an FPGA chip.

[0021] The motherboard 10 is equipped with at least one SlimSAS interface, and each SlimSAS interface is bound to a group of hard drives, with each group of hard drives containing at least one hard drive.

[0022] The backplane 11 is equipped with at least two SlimSAS interfaces, at least one of which is used to connect to a SlimSAS interface on the motherboard 10, and at least the other is used to connect to a SlimSAS interface on the RAID card 12. RAID card 12, as a storage control unit independent of motherboard 10, also has the function of managing hard drive status indicator lights. It sends indicator signals directly to backplane 11 via its SlimSAS interface. This signal has a specific data encapsulation format, defined as the first format in this manual. This format differs from the signal format generated by PCH chip 100.

[0023] Based on the above server architecture, the hard drive lighting control method disclosed in the embodiments of this specification aims to solve the above problems. Figure 2 This is a schematic diagram illustrating an exemplary lamp control method for a hard disk in this specification. The lamp control method is applied to the programmable logic chip and includes: S200: Obtain the SGPIO LED signal from the motherboard. The SGPIO LED signal includes at least one data segment, each data segment used to control the status LED of one of the hard drives, such as a positioning LED or activity indicator. The programmable logic chip obtains the SGPIO LED signal from the PCH chip. The SGPIO LED signal contains a data sequence for controlling the status LEDs of multiple hard drives, which indicate the activity status, positioning information, or fault conditions of the hard drives.

[0024] For example, a data segment can consist of 3 bits. Different combinations of these 3 bits are used to indicate the off, constant on, slow flashing, fast flashing, or other states of one or more status lights on the corresponding hard drive. In one embodiment, the hard drive's status lights include a monochrome light and a dual-color light. One bit of data in the data segment is used to control the monochrome light, and the other two bits are used to control the dual-color light. It is understood that the embodiments in this specification do not require specific limitations on how each data segment controls the hard drive's status lights.

[0025] S202: Parse the SGPIO LED signal into several data segments, each of which is used to control the status LED of one of the hard drives.

[0026] The programmable logic chip (PLC) parses the acquired SGPIO LED signal into several independent data segments. The parsing process is based on the data frame structure of the SGPIO LED signal, identifying each data segment and ensuring that each segment corresponds one-to-one with the target hard drive. This segment parsing allows the PLC to extract independent control information for each hard drive, laying the foundation for subsequent signal reassembly.

[0027] S204: Group the data segments corresponding to the same SlimSAS interface into a data segment group, and combine the data segments in the data segment group into a new lighting signal. The new lighting signal is in the first format.

[0028] After parsing the data segments, the programmable logic chip (PLC) groups the data segments corresponding to the same SlimSAS interface into a data segment group based on the binding relationship between each SlimSAS interface and a group of hard drives. Each SlimSAS interface is bound to a specific group of hard drives during the server design phase, and this binding relationship clearly defines all the hard drives that the interface is responsible for controlling. Based on this established binding relationship, the PLC selects the necessary data segments from all parsed data segments to control each hard drive in the bound hard drive group. For example, one SlimSAS interface can control four hard drives and their status lights. For instance, the first SlimSAS interface can be configured to control "Hard Drive 0, Hard Drive 1, Hard Drive 2, Hard Drive 3" on the backplane; the second SlimSAS interface can control "Hard Drive 4, Hard Drive 5, Hard Drive 6, Hard Drive 7" on the backplane.

[0029] It should be noted that the embodiments in this specification do not limit the number of backplanes. The motherboard in the server can connect to one or more backplanes. However, it should be noted that one SlimSAS interface on the motherboard can only connect to one SlimSAS interface on the backplane at the same time. That is, one SlimSAS interface cannot control multiple hard drives from different backplanes at the same time.

[0030] Subsequently, the programmable logic chip combines all data segments belonging to the same SlimSAS interface data segment group to generate a new LED signal. A key characteristic of this new LED signal is that its data encapsulation format is the same as the LED signal format sent by the RAID card to the backplane, i.e., the first format. For example, the first format refers to the data size of each frame of the LED signal sent by the RAID card, such as 12 bits; however, this specification does not impose any limitation on this.

[0031] Since the data segment group is constructed entirely based on the binding relationship between the SlimSAS interface and the hard drive group, the generated new indicator signal must contain all the data segments required to control the status lights of each hard drive in the hard drive group bound to this interface. This allows the new indicator signal to independently meet the indicator control requirements of the corresponding hard drive group.

[0032] For example, in a practical application scenario, the PCH chip on the motherboard needs to manage the status indicators of eight hard drives. It generates a set of SGPIO LED signals containing eight data segments. In this signal frame consisting of eight data segments, the first data segment is dedicated to controlling the status LED of the first hard drive, the second data segment is dedicated to controlling the status LED of the second hard drive, and so on, until the eighth data segment is dedicated to controlling the status LED of the eighth hard drive. This one-to-one correspondence ensures that each hard drive receives its own dedicated control command. It should be noted that the embodiments in this specification do not require a specific limit on the number of data segments included in each SGPIO LED signal, and can be adjusted according to actual business needs.

[0033] Continuing with the aforementioned application scenario, it's worth further elaborating that these eight data segments are transmitted serially in a specific bit order within the SGPIO LED signal. The hard drive controlled by the bit order of each data segment can be determined through a predefined mapping relationship. When the programmable logic chip parses these eight data segments, it regroups them according to the pre-established binding relationship between the SlimSAS interface and the hard drive group. For example, in a configuration with two SlimSAS interfaces, the first four data segments might be assigned to the hard drive group corresponding to the first SlimSAS interface, while the latter four data segments are assigned to the hard drive group corresponding to the second SlimSAS interface. Furthermore, not all eight data segments need to have a mapping relationship with a hard drive. For instance, in a configuration with two SlimSAS interfaces, four data segments might be assigned to the hard drive group corresponding to the first SlimSAS interface, two data segments to the hard drive group corresponding to the second SlimSAS interface, and the remaining two data segments, which have no mapping relationship with the hard drive, can be considered invalid data and discarded during processing.

[0034] In the example above, each SlimSAS interface is used to send 4 data segments. This is because each frame of the LED signal in the first format sent by the RAID card in this example includes 4 data segments. It can be understood that when the first format includes a different number of data segments, the number of data segments sent by the SlimSAS interface also needs to be adjusted accordingly to maintain format consistency.

[0035] Continuing with the example of each LED signal frame in the first format comprising four data segments, each SlimSAS interface needs to send four data segments, but the number of hard drives bound to the SlimSAS interface does not necessarily have to be four. For example, if a SlimSAS interface is used to transmit two data segments controlling SATA5 and SATA6, in this case, the programmable logic chip will perform the following operations when generating a new LED signal: First, it filters out the two data segments controlling SATA5 and SATA6 from the corresponding SGPIO LED signals. Then, to meet the first format's requirement for the number of data segments, the chip can generate two additional data segments, or use invalid data from the aforementioned SGPIO LED signal as additional data segments. The two valid data segments and the two additional data segments are combined to form a new LED signal containing four data segments. This new LED signal conforms to the first format specification in terms of data volume and can be normally received and parsed by the backplane. Since these additional data segments do not have corresponding hard drives, the backplane will treat them as invalid data after receiving the new LED signal.

[0036] S206: Send each new LED signal to the backplane through the corresponding SlimSAS interface to control the status LEDs of each hard drive in the hard drive group bound to the SlimSAS interface.

[0037] Finally, the programmable logic chip sends each newly generated LED signal to the server's hard drive backplane via its corresponding SlimSAS interface. Each new LED signal is transmitted through its bound SlimSAS interface, utilizing the interface's low-speed sideband signal lines for communication. When the backplane receives a new LED signal, its internal control logic directly parses the signal based on a unified first format. Since each new LED signal already contains all the information needed to control all hard drives in its corresponding hard drive group, the backplane does not need to determine the signal source or perform complex format conversions and data mappings to directly drive the status lights of each hard drive in the corresponding hard drive group.

[0038] It should be noted that the SlimSAS interface mentioned above refers to the SlimSAS interface on the motherboard. A SlimSAS interface is also available on the backplane. This transmission process occurs through a communication channel formed by the SlimSAS interfaces on the motherboard and the backplane. The low-speed sideband signal line within the SlimSAS interface carries the new LED signal. For clarity, unless otherwise specified, the SlimSAS interface mentioned below also refers to the SlimSAS interface on the motherboard.

[0039] It should be noted that the SGPIO LED activation signals acquired by the programmable logic chip and the newly generated LED activation signals can conform to the SFF-8485 protocol specification. This specification requires that both the SGPIO LED activation signals and the new LED activation signals be a set of pulse signals including a clock signal, a load signal, and a data output signal. During transmission, the programmable logic chip follows the timing requirements of this protocol. Under the synchronization of the clock signal, it sequentially drives the serial data bits representing the control information of each hard disk status LED onto the data output signal line, while using the high and low level changes of the load signal to indicate the start and end of the valid data cycle on the data output signal line.

[0040] When the backplane receives the new LED signal through its SlimSAS interface, its internal control chip immediately parses the signal. Since the new LED signal has been standardized to the same first format as the signal sent by the RAID card, the backplane's control chip does not need additional GPIO signals to distinguish whether the signal comes from the motherboard or the RAID card; that is, the backplane can use a fixed parsing logic for processing. Based on the foregoing, the correspondence between the motherboard's SlimSAS interface and the hard drive is predefined, and there is a one-to-one correspondence between the motherboard's SlimSAS interface and the backplane's SlimSAS interface. Therefore, the backplane, by parsing the various data segments included in the new LED signal, can control the corresponding hard drive.

[0041] This embodiment converts the SGPIO LED signals on the motherboard into the same first format as the RAID card, and ensures that each new LED signal completely contains the data segments of all hard drives controlled by its corresponding SlimSAS interface. The backplane does not need to perform data source judgment or format conversion during parsing, and the parsing method is simplified, thereby improving the versatility and reusability of the backplane and ensuring the reliability of LED control.

[0042] As one or more embodiments of the present invention, the step of obtaining the SGPIO LED signal of the motherboard includes: The first SGPIO LED signal of the motherboard is acquired during the first time period. The second SGPIO LED signal of the motherboard is acquired during the second time period; wherein the first SGPIO LED signal and the second SGPIO LED signal are used to control the status lights of different hard drives.

[0043] The programmable logic chip (PLC) acquires the first SGPIO LED signal from the motherboard during a first time period. This signal contains data segments used to control a specific set of hard drive status LEDs. Subsequently, during a second time period, the PLC acquires the second SGPIO LED signal from the motherboard. This second signal is used to control a different set of hard drive status LEDs. The two signals are acquired alternately or sequentially in time, ensuring that the control information is completely captured.

[0044] Specifically, both the first and second SGPIO LED signals are based on the SATA protocol. SATA (Serial Advanced Technology Attachment) is a widely used serial communication standard for connecting hard drives and motherboards.

[0045] The PCH chip integrates multiple SATA controllers, which control the corresponding SATA interfaces on the backplane. Each SATA interface on the backplane can connect to one hard drive. These SATA interfaces can be divided into two groups, referred to as the first group and the second group.

[0046] The purpose of grouping SATA interfaces is to meet the expanding needs of server systems for the number of hard drive connections. The first group of SATA interfaces provides basic connectivity, while the second group is designed to expand the number of hard drive connections on the server, aiming to increase the number of hard drives that can be connected.

[0047] These two SATA interfaces are physically and logically independent control units. The PCH chip generates two independent SGPIO LED signals for each, which are then sent in parallel to the programmable logic chip on the motherboard. The LED signal generated for the first SATA interface is called the first SGPIO LED signal, and the LED signal generated for the second SATA interface is called the second SGPIO LED signal, which can also be called the SSATA LED signal or extended SATA LED signal.

[0048] In early ICX platforms, the first SATA interface was often simply called SATA, and the second SATA interface was often called SSATA. The first SATA interface supported 8 ports, while the second SATA interface (SSATA) supported 6 ports. In the EGS platform, a naming convention of SATA0, SATA1, SATA2, etc., was adopted, with all interfaces maintaining the same transmission rate. Although the number of supported hard drive ports may differ, each SATA interface supports DMA operations through its corresponding controller, and the generated SGPIO LED signal data frames are all 24 bits. This provides the fundamental data format prerequisite for unified parsing, filtering, and reassembly within the programmable logic chip in this invention.

[0049] The first SGPIO LED signal carries the status LED control information for all hard drives connected to the first set of SATA interfaces, while the second SGPIO LED signal specifically corresponds to the status of the hard drives connected to the second set of SATA interfaces. This separate signal generation mechanism can comprehensively reflect the status information of all hard drives in the server, but it also brings the challenge of dispersed signal sources.

[0050] Since each SlimSAS interface is bound to a set of hard drives, and the hard drives controlled by each data segment included in the first and second SGPIO indicator signals are pre-defined, the first and second SGPIO indicator signals each correspond to one or more specific SlimSAS interfaces. For example, it can be configured that a portion of the data in the first SGPIO indicator signal is sent through the first SlimSAS interface, and another portion is sent through the second SlimSAS interface; similarly, a portion of the data in the second SGPIO indicator signal can be sent through the third SlimSAS interface, and another portion through the fourth SlimSAS interface.

[0051] Based on the premise that the SGPIO LED indicator signal is either the first SGPIO LED indicator signal or the second SGPIO LED indicator signal, the traditional method of processing LED indicator signals from different protocols has significant limitations. In the traditional method, after the PCH generates the first and second SGPIO LED indicator signals, they are transmitted to the backplane separately through different SlimSAS interfaces. That is, the first and second SGPIO LED indicator signals remain independent during transmission, making it impossible to flexibly combine the data segments actually sent by each SlimSAS interface.

[0052] This fixed processing method restricts the motherboard routing. Since the first SGPIO LED signal and the second SGPIO LED signal cannot be flexibly combined, the signal routing between the PCH chip and the SlimSAS interface follows the grouping of signals that the SlimSAS interface can send. That is, there are only two SlimSAS interfaces on the motherboard: one for sending the first SGPIO LED signal and the other for sending the second SGPIO LED signal. The routing may need to take long detours to meet the interface grouping requirements, which limits the flexibility of hardware design.

[0053] In the embodiments of this specification, combining the data segments in the data segment group into a new lighting signal specifically includes at least one of the following steps: Several data segments targeting the same SlimSAS interface are selected from the first SGPIO LED signal and combined into a first new LED signal. Several data segments targeting the same SlimSAS interface are selected from the second SGPIO LED signal and combined into a second new LED signal. Several data segments targeting the same SlimSAS interface are selected from the first SGPIO lighting signal and the second SGPIO lighting signal, and combined into a third new lighting signal.

[0054] This specification describes embodiments that categorize data segments into first data segments and second data segments, and the formation of new LED signals includes three specific types. The first type is a first new LED signal obtained by combining several first data segments. This signal contains only data segments from the first SGPIO LED signal and is suitable for controlling hard drive groups composed entirely of hard drives corresponding to the first set of SATA interfaces. The second type is a second new LED signal obtained by combining several second data segments. This signal contains only data segments from the second SGPIO LED signal and is suitable for controlling hard drive groups composed entirely of hard drives corresponding to the second set of SATA interfaces. The third type is a third new LED signal generated by mixing and combining several first data segments and several second data segments. This signal contains data segments from both the first and second SGPIO LED signals and is suitable for controlling hard drive groups composed of hard drives corresponding to a mixture of two sets of SATA interfaces.

[0055] This new combination of LED signals allows programmable logic chips to flexibly adapt to different SlimSAS interface configurations. Each SlimSAS interface is bound to a specific hard drive group, which may originate entirely from the first SATA interface group, entirely from the second SATA interface group, or a mixture of both groups. By parsing the SGPIO LED signals and extracting the corresponding data segments, the programmable logic chip can combine the data segments into a first, second, or third new LED signal as needed, based on the actual hardware connection relationship. This means that the two independent SGPIO signals on the motherboard are no longer fixed as two isolated signal streams directly output. During hardware design, hard drives controlled by the first and second SGPIO LED signals can be arbitrarily grouped, making the wiring from the programmable logic chip to each SlimSAS interface more flexible, without worrying about LED signal incompatibility.

[0056] For example, Figure 3 This is a schematic diagram illustrating an example of a server application in this specification. The server has two backplanes, designated as a first backplane 31 and a second backplane 32. Eight hard drives are connected to both backplanes 31 and 32. The hard drives on the first backplane 31 are numbered SATA1 to SATA8, and the hard drives on the second backplane 32 are numbered SATA9 to SATA16. Hard drives SATA9 to SATA12 are controlled by LED signals from a RAID card 33.

[0057] The motherboard 30 has three SlimSAS interfaces and the following pre-set binding relationships: the first SlimSAS interface 3041 is bound to hard drives SATA1, SATA2, SATA3, and SATA4; the second SlimSAS interface 3042 is bound to hard drives SATA5, SATA6, SATA7, and SATA8; and the third SlimSAS interface 3043 is bound to hard drives SATA13, SATA14, SATA15, and SATA16.

[0058] The PCH chip 300 on the motherboard 30 generates two independent SGPIO LED signals: a first SGPIO LED signal and a second SGPIO LED signal. The first SGPIO LED signal carries data segments controlling the status LEDs for SATA1 to SATA6, while the second SGPIO LED signal carries data segments controlling the status LEDs for SATA7, SATA8, SATA13, SATA14, SATA15, and SATA16. The programmable logic chip 301 acquires these two signals in time intervals and processes them according to the aforementioned binding relationship. Based on the foregoing, the first and second SGPIO LED signals may still carry some invalid data segments; however, this explanation only addresses valid data segments, and invalid data segments are considered discarded.

[0059] After acquiring the first SGPIO LED signal in the first time period, the programmable logic chip 301 parses it to obtain multiple data segments. Based on the binding relationship of the first SlimSAS interface 3041, the chip selects four data segments specifically for controlling SATA1, SATA2, SATA3, and SATA4. Since these data segments all originate from the first SGPIO LED signal, they are directly combined into a single new LED signal. This new signal is the first new LED signal, and its data format is converted to the same first format as the RAID card 33 signal. It is then sent to the backplane via the first SlimSAS interface 3041 to control the status LEDs of the four hard drives bound to that interface.

[0060] The programmable logic chip 301 acquires the second SGPIO LED signal during the second time period. Similarly, the programmable logic chip 301 parses this signal and obtains its contained data segments. Based on the binding relationship of the third SlimSAS interface 3043, the programmable logic chip 301 filters out four data segments from the second SGPIO LED signal specifically for controlling SATA13, SATA14, SATA15, and SATA16. These data segments, all originating from the second signal, are combined into another new LED signal, namely the second new LED signal. This signal also follows the first format and is sent through the third SlimSAS interface 3043 to control its bound four hard drives.

[0061] Since the second SlimSAS interface 3042 is connected to hard drives SATA5, SATA6, SATA7, and SATA8, the control information required by the second SlimSAS interface 3042 is distributed across two SGPIO LED signals. After acquiring the two signals in time intervals, the programmable logic chip 301 needs to perform cross-filtering. From the first SGPIO LED signal, the programmable logic chip 301 filters out the data segments controlling SATA5 and SATA6; from the second SGPIO LED signal, the programmable logic chip 301 filters out the data segments controlling SATA7 and SATA8. Then, the data segments from different signal sources are combined into a unified new LED signal, namely the third new LED signal. This third new LED signal completely contains the data segments required to control all the hard drives connected to the second SlimSAS interface 3042, and is sent to the first backplane 31 through the second SlimSAS interface 3042.

[0062] As one or more embodiments of this specification, the process of assembling the third new lighting signal specifically includes: Several data segments targeting the same SlimSAS interface are selected from the first / second SGPIO LED signal received at the current moment and the second / first SGPIO LED signal received at the previous moment, and combined into the third new LED signal.

[0063] To ensure that the indicator lights are transmitted to the backplane in real time to control the hard drive status lights, when the programmable logic chip receives an SGPIO indicator light signal (e.g., the first SGPIO indicator light), it immediately combines it with the relevant data segments from another signal received and temporarily stored in the previous moment—the second SGPIO indicator light signal. Then, based on the hard drive binding relationship of the target SlimSAS interface, it performs parallel data filtering from these two signal sources belonging to different moments. It extracts the data segments corresponding to a portion of the hard drives bound to the interface from the currently received first SGPIO indicator light signal, and simultaneously extracts the data segments corresponding to another portion of the hard drives bound to the interface from the previously received second SGPIO indicator light signal.

[0064] After data filtering, the programmable logic chip combines these data segments from the current time signal and the previous time signal to generate a complete third new LED signal. This newly generated signal contains all the latest instructions needed to control all the hard drives bound to the SlimSAS interface.

[0065] Furthermore, to ensure the timeliness and accuracy of the signal, the method also includes: Save the parsed data segments as the data segments of the first / second SGPIO lamp-lighting signals received in the previous moment.

[0066] The programmable logic chip (PLC) maintains a dynamically updated record of data segments. Whenever a new SGPIO LED signal is received, the PLC overwrites the corresponding part of the updated record with the new data segment parsed from that signal. Therefore, when assembling a third new LED signal for the next transmission cycle, the PLC does not need to wait for the first and second SGPIO LED signals to arrive simultaneously. Instead, it reads all data segments from this already integrated record in high-speed line order and combines them. Thus, regardless of any differences in the transmission timing of the two signals, the PLC can continuously construct the correct LED control signal for the SlimSAS interface, which requires mixed signal sources, through this cross-time filtering and combination, thereby ensuring the continuity and reliability of LED control.

[0067] As one or more embodiments of the present invention, the SlimSAS interface includes at least one high-speed line pin, and the bonding relationship refers to the preset correspondence between the high-speed line pin of the SlimSAS interface and the hard disk.

[0068] It should be noted that the SlimSAS interface, as a composite physical port, includes high-speed line pins and low-speed sideband signal pins. The high-speed line pins are used to transmit high-speed signals between the motherboard and the hard drive backplane to perform hard drive read and write tasks. The low-speed sideband signal pins are used to transmit low-speed control signals, including SGPIO signals, and are responsible for managing hard drive status indications and other functions. These two types of pins are independent of each other and together constitute the complete functionality of the SlimSAS interface.

[0069] Based on the foregoing description, the new LED signal in the embodiments of this specification is an SGPIO signal, meaning the programmable logic chip sends the new LED signal to the SlimSAS interface and then to the backplane via a low-speed sideband signal pin, rather than via a high-speed line pin. However, the high-speed line pin can reflect the physical drive bay number on the backplane of the hard drive controlled by the SlimSAS interface. The embodiments of this specification utilize this information to determine the hard drive corresponding to the SlimSAS interface.

[0070] During the server hardware design phase, each set of high-speed pins for every SlimSAS interface on the motherboard is pre-planned to connect to a specific physical hard drive bay on the backplane. For example, a SlimSAS interface designed to connect four hard drives contains four sets of high-speed pins, each set connected to a physical hard drive bay on the backplane via a cable. Therefore, this SlimSAS interface is logically defined to control these four specific hard drives.

[0071] In traditional solutions, since all the LED signals from various sources are sent to the backplane, the backplane's control chip parses them and then determines which hard drive's status LED each data segment controls based on its position in the SGPIO LED signal. The motherboard does not need to precisely bind the SGPIO signal to the physical connection of each specific SlimSAS interface.

[0072] This embodiment, by uniformly converting the SGPIO LED signals on the motherboard to a first format, further simplifies the backplane's parsing logic and improves its reusability. It explicitly identifies the hard drive controlled by each SlimSAS interface through a pre-defined physical correspondence between its high-speed line pins and the hard drives on the backplane. This ensures that the LED signal sent by one SlimSAS interface completely covers all hard drives connected to that interface's high-speed line. Thus, regardless of the number of backplanes configured in the server or the distribution of SlimSAS cables, the LED signal carried by each cable is self-contained and complete, ensuring that every hard drive on its target backplane receives the correct status indication.

[0073] Furthermore, in order to parse and reassemble the SGPIO LED signal into a third new LED signal that conforms to the requirements of the SlimSAS interface, the specific steps for assembling the third new LED signal include: The data segments are sorted and combined according to the high-speed line order so that each data segment in the obtained third new light signal is arranged according to the order of the controllable hard drives; the high-speed line order is used to characterize the order of the high-speed line pins corresponding to each hard drive in the SlimSAS interface.

[0074] After successfully acquiring all relevant data segments, the data segments are rearranged according to the high-speed line order of their corresponding hard drives within the SlimSAS interface. The high-speed line order defines the immutable connection order between each high-speed line pin on the interface and the specific hard drive bay on the backplane. By sorting the data segments according to this order, the programmable logic chip ensures that the position of each data segment in the final generated new LED signal serial data stream strictly corresponds to the position of the hard drive it can control on the backplane. Therefore, the arrangement order of the data segments included in the third new LED signal is consistent with the physical order of the hard drives they can control and connected through the SlimSAS interface.

[0075] Because the backplane control chip can predetermine the disk bay order of each hard drive on the backplane, and the high-speed pins of the SlimSAS interface correspond one-to-one with the hard drives, this sequencing mechanism eliminates the need for complex data parsing or address mapping calculations after the backplane receives the LED signal. The backplane control chip can directly drive the status LEDs of each hard drive on the backplane according to the order of the data segments in the signal, based on its inherent hardware knowledge, such as "the high-speed pin order of this interface corresponds to hard drives 0, 1, 2, 3…", further simplifying the backplane's processing logic and improving the versatility of the backplane design.

[0076] For example, Figure 4This is a schematic diagram illustrating another server application example as exemplified in this specification. The server has a third backplane 41. The third backplane 41 has at least twelve hard drives. Six of these hard drives are controlled by data segments DATA1_1 to DATA1_6 carried by a first SGPIO indicator signal; these six hard drives are denoted as SATA1_1 to SATA1_6. The other six hard drives are controlled by data segments DATA2_1 to DATA2_6 carried by a second SGPIO indicator signal; these six hard drives are denoted as SATA2_1 to SATA2_6. Based on the foregoing description, the first and second SGPIO indicator signals may also carry some invalid data segments; however, this section only explains the valid data segments, and invalid data segments are considered to be discarded. It is understandable that the server may also have other backplanes besides the third backplane, as well as RAID cards that control other hard drives. One frame of the first SGPIO LED signal and the second SGPIO LED signal can transmit 8 data segments, i.e., 24 bits of data, respectively. However, this section only explains the processing method of DATA1_1 to DATA1_6 and DATA2_1 to DATA2_6.

[0077] The motherboard 40 has three SlimSAS interfaces with the following pre-defined bonding relationships: the four high-speed pins of the first SlimSAS interface 4041 are pre-connected to hard drives SATA1_1, SATA1_2, SATA1_3, and SATA1_4 respectively; the four high-speed pins of the second SlimSAS interface 4042 are pre-connected to hard drives SATA2_1, SATA2_2, SATA2_3, and SATA2_4 respectively; and the four high-speed pins of the third SlimSAS interface 4043 are pre-connected to hard drives SATA1_5, SATA1_6, SATA2_5, and SATA2_6 respectively.

[0078] After acquiring the first SGPIO LED signal in the first time period, the programmable logic chip 401 parses it to obtain multiple data segments. Based on the binding relationship of the first SlimSAS interface 4041, the chip selects DATA1_1, DATA1_2, DATA1_3, and DATA1_4 from these data segments. Since all these data segments originate from the first SGPIO LED signal, they are directly combined into a new LED signal and sent through the first SlimSAS interface 4041, thereby controlling the status LEDs of the four hard drives bound to this interface.

[0079] The programmable logic chip 401 acquires the second SGPIO LED signal during the second time period. Similarly, the programmable logic chip 401 parses this signal and obtains its contained data segments. Based on the binding relationship of the second SlimSAS interface 4042, the programmable logic chip 401 selects DATA2_1, DATA2_2, DATA2_3, and DATA2_4 from the second SGPIO LED signal to form a second new LED signal, which is then sent through the second SlimSAS interface 4042 to control the four hard drives it is bound to.

[0080] The control information required by the third SlimSAS interface 4043 is distributed across two SGPIO LED signals. Therefore, the programmable logic chip 401 selects the data segments controlling DATA1_5 and DATA1_6 from the first SGPIO LED signal; and selects the data segments controlling DATA2_5 and DATA2_6 from the second SGPIO LED signal. Since the four high-speed line pins of the third SlimSAS interface 4043 are pre-set to correspond to hard drives SATA1_5, SATA1_6, SATA2_5, and SATA2_6 in sequence, the programmable logic chip 401 arranges the selected data segments in this order: DATA1_5, DATA1_6, DATA2_5, and DATA2_6, thereby generating a third new LED signal. This third new LED signal completely contains the data segments required to control all the hard drives bound to the third SlimSAS interface 4043, and the order of the data segments is consistent with the order of the hard drives connected to the interface's high-speed line pins. It is then sent to the third backplane 41 through the third SlimSAS interface 4043. During the resolution process, the backplane can directly drive the status lights of the corresponding hard drives according to this fixed order, without the need for complex mapping calculations.

[0081] In one or more preferred embodiments of the present invention, the data segments in the SGPIO lighting signal are arranged in high-speed line order.

[0082] The SGPIO LED signal, emitted from the PCH chip and acquired by the programmable logic chip, contains multiple data segments within its data frame that are not arbitrarily arranged but pre-organized according to the high-speed line sequence. For example, each SlimSAS interface includes four high-speed line pins. In the SGPIO LED signal, the first data segment in the sequence corresponds to the hard drive connected to the first high-speed line pin on the first SlimSAS interface, the hard drive connected to the second high-speed line pin on the first SlimSAS interface, and so on. After arranging the four hard drives corresponding to the first SlimSAS interface, the sequence continues with the hard drive connected to the first high-speed line pin on the second SlimSAS interface, the hard drive connected to the second high-speed line pin on the second SlimSAS interface, and so on.

[0083] When a programmable logic chip receives such a signal, it can directly understand the target hard drive that each data segment intends to control based on the inherent sequence relationship within the signal, without relying on additional complex mapping tables or dynamic calculations to establish the association between the data segment and the hard drive.

[0084] Furthermore, the aforementioned embodiments ensure that the internal data segments of the input SGPIO LED signal are arranged in high-speed line order. Therefore, when generating the first or second new LED signal, the programmable logic chip does not need to perform complex parsing or reordering of the data segments. Instead, based on the position of the hard drive group currently bound to the SlimSAS interface in the global data sequence, it extracts a continuous segment from the complete SGPIO LED signal stream, with the number of segments matching the number of hard drives controlled by the interface. The order of these extracted continuous data segments naturally remains consistent with the high-speed line order. Compared to the aforementioned sorting and reorganization method for the third new LED signal, this method has lower logical complexity and also ensures the core advantage of correct parsing without backplane adaptation, achieving a balance between processing efficiency and compatibility.

[0085] Figure 5 This is a schematic diagram of a motherboard according to an embodiment of this specification. The motherboard 50 is equipped with a programmable logic chip 501 and at least one SlimSAS interface 502. The programmable logic chip 501 is used to perform the methods of any embodiment of this disclosure.

[0086] Figure 6 This is a schematic diagram illustrating a server according to an embodiment of this specification. The server 60 includes a backplane 601, a motherboard 600, and a RAID card 602; the backplane is equipped with a hard drive; the motherboard is equipped with a programmable logic chip 6001. The RAID card 602 is used to send a first-format LED signal to the backplane 601; The programmable logic chip 6001 is used to execute the method described in any embodiment of the present disclosure and send a new lamp signal in the first format to the backplane 601. The backplane 601 is used to control the status lights of the hard disk based on the new light signal of the first format.

[0087] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of any embodiment of this disclosure.

[0088] Computer-readable storage media include both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0089] The embodiments of the subject matter and functional operation described in this specification can be implemented in the following ways: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. Alternatively or additionally, the program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiving device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or combinations thereof.

[0090] The processing and logic flow described in this specification can be executed by one or more programmable computers that execute one or more computer programs to perform corresponding functions by operating on input data and generating output. The processing and logic flow can also be executed by dedicated logic circuitry—such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the device can also be implemented as dedicated logic circuitry.

[0091] Suitable computers for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as disks, magneto-optical disks, or optical disks, or the computer will be operatively coupled to such mass storage devices to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0092] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. Processors and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0093] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather are primarily intended to describe features of specific embodiments of a particular invention. Certain features described in the various embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in various embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described above and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation thereof.

[0094] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0095] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

[0096] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method of controlling a hard disk, characterized by, The hard disks are arranged on a backplane of the server; the server further comprises a mainboard and a RAID card, the mainboard is provided with a programmable logic chip and at least one SlimSAS interface, each of the SlimSAS interfaces is in a binding relationship with a group of hard disks; and each group of hard disks comprises at least one hard disk; The RAID card is configured to send a first format of a lighting signal to the backplane; The lighting control method is applied to the programmable logic chip and comprises the following steps: obtaining an SGPIO lighting signal of the mainboard; parsing a plurality of data segments from the SGPIO lighting signal, each of the data segments being used for controlling a status light of one of the hard disks; combining data segments corresponding to the same SlimSAS interface as a data segment group, and combining each data segment in the data segment group into a new lighting signal, the new lighting signal being in the first format; sending each new lighting signal to the backplane through a corresponding SlimSAS interface to control the status lights of the hard disks in the group of hard disks bound to the SlimSAS interface.

2. The ignition control method according to claim 1, characterized by The step of obtaining the SGPIO lighting signal of the mainboard comprises the following steps: obtaining a first SGPIO lighting signal of the mainboard in a first time period; obtaining a second SGPIO lighting signal of the mainboard in a second time period; wherein the first SGPIO lighting signal and the second SGPIO lighting signal are used for controlling the status lights of different hard disks; The step of combining each data segment in the data segment group into a new lighting signal comprises at least one of the following steps: filtering a plurality of data segments for the same SlimSAS interface from the first SGPIO lighting signal and combining the data segments into a first new lighting signal; filtering a plurality of data segments for the same SlimSAS interface from the second SGPIO lighting signal and combining the data segments into a second new lighting signal; filtering a plurality of data segments for the same SlimSAS interface from the first SGPIO lighting signal and the second SGPIO lighting signal, respectively, and combining the data segments into a third new lighting signal.

3. The ignition control method according to claim 2, characterized by The process of combining into the third new lighting signal comprises the following steps: filtering a plurality of data segments for the same SlimSAS interface from the first / second SGPIO lighting signal received at the current time and the second / first SGPIO lighting signal received at the previous time, and combining the data segments into the new lighting signal.

4. The ignition control method according to claim 3, characterized by The method further comprises the following steps: saving the parsed plurality of data segments as data segments of the first / second SGPIO lighting signal received at the previous time.

5. The ignition control method according to claim 1 or 2, characterized by The SlimSAS interface comprises at least one high-speed line pin, and the binding relationship refers to a preset correspondence between the high-speed line pin of the SlimSAS interface and the hard disk.

6. The ignition control method according to claim 5, characterized by The process of combining into the third new lighting signal comprises the following steps: sorting and combining the data segments according to the order of the high-speed lines, so that each data segment in the third new lighting signal is arranged in the order of the hard disks that can be controlled; and the order of the high-speed lines is used to represent the order of the high-speed line pins corresponding to the hard disks in the SlimSAS interface.

7. The ignition control method according to claim 5, characterized by The data segments in the SGPIO lighting signal are arranged in the order of the high-speed lines; and the order of the high-speed lines is used to represent the order of the high-speed line pins corresponding to the hard disks in the SlimSAS interface.

8. A main board, characterized by, The mainboard is provided with a programmable logic chip and at least one SlimSAS interface, and the programmable logic chip is used to execute the method in any one of claims 1 to 7.

9. A server, characterized by The backplane, the mainboard and the RAID card are included; the backplane is provided with hard disks; and the mainboard is loaded with a programmable logic chip. The RAID card is used to send a first format lighting signal to the backplane. The programmable logic chip is used to execute the method in any one of claims 1 to 7 and send a new first format lighting signal to the backplane. The backplane is used to control the status light of the hard disk based on the new first format lighting signal.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program is executed by the processor to implement the method in any one of claims 1 to 7.

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