Protection circuit for resisting microprobe attack, electronic chip and electronic equipment

Abstract

The invention provides a protection circuit for resisting microprobe attack, an electronic chip and electronic equipment, the protection circuit is applied to the electronic chip, and the protection circuit comprises a mode driving module, a random number generation module, and a frequency calculation module, an address calculation module and an interrupt generation module which are connected with the mode driving module and the random number generation module, the mode driving module is used for driving the three modules connected with the mode driving module to work; the random number generation module regularly generates random numbers; and the frequency calculation module, the address calculation module and the interrupt generation module are respectively used for determining actual reading frequency, determining a to-be-read address and outputting an interrupt signal to the processor. According to the protection circuit disclosed by the invention, when the processor receives the interrupt signal, the actual reading times and the address to be read are respectively obtained from the times calculation module and the address calculation module, and data reading of the actual reading times is carried out on the memory of the electronic chip based on the address to be read; it is guaranteed that the number of times of reading the memory by the processor based on the interrupt signal each time is random, and therefore microprobe attacks can be effectively resisted.

Description

Technical Field

[0001] This invention relates to the field of electronic chip security protection, and more specifically, to a protective circuit, electronic chip, and electronic device against microprobe attacks. Background Technology

[0002] The security categories involved in computer systems can be divided into: hardware security, software security, network security, and information security. The difficulty of attacks and the magnitude of their impact are as follows: Figure 1 As shown.

[0003] Compared to other security categories, research on hardware security is lagging and limited because it was traditionally considered the root of trust (ROT) in design, meaning the computing system unconditionally trusts its own hardware. However, with the advent of high-precision analysis equipment targeting chips, system hardware can also be attacked and compromised, leading to an increasing number of security issues at the hardware layer.

[0004] In essence, security is a relative concept. There is no such thing as a one-size-fits-all security design in chip design; there are only various protective measures designed to counter specific attacks. Among them, microprobe technology (microprobe attack) is a rapidly developing and maturing attack method that uses a microscopic probe to probe the internal wires of a chip to obtain secret information, thereby enabling decryption or functional analysis.

[0005] Given that memory carries confidential information, it is also the most frequently targeted by microprobe attacks. Conventional memory security designs, such as Memory Protect Units (MPUs) for access control, CRC (Cyclic Redundancy Check) for tamper protection, and ECC (Error Checking and Correction) for error correction, are not capable of resisting microprobe attacks. Therefore, ensuring that the memory within electronic chips can effectively resist microprobe attacks is a problem that needs to be considered. Summary of the Invention

[0006] The purpose of this invention is to provide a protective circuit, electronic chip, and electronic device against microprobe attacks, so as to improve the problems existing in the prior art.

[0007] The embodiments of the present invention can be implemented as follows:

[0008] In a first aspect, the present invention provides a protective circuit against micro probe attacks, applied to electronic chips. The protective circuit includes a pattern driving module, a random number generation module, a count calculation module, an address calculation module, and an interrupt generation module.

[0009] The mode driving module is electrically connected to the interrupt generation module, the count calculation module and the address calculation module, and is used to output mode driving signals to the three to drive the three to work.

[0010] The random number generation module is electrically connected to the interrupt generation module, the count calculation module, and the address calculation module, and is used to generate random numbers at regular intervals so that the three modules can perform random number sampling.

[0011] The count calculation module is also electrically connected to the processor of the electronic chip, and is used to determine the actual count based on a preset count or a sampled random number;

[0012] The address calculation module is also electrically connected to the processor and is used to determine the address to be read based on a preset base address and a sampled random number.

[0013] The interrupt generation module is also electrically connected to the processor and is used to output an interrupt signal to the processor based on preset probability data, preset time data, and sampled random numbers; wherein, the interrupt signal is used to instruct the processor to obtain the actual number of reads and the address to be read from the count calculation module and the address calculation module respectively, and to read the data of the electronic chip's memory based on the address to be read.

[0014] In an optional implementation, the mode driving module includes a mode register and a decoder;

[0015] The decoder is electrically connected to the mode register, the count calculation module, the address calculation module, and the interrupt generation module, and is used to convert the protection mode signal stored in the mode register into the mode drive signal.

[0016] In an optional implementation, the mode drive signal has 8 bits; the count calculation module includes a count register, a fixed count register, a count calculation unit, and an actual count register.

[0017] The count calculation unit is electrically connected to the mode driving module, the random number generation module, the count register fixed count register, and the actual count register, and is used for: when any odd-numbered bit of the mode driving signal is valid, the third calculation unit reads the preset read count stored in the count register fixed count register and stores it as the actual read count in the actual count register; and when any even-numbered bit of the mode driving signal is valid, the third calculation unit uses the sampled random number to perform a modulo operation on the preset maximum read count to obtain the actual read count, and stores the actual read count in the actual count register.

[0018] In an optional implementation, the actual count register is also connected to the processor and is used to provide the processor with the actual count when the processor receives the interrupt signal.

[0019] In an optional implementation, the address calculation module includes a base address register, an address calculation unit, and a random address register;

[0020] The address calculation unit is electrically connected to the base address register, the mode driving module, the random number generation module, and the random address register. Under the drive of the mode driving signal, the fourth calculation unit is used to perform a modulo operation on the preset maximum read address using the sampled random number to obtain the modulo result, and the sum of the modulo result and the preset base address is stored as the address to be read in the random address register.

[0021] In an optional implementation, the random address register is also electrically connected to the processor and is used to provide the address to be read to the processor when the processor receives the interrupt signal.

[0022] In an optional implementation, the interrupt generation module includes an effective calculation module, a time calculation module, and an AND gate;

[0023] The effective calculation module is electrically connected to the mode driving module, the random number generation module, and the first input terminal of the AND gate. Under the drive of the mode driving signal, the effective calculation module outputs a valid flag signal to the AND gate based on the preset probability data and the sampled random number.

[0024] The time calculation module is electrically connected to the mode driving module, the random number generation module, and the second input terminal of the AND gate. Under the drive of the mode driving signal, the time calculation module outputs a time comparison signal to the AND gate based on the preset time data and the sampled random number.

[0025] The output of the AND gate is electrically connected to the processor and is used to perform a logical AND operation on the valid flag signal and the time comparison signal, and output the interrupt signal to the processor when the AND operation result is 1.

[0026] In an optional implementation, the effective calculation module includes a probability register, an effective calculation unit, and an effective register;

[0027] The effective calculation unit is electrically connected to the probability register, the mode driving module, the random number generation module, and the effective register. It is used to: under the drive of the mode driving signal, read the preset probability data stored in the probability register, perform a modulo operation on the preset probability precision using the sampled random number to obtain the modulo result, determine the effective flag signal based on the comparison result of the modulo result and the preset probability data, and store the effective flag signal in the effective register.

[0028] The valid register is also connected to the first input of the AND gate, and is used to output the valid flag signal to the AND gate.

[0029] In an optional implementation, the mode drive signal has 8 bits; the preset time data includes an upper time threshold and a lower time threshold; the time calculation module includes an upper time threshold register, a lower time threshold register, a time calculation unit, an interval register, a counter, and a comparator.

[0030] The time calculation unit is electrically connected to the upper time limit register, the lower time limit register, the mode driving module, the random number generation module, and the interval register. It is configured to: when any one of the first four bits of the mode driving signal is valid, the second calculation unit reads the lower time limit threshold stored in the lower time limit register and stores the lower time limit threshold as the current time interval in the interval register; and when any one of the last four bits of the mode driving signal is valid, the time calculation unit reads the upper time limit threshold and the lower time limit threshold stored in the upper time limit register and the lower time limit register respectively, calculates the time difference between them, performs a modulo operation on the time difference using a sampled random number, adds the lower time limit threshold to obtain the current time interval, and stores the current time interval in the interval register.

[0031] The interval register is also electrically connected to the first input terminal of the comparator, and is used to provide the comparator with the current time interval;

[0032] The counter is electrically connected to both the second input and the output of the comparator, and is used to provide a count value to the comparator; wherein, when the comparator outputs a time comparison signal of 0 once, the count value of the counter is incremented by 1; when the comparator outputs a time comparison signal of 1 once, the count value of the counter is set to 0;

[0033] The output of the comparator is also electrically connected to the second input of the AND gate, for comparing the current time interval of the interval register with the current count value of the counter, and outputting the time comparison signal to the counter and the AND gate; wherein, when the comparator outputs a time comparison signal of 0, the count value of the counter is accumulated periodically; when the comparator outputs a time comparison signal of 1, the count value of the counter is reset.

[0034] In an optional implementation, the protection circuit has eight operating modes, each corresponding to a different mode drive signal.

[0035] In a second aspect, the present invention provides an electronic chip, the electronic chip including a processor, a memory, and a protective circuit against microprobe attacks as described in the first aspect above;

[0036] When the processor receives an interrupt signal output by the protection circuit, it obtains the actual number of reads and the address to be read from the count calculation module and the address calculation module, respectively, and reads the data of the memory based on the address to be read based on the actual number of reads.

[0037] Thirdly, the present invention provides an electronic device comprising the electronic chip described in the second aspect above.

[0038] Compared with the prior art, the embodiments of the present invention provide a protective circuit, electronic chip and electronic device against micro probe attacks. The protective circuit is applied to the electronic chip and includes a pattern driving module, a random number generation module, a count calculation module, an address calculation module and an interrupt generation module. The module comprises three electrical components: a mode-driven module electrically connected to the interrupt generation module, the count calculation module, and the address calculation module, which outputs mode-driven signals to drive these components; a random number generation module electrically connected to the interrupt generation module, the count calculation module, and the address calculation module, which generates random numbers periodically for the three components to sample; a count calculation module electrically connected to the processor of the electronic chip, which determines the actual number of reads based on a preset number of reads or the sampled random numbers; an address calculation module electrically connected to the processor, which determines the address to be read based on a preset base address and the sampled random numbers; and an interrupt generation module electrically connected to the processor, which outputs an interrupt signal to the processor based on preset probability data, preset time data, and the sampled random numbers. The interrupt signal instructs the processor to obtain the actual number of reads and the address to be read from the count calculation module and the address calculation module, respectively, and to read the data from the electronic chip's memory based on the address to be read, based on the actual number of reads. The protection circuit of this invention enables the processor to obtain the actual number of reads and the address to be read from the count calculation module and the address calculation module respectively when it receives an interrupt signal, and to read the memory of the electronic chip based on the address to be read, thereby ensuring that the number of times the processor reads the memory based on the interrupt signal is random each time, thus effectively resisting micro probe attacks. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This diagram illustrates the attack difficulty and impact of different security categories involved in a computer system.

[0041] Figure 2 This is an example diagram of signals during a microprobe attack process in existing technologies.

[0042] Figure 3 This is an example diagram of data splicing after a micro-probe attack in existing technology.

[0043] Figure 4 This is one of the structural schematic diagrams of a protective circuit against microprobe attacks provided by the present invention.

[0044] Figure 5 This is the second schematic diagram of a protective circuit against microprobe attacks provided by the present invention.

[0045] Figure 6 The third schematic diagram of a protective circuit against microprobe attacks provided by the present invention.

[0046] Figure 7 The fourth schematic diagram of a protective circuit against microprobe attacks provided by the present invention.

[0047] Icons: 1000 - Electronic Chip; 10 - Protection Circuit; 100 - Mode Driver Module; 110 - Mode Register; 120 - Decoder; 200 - Random Number Generation Module; 300 - Count Calculation Module; 310 - Fixed Count Register; 320 - Count Calculation Unit; 330 - Actual Count Register; 400 - Address Calculation Module; 410 - Base Address Register; 420 - Address Calculation Unit; 430 - Random Address Register; 500 - Interrupt Generation Module; 510 - Valid Calculation Module; 511 - Probability Register; 512 - Valid Calculation Unit; 513 - Valid Register; 520 - Time Calculation Module; 521 - Upper Time Limit Register; 522 - Lower Time Limit Register; 523 - Time Calculation Unit; 524 - Interval Register; 525 - Counter; 526 - Comparator; 530 - AND Gate; 20 - Processor; 30 - Memory. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0050] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0051] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0052] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0053] As mentioned in the background section, in electronic chips, memory serves as a carrier of confidential information and is frequently attacked by microprobes. Some existing conventional memory security designs do not have the ability to resist microprobe attacks.

[0054] Therefore, in order to enable electronic chips to resist microprobe attacks targeting memory, it is necessary to start with the principle of microprobe attacks targeting memory and carry out targeted design.

[0055] The following describes one of the most feasible procedures for micro-probe attacks on chip memory or bus data:

[0056] 1. Reverse engineering to obtain the circuit structure of a chip: that is, using tools such as microscopes and scanning electron microscopes (SEM) to observe the physical structure of the chip;

[0057] 2. Based on FIB (Focused Ion Beam) technology, the circuitry on the chip is precisely modified or manufactured to create probe points or disconnect / redirect internal connections;

[0058] 3. Use the probe multiple times at the detection points determined in the memory to detect the signals of the wires inside the chip;

[0059] 4. The detected signals are spliced ​​together to form correct bus data;

[0060] 5. Use EDA (Electronic Design Automation) tools for simulation analysis or decompilation analysis.

[0061] Assuming three signal probe points (DATA(m-3), DATA(m-2), and DATA(m-1)) and one clock probe point (CLK) are determined, an example diagram of the signals obtained from multiple probes in step 2 is shown below. Figure 2 As shown in the figure, an example diagram of data splicing in step 4 is as follows. Figure 3 As shown.

[0062] from Figure 2 and Figure 3 As can be seen, during each probe, three signal probe points and one clock probe point are probed simultaneously, and each probe involves n data reads. If the final concatenated data is plaintext, the attacker only needs to decompile it to analyze the chip function or other important information; if the final concatenated data is memory ciphertext, the attacker can use EDA tools to simulate and analyze the netlist obtained from reverse engineering, and can also obtain the chip function or other important information.

[0063] Therefore, in order to prevent attackers from quickly obtaining the actual data of the memory and bus during chip operation based on micro-probe technology, the inventors designed a protective circuit against micro-probe attacks. The key points are:

[0064] 1. The number of times the chip reads the memory is different each time it operates, to prevent attackers from analyzing and summarizing the patterns of the probe test waveforms and thus quickly obtaining the correct data sequence;

[0065] 2. Multiple modes are available, making it more practical and more resistant to analysis.

[0066] The protection circuit provided by the present invention will be described in detail below.

[0067] Please see Figure 4 , Figure 4 This is one of the structural schematic diagrams for resisting micro-probe attacks provided by the present invention. The protection circuit 10 is applied to an electronic chip 1000, which also includes a processor 20 and a memory 30. The protection circuit 10 includes a pattern driving module 100, a random number generation module 200, a count calculation module 300, an address calculation module 400, and an interrupt generation module 500;

[0068] The mode driving module 100 is electrically connected to the interrupt generation module 500, the count calculation module 300, and the address calculation module 400, and is used to output mode driving signals to the three to drive the three to work.

[0069] The random number generation module 200 is electrically connected to the interrupt generation module 500, the count calculation module 300, and the address calculation module 400, and is used to generate random numbers at regular intervals so that the three modules can perform random number sampling.

[0070] The count calculation module 300 is also electrically connected to the processor 20 of the electronic chip 1000, and is used to determine the actual number of reads based on a preset number of reads or a sampled random number;

[0071] The address calculation module 400 is also electrically connected to the processor 20 and is used to determine the address to be read based on a preset base address and a sampled random number.

[0072] The interrupt generation module 500 is also electrically connected to the processor 20 and is used to output an interrupt signal to the processor 20 based on preset probability data, preset time data and sampled random numbers. The interrupt signal is used to instruct the processor 20 to obtain the actual number of reads and the address to be read from the count calculation module 300 and the address calculation module 400 respectively, and to read the data of the actual number of reads from the memory 30 of the electronic chip 1000 based on the address to be read.

[0073] The protective circuit 10 against micro-probe attacks provided in this embodiment of the invention is applied to an electronic chip 1000. It includes a mode driving module 100, a random number generation module 200, and a count calculation module 300, an address calculation module 400, and an interrupt generation module 500, all connected to the mode driving module 100. The mode driving module 100 drives the three connected modules to operate. The random number generation module 200 generates random numbers periodically. The count calculation module 300, address calculation module 400, and interrupt generation module 500 are respectively used to determine the actual number of reads, determine the address to be read, and output an interrupt signal to the processor 20. The protective circuit 10 of this invention enables the processor 20 to obtain the actual number of reads and the address to be read from the count calculation module 300 and the address calculation module 400 respectively when it receives an interrupt signal. Based on the address to be read, it reads the data of the actual number of reads from the memory 30 of the electronic chip 1000, ensuring that the number of reads from the memory 30 by the processor 20 based on the interrupt signal is random each time, thereby effectively resisting micro-probe attacks.

[0074] For optional implementation methods, please refer to [link / reference]. Figure 5 The mode driving module 100 may include a mode register 110 and a decoder 120; the decoder 120 is electrically connected to the mode register 110, the count calculation module 300, the address calculation module 400 and the interrupt generation module 500, and is used to convert the protection mode signal stored in the mode register 110 into a mode driving signal.

[0075] Optionally, the mode drive signal has 8 bits, allowing the protection circuit 10 to have 8 operating modes. Different operating modes correspond to different protection mode signals and mode drive signals. Please continue reading. Figure 5 The count calculation module 300 may include a fixed count register 310, a count calculation unit 320, and an actual count register 330;

[0076] The count calculation unit 320 is electrically connected to the mode driving module 100, the random number generation module 200, the fixed count register 310, and the actual count register 330. It is used to: read the preset count stored in the fixed count register 310 when any odd-numbered bit of the mode driving signal is valid, and store it as the actual count in the actual count register 330; and when any even-numbered bit of the mode driving signal is valid, use the sampled random number to perform a modulo operation on the preset maximum count to obtain the actual count, and store the actual count in the actual count register 330.

[0077] The actual count register 330 is also connected to the processor 20 and is used to provide the processor 20 with the actual count when the processor 20 receives an interrupt signal.

[0078] Optional, please continue to see Figure 5 The address calculation module 400 may include a base address register 410, an address calculation unit 420, and a random address register 430;

[0079] The address calculation unit 420 is electrically connected to the base address register 410, the mode driving module 100, the random number generation module 200, and the random address register 430. Under the drive of the mode driving signal, it uses the sampled random number to perform a modulo operation on the preset maximum read address to obtain the modulo result, and stores the sum of the modulo result and the preset base address as the address to be read in the random address register 430.

[0080] The random address register 430 is also electrically connected to the processor 20 and is used to provide the processor 20 with the address to be read when the processor 20 receives an interrupt signal.

[0081] Optional, please continue to see Figure 5 The interrupt generation module 500 may include an effective calculation module 510, a time calculation module 520, and an AND gate 530;

[0082] The effective calculation module 510 is electrically connected to the pattern driving module 100, the random number generation module 200, and the first input terminal of the AND gate 530, and is used to output a valid flag signal to the AND gate 530 based on preset probability data and sampled random numbers under the drive of the pattern driving signal.

[0083] The time calculation module 520 is electrically connected to the mode driving module 100, the random number generation module 200 and the second input terminal of the AND gate 530, and is used to output a time comparison signal to the AND gate 530 based on preset time data and sampled random numbers under the drive of the mode driving signal.

[0084] The output of AND gate 530 is electrically connected to processor 20 and is used to perform a logical AND operation on the valid flag signal and the time comparison signal. When the result of the AND operation is 1, an interrupt signal is output to processor 20.

[0085] Optional, please see Figure 6 The effective calculation module 510 may include a probability register 511, an effective calculation unit 512, and an effective register 513;

[0086] The effective calculation unit 512 is electrically connected to the probability register 511, the mode driving module 100, the random number generation module 200, and the effective register 513. It is used to: read the preset probability data stored in the probability register 511 under the drive of the mode driving signal, and use the sampled random number to perform a modulo operation on the preset probability precision to obtain the modulo result, and determine the effective flag signal based on the comparison result of the modulo result and the preset probability data, and store the effective flag signal in the effective register 513.

[0087] The valid register 513 is also connected to the first input of AND gate 530 and is used to output a valid flag signal to AND gate 530.

[0088] Optional, please continue to see Figure 6 The preset time data includes an upper time threshold and a lower time threshold; the time calculation module 520 may include: an upper time threshold register 521, a lower time threshold register 522, a time calculation unit 523, an interval register 524, a counter 525, and a comparator 526;

[0089] The time calculation unit 523 is electrically connected to the upper time limit register 521, the lower time limit register 522, the mode driving module 100, the random number generation module 200, and the interval register 524. It is used for: when any one of the first four bits of the mode driving signal is valid, reading the lower time limit threshold stored in the lower time limit register 522 and storing the lower time limit threshold as the current time interval in the interval register 524; and when any one of the last four bits of the mode driving signal is valid, reading the upper time limit threshold and the lower time limit threshold stored in the upper time limit register 521 and the lower time limit register 522 respectively and calculating the time difference between the two, performing a modulo operation on the time difference using the sampled random number and adding the lower time limit threshold to obtain the current time interval, and storing the current time interval in the interval register 524.

[0090] The interval register 524 is also electrically connected to the first input of the comparator 526 to provide the current time interval to the comparator 526;

[0091] The counter 525 is electrically connected to both the second input and the output of the comparator 526, and is used to provide a count value to the comparator 526;

[0092] The output of comparator 526 is also electrically connected to the second input of AND gate 530, used to compare the current time interval of interval register 524 with the current count value of counter 525, and output a time comparison signal to counter 525 and AND gate 530; wherein, when the time comparison signal output by comparator 526 is 0, the count value of counter 525 is incremented in a timed manner; when the time comparison signal output by comparator 526 is 1, the count value of counter 525 is reset.

[0093] That is, combining Figure 6 When the processor 20 receives the interrupt signal generated by the protection circuit 10, it will immediately read the random address register 430 of the protection circuit 10 to obtain the actual number of reads M and read the actual number of reads register 330 to obtain the address to be read ADDR1. The processor 20 can perform M data reads on the memory 30 based on ADDR1.

[0094] Alternatively, processor 20 can first perform a first data read from memory 30 based on ADDR1, then read the actual number of reads register 330 to obtain the address to be read, ADDR2, and then perform a second data read from memory 30 based on ADDR2, and so on, until processor 20 obtains the address to be read, ADDRM, and then performs the Mth data read from memory 30 based on ADDRM, at which point the reading ends. Since the random number generation module 200 generates random numbers periodically, the address to be read in the random address register 430 may change if the random number changes. That is, the M addresses to be read successively by processor 20 (ADDR1, ADDR2, ADDR3...ADDRM) may be exactly the same or different. If the random number generation frequency is set high, it is easy to have M different addresses to be read, thus making the addresses of the M data reads random, which also helps to combat micro-probe attacks.

[0095] Optionally, the 30-bit memory of the mode register 110 is at least 4 bits, the decoder 120 has at least four input lines and at least eight output lines. In an optional example, the protection mode signal and mode drive signal of the protection circuit 10 in different operating modes are shown in Table (1) below:

[0096] Table (1)

[0097]

[0098]

[0099] Optional, combined Figure 6 The data in the mode register 110, fixed number of times register 310, base address register 410, probability register 511, time upper limit register 521, and actual lower limit register can be fixed or can be adaptively configured by the processor 20 according to different working modes, which is not limited here.

[0100] Taking processor 20 as an example, the effects of data in each register under different operating modes are as follows:

[0101] (1) The configuration data of the fixed number of reads register 310 is effective in mode 1, mode 3, mode 5 and mode 7. The fixed number of reads register 310 is used to store the fixed number of reads of memory 30 (assuming it is M0).

[0102] (2) The configuration data of the base address register 410 is effective in all modes. The fixed number of times register 310 is used to store the base address for reading data from memory 30, i.e. the starting address (assuming it is ADDR0).

[0103] (3) The configuration data of probability register 511 is effective in modes 3, 4, 7, and 8. Probability register 511 is used to store preset probability data (let's assume it's L);

[0104] (4) The configuration data of the time limit register 521 is effective in modes 5, 6, 7, and 8. The time limit threshold (assumed to be A) in the time limit register 521 serves as the maximum time interval constraint for reading data from the memory 30;

[0105] (5) The configuration data of the time lower limit register 522 is effective in all modes. Specifically, in modes 1, 2, 3, and 4, the time lower limit threshold (assumed to be B) in the time lower limit register 522 serves as a timing time interval constraint; in modes 5, 6, 7, and 8, the time lower limit threshold in the time lower limit register 522 serves as a minimum time interval constraint for reading data from the memory 30.

[0106] Please combine Figure 7 Based on Table (1) above, the working principles of the four computing units in the protection circuit 10 under different working modes will be introduced below.

[0107] (1) Count calculation unit 320:

[0108] In modes 1, 3, 5, and 7, the count calculation unit 320 directly reads the preset count M0 stored in the fixed count register 310 and then stores the actual count M = M0 in the actual count register 330.

[0109] In modes 2, 4, 6, and 8, the actual number of reads M = RNG%N stored in the actual number of reads register 330 by the count calculation unit 320, where N represents the preset maximum number of reads and RNG represents the sampled random number; M will be recalculated when the random number RNG changes once.

[0110] (2) Address calculation unit 420:

[0111] In full mode, ADDRout = ADDR0 + RNG%K, where K represents the preset maximum read address; ADDRout will be recalculated every time the random number RNG changes.

[0112] (3) Effective calculation unit 512:

[0113] Assuming the preset probability precision is 100 and the probability configuration data is P. In full mode: when RNG%100≤P, the effective calculation unit 512 stores the effective flag signal Y=1 in the effective register 513; when RNG%100>P, the effective calculation unit 512 stores the effective flag signal Y=0 in the effective register 513.

[0114] (4) Time calculation unit 523:

[0115] In modes 1, 2, 3, and 4, the time calculation unit 523 directly reads the time lower limit threshold B stored in the time lower limit register 522 and then stores the current time interval T = B in the interval register 524. In modes 5, 6, 7, and 8, the time calculation unit 523 directly reads the time upper limit threshold A stored in the time upper limit register 521 and the time lower limit threshold B stored in the time lower limit register 522, and then calculates the current time interval T = RNG%(AB) + B by combining it with the sampled random number RNG. When the random number RNG changes once, T will be recalculated.

[0116] Combination Figure 7 In full mode, counter 525 performs an accumulation operation at regular intervals. When the count value equals the current time interval T, the comparator 526 outputs a comparison signal Z=1, and counter 525 is reset.

[0117] In full mode, when Y=0, the comparison signal Z=1 or Z=0 is invalid, the protection circuit 10 does not generate an interrupt signal, and the processor 20 operates normally. Only when the valid flag signal Y=1 and the comparison signal Z=1, the protection circuit 10 outputs an interrupt signal to the processor 20.

[0118] When the processor 20 receives an interrupt signal from the protection circuit 10, it immediately suspends the original program and performs M read operations on the memory 30. The address read each time is derived from the address to be read calculated by the protection circuit 10. The processor 20 independently verifies the address to be read each time. If the verification passes, the read is performed. After M reads are completed, the processor 20 completes the interrupt handling and resumes the original program. If a verification fails, it means that the address is invalid, and the processor 20 resets the electronic chip 1000.

[0119] Optionally, during the power-on operation of the electronic chip 1000, the processor 20 can configure the mode register 110 to 0000 to disable the entire protection circuit 10; when running an important program, the processor 20 can configure the mode register 110 to one of 0001 to 1000 to enable the protection circuit 10 to start, thereby enabling the memory 30 of the electronic chip 1000 to have the ability to resist micro probe attacks.

[0120] The above combination Figure 7 The designations used for each signal are merely examples for ease of understanding and are not intended to be limiting.

[0121] In an electronic chip 1000 that utilizes the protection circuit 10 provided by this invention, the memory 30 is subjected to i micro-probe attacks, and the results are shown in the table below:

[0122] Microprobe attack count Memory read count 1 n 2 n+r1 3 n+r2 …… …… i-1 n+r3 i n+r4

[0123] It is evident from the table that the number of memory reads is inconsistent in the results obtained from different microprobes. This makes it difficult for attackers to combine and statistically analyze the probe results. In other words, the protection circuit 10 provided by this invention can effectively resist microprobe attacks, thereby protecting the correct data sequence of the memory 30 and causing some important reference signals of the chip to lose their reference significance due to the addition of randomness, thus improving chip security.

[0124] It should be noted that the object protected by the protection circuit 10 in the above description is the memory 30 in the electronic chip 1000. At the same time, the object protected by the protection circuit 10 can also be: data with a bus structure, characteristic signals with a fixed number of times, and chip reference signals in the electronic chip 1000, etc., to counteract micro probe attacks. The principle is basically the same as the above description and will not be elaborated here.

[0125] This invention also provides an electronic chip 1000, which includes a processor 20, a memory 30, and the aforementioned protection circuit 10 against microprobe attacks. The processor 20, upon receiving an interrupt signal from the protection circuit 10, obtains the actual number of reads and the address to be read from the count calculation module 300 and the address calculation module 400, respectively, and reads the data from the memory 30 based on the address to be read, representing the actual number of reads.

[0126] The memory 30 may be, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), FLASH (Flash Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0127] The processor 20 can be an integrated circuit chip with signal processing capabilities. The processor 20 can be a general-purpose processor, including: CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be: DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0128] This invention also provides an electronic device, which includes the aforementioned electronic chip 1000.

[0129] In summary, this invention provides a protective circuit, electronic chip, and electronic device to combat micro-probe attacks. The protective circuit, applied to the electronic chip, includes a pattern driving module, a random number generation module, and a count calculation module, an address calculation module, and an interrupt generation module, all connected to the pattern driving module. The pattern driving module drives the three connected modules; the random number generation module generates random numbers periodically; and the count calculation module, address calculation module, and interrupt generation module are respectively used to determine the actual number of reads, determine the address to be read, and output an interrupt signal to the processor. This protective circuit ensures that when the processor receives an interrupt signal, it obtains the actual number of reads and the address to be read from the count calculation module and the address calculation module, respectively, and reads the actual number of reads from the electronic chip's memory based on the address to be read. This guarantees that the number of reads from the memory based on the interrupt signal is random each time, thus effectively combating micro-probe attacks.

[0130] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A guard circuit against micro-probe attacks, characterized in that, The protection circuit applied to an electronic chip comprises a mode driving module, a random number generating module, a frequency calculating module, an address calculating module and an interrupt generating module. The mode driving module is electrically connected with the interrupt generating module, the frequency calculating module and the address calculating module, and is configured to output a mode driving signal to the three modules to drive the three modules to work. The random number generating module is electrically connected with the interrupt generating module, the frequency calculating module and the address calculating module, and is configured to generate random numbers at a fixed time to make the three modules sample the random numbers. The frequency calculating module is further electrically connected with a processor of the electronic chip, and is configured to determine an actual reading frequency based on a preset reading frequency or the sampled random numbers. The address calculating module is further electrically connected with the processor, and is configured to determine a to-be-read address based on a preset base address and the sampled random numbers. The interrupt generating module is further electrically connected with the processor, and is configured to output an interrupt signal to the processor based on preset probability data, preset time data and the sampled random numbers; the interrupt signal is configured to instruct the processor to acquire the actual reading frequency and the to-be-read address from the frequency calculating module and the address calculating module respectively, and to perform data reading on a memory of the electronic chip for the actual reading frequency based on the to-be-read address.

2. The protection circuit of claim 1, wherein, The mode driving module comprises a mode register and a decoder. The decoder is electrically connected with the mode register, the frequency calculating module, the address calculating module and the interrupt generating module, and is configured to convert a protection mode signal stored in the mode register into the mode driving signal.

3. The protection circuit of claim 1, wherein, The mode driving signal has 8 bits; the frequency calculating module comprises a fixed frequency register, a frequency calculating unit and an actual frequency register. The frequency calculating unit is electrically connected with the mode driving module, the random number generating module, the fixed frequency register and the actual frequency register, and is configured to: when any odd bit of the mode driving signal is valid, read the preset reading frequency stored in the fixed frequency register and store the preset reading frequency as the actual reading frequency in the actual frequency register; and when any even bit of the mode driving signal is valid, perform a modulo operation on a preset maximum reading frequency by using the sampled random number to obtain the actual reading frequency, and store the actual reading frequency in the actual frequency register. The actual frequency register is further connected with the processor, and is configured to provide the actual reading frequency to the processor when the processor receives the interrupt signal.

4. The protection circuit of claim 3, wherein, The address calculating module comprises a base address register, an address calculating unit and a random address register.

5. The protection circuit of claim 1, wherein, The address calculating unit is electrically connected with the base address register, the mode driving module, the random number generating module and the random address register, and is configured to, under the driving of the mode driving signal, perform a modulo operation on a preset maximum reading address by using the sampled random number to obtain a modulo result, and store the sum of the modulo result and the preset base address as the to-be-read address in the random address register. ​ 6. The protection circuit of claim 5, wherein, The random address register is also electrically connected with the processor, for providing the to-be-read address to the processor when the processor receives the interrupt signal.

7. The protection circuit of claim 1, wherein, The interrupt generation module comprises an effective calculation module, a time calculation module and an AND gate; The effective calculation module is electrically connected with the mode driving module, the random number generation module and a first input terminal of the AND gate, for outputting an effective flag signal to the AND gate based on the preset probability data and the sampled random number under the driving of the mode driving signal; The time calculation module is electrically connected with the mode driving module, the random number generation module and a second input terminal of the AND gate, for outputting a time comparison signal to the AND gate based on the preset time data and the sampled random number under the driving of the mode driving signal; An output terminal of the AND gate is electrically connected with the processor, for performing logical AND operation on the effective flag signal and the time comparison signal, and outputting the interrupt signal to the processor when the AND operation result is 1.

8. The protection circuit of claim 7, wherein, The effective calculation module comprises a probability register, an effective calculation unit and an effective register; The effective calculation unit is electrically connected with the probability register, the mode driving module, the random number generation module and the effective register, for reading the preset probability data stored in the probability register under the driving of the mode driving signal, performing remainder operation on the preset probability precision by using the sampled random number to obtain a remainder result, determining the effective flag signal based on a comparison result of the remainder result and the preset probability data, and storing the effective flag signal to the effective register; The effective register is also connected with the first input terminal of the AND gate, for outputting the effective flag signal to the AND gate.

9. The protection circuit of claim 7, wherein, The bit number of the mode driving signal is 8; the preset time data comprises an upper time threshold and a lower time threshold; the time calculation module comprises an upper time register, a lower time register, a time calculation unit, an interval register, a counter and a comparator; The time calculation unit is electrically connected with the upper time register, the lower time register, the mode driving module, the random number generation module and the interval register, for reading the lower time threshold stored in the lower time register when any bit in the first four bits of the mode driving signal is effective, and storing the lower time threshold as a current time interval to the interval register; and reading the upper time threshold and the lower time threshold stored in the upper time register and the lower time register respectively when any bit in the last four bits of the mode driving signal is effective, calculating a time difference value of the upper time threshold and the lower time threshold, performing remainder operation on the time difference value by using the sampled random number, adding the lower time threshold to the time difference value to obtain the current time interval, and storing the current time interval to the interval register; The interval register is also electrically connected with a first input terminal of the comparator, for providing the current time interval to the comparator; The counter is electrically connected with the second input terminal and the output terminal of the comparator, for providing the counter value to the comparator; The output terminal of the comparator is also electrically connected with the second input terminal of the AND gate, for comparing the current time interval of the interval register with the current counter value of the counter, and outputting the time comparison signal to the counter and the AND gate; wherein when the time comparison signal output by the comparator is 0, the counter value is timed to accumulate; when the time comparison signal output by the comparator is 1, the counter value is reset.

10. The protection circuit according to claim 3 or 9, characterized in that, The protection circuit has 8 working modes, and different working modes correspond to different mode driving signals.

11. An electronic chip, characterized by The electronic chip comprises a processor, a memory and the protection circuit against micro-probe attack according to any one of claims 1-10. The processor is configured to acquire the actual reading times and the to-be-read address from the times counting module and the address counting module respectively when receiving the interrupt signal output by the protection circuit, and perform data reading of the actual reading times on the memory based on the to-be-read address.

12. An electronic device, comprising: The electronic device comprises the electronic chip according to claim 11.

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