Information processing method of isomorphic quantum circuit and related device

Abstract

The invention discloses an information processing method of an isomorphic quantum circuit and a related device, and belongs to the field of quantum computation.The method comprises the steps that the isomorphic quantum circuit is compressed and coded to a target byte according to the mapping relation between the quantum circuit and the target byte so as to generate a target byte stream; and transmitting the target byte stream from the client to the server. According to the method, the circuit structure and the data of the quantum circuit are split, the related information of the quantum circuit is compressed and coded before network transmission, and the information is decoded after being transmitted, so that efficient data transmission in a client-server architecture mode is realized, and the data transmission efficiency is improved. Therefore, the network transmission delay in the quantum classical hybrid computing service can be reduced, and network resources are effectively saved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum computing, and particularly relates to an information processing method of isomorphic quantum circuits and a related device. BACKGROUND

[0002] In actual deployment of quantum-classical hybrid computing, especially when a variational quantum circuit is applied in a real quantum chip or quantum cloud service, bidirectional data transmission is usually adopted in a "client-server" architecture mode. In this mode, the user side needs to submit multiple quantum circuit computing tasks at a time. However, with the increase of complexity of the variational quantum circuit, i.e., the increase of the depth of the quantum circuit, the number of qubits and the number of circuits, the amount of data transmitted from the client to the server increases explosively, which not only poses a severe challenge to the network bandwidth, but also directly affects the overall performance and response speed of the quantum-classical hybrid computing service.

[0003] Therefore, it is urgent to provide a new information processing method capable of effectively transmitting batch quantum variational circuits, so as to improve the comprehensive processing capability of the quantum-classical hybrid computing service. SUMMARY

[0004] The application aims to provide an information processing method of isomorphic quantum circuits and a related device, which can facilitate efficient data transmission of quantum circuits between the client and the server, improve the processing capability of the quantum-classical hybrid computing service, reduce network delay, and effectively save network resources.

[0005] One embodiment of the application provides an information processing method of isomorphic quantum circuits, applied to a client, and the method comprises the following steps.

[0006] According to a mapping relationship between the quantum circuit and target bytes, the isomorphic quantum circuit is compressed and encoded into the target bytes to generate a target byte stream.

[0007] The target byte stream is transmitted from the client to a server.

[0008] Optionally, before the step of compressing and encoding the isomorphic quantum circuit into the target bytes according to the mapping relationship between the quantum circuit and the target bytes to generate the target byte stream, the method further comprises the following steps.

[0009] A user-submitted isomorphic quantum circuit is received.

[0010] A parameter-containing quantum logic gate of the isomorphic quantum circuit is determined, wherein the parameter-containing quantum logic gate comprises a quantum logic gate structure and a quantum logic gate parameter.

[0011] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0012] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0013] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0014] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0015] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0016] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0017] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0018] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0019] Another embodiment of the application provides an information processing method of an isomorphic quantum circuit, applied to a server, and the method comprises the following steps:

[0020] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0021] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0022] Optionally, the mapping relationship between the quantum circuit and the target byte is determined, and the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte.

[0023] Determine the byte stream structure of the target byte stream; wherein the byte stream structure includes the byte order and / or the required number of bytes;

[0024] Optionally, the step of decoding the target byte stream based on the mapping relationship between the target bytes and the quantum circuit before compression encoding to generate the original quantum circuit information includes:

[0025] Determine the mapping relationship between the target byte and the quantum circuit; wherein the mapping relationship is used to characterize the correspondence between the target byte and the isomorphic quantum circuit and the parameterized quantum logic gate;

[0026] The original quantum circuit information is obtained by decoding the byte stream structure of the target byte stream according to the mapping relationship.

[0027] Another embodiment of the present invention provides an information processing device for isomorphic quantum circuits, applied to a client, the device comprising:

[0028] An encoding unit is used to compress and encode the isomorphic quantum circuit into the target byte according to the mapping relationship between the quantum circuit and the target byte, so as to generate a target byte stream;

[0029] A transmission unit is used to transmit the target byte stream from the client to the server.

[0030] Another embodiment of the present invention provides an information processing device for homogeneous quantum circuits, applied to a server, the device comprising:

[0031] The decoding unit is used to decode the target byte stream according to the mapping relationship between the target byte and the quantum circuit before compression encoding, so as to generate the original quantum circuit information.

[0032] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0033] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0034] Compared with the prior art, the present invention provides an information processing method for isomorphic quantum circuits. First, according to the mapping relationship between the quantum circuit and the target byte, the isomorphic quantum circuit is compressed and encoded into the target byte to generate a target byte stream; then the target byte stream is transmitted from the client to the server.

[0035] This invention first compresses and encodes the isomorphic quantum circuit into the target byte based on the mapping relationship between the quantum circuit and the target byte to generate a target byte stream. By converting the quantum circuit into the target byte form through the mapping relationship, effective data compression is achieved. This not only simplifies the data expression method but also reduces the data storage requirements. By compressing and encoding the quantum circuit into a target byte stream with a smaller data volume, the network bandwidth resources occupied during data transmission can be significantly reduced. This is especially important for application scenarios with limited network conditions or cost sensitivity. In addition, smaller data packets mean faster transmission speeds, thereby improving the response time and processing capacity of the entire system. By encrypting the data through compression encoding, data security is improved. Attached Figure Description

[0036] Figure 1 This is a network block diagram of an information processing system based on a homogeneous quantum circuit, provided as an embodiment of the present invention.

[0037] Figure 2 This is a flowchart of an information processing method for isomorphic quantum circuits provided in an embodiment of the present invention.

[0038] Figure 3 This is a flowchart of a target byte stream generation method provided in an embodiment of the present invention.

[0039] Figure 4 This is a schematic diagram of client-side encoding provided in an embodiment of the present invention.

[0040] Figure 5 A flowchart of another information processing method for isomorphic quantum circuits provided in an embodiment of the present invention.

[0041] Figure 6 This is a flowchart of a method for generating raw quantum circuit information provided in an embodiment of the present invention.

[0042] Figure 7 This is a schematic diagram of server-side decoding provided in an embodiment of the present invention.

[0043] Figure 8 This is a structural diagram of an information processing device based on a homogeneous quantum circuit, provided in an embodiment of the present invention.

[0044] Figure 9 This is a structural diagram of another isomorphic quantum circuit information processing device provided in an embodiment of the present invention.

[0045] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0046] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0047] Figure 1 This is a network block diagram of an information processing system based on a homogeneous quantum circuit according to an embodiment of the present invention. The information processing system based on the homogeneous quantum circuit may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices (not shown).

[0048] Network 110 is a medium used to provide communication links between various devices and computers connected together within an information processing system of homogeneous quantum circuits, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof, and the connection method can be wired, wireless communication links or fiber optic cables, etc.

[0049] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0050] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled by the information processing method of isomorphic quantum circuits provided in the embodiments of the present invention.

[0051] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0052] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0053] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0054] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0055] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0056] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0057] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0058] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0059] In practical deployments of quantum-classical hybrid computing, especially when variable quantum circuits are used in real quantum chips or quantum cloud services, a bidirectional data transmission architecture of "client-server" is typically adopted. In this model, the user sometimes needs to submit multiple quantum circuit computing tasks at once. However, with the increasing complexity of variable quantum circuits—namely, the increase in the depth of quantum circuits, the number of qubits, and the number of circuits—the amount of data transmitted from the client to the server has exploded. This surge in data volume not only poses a severe challenge to network bandwidth but also directly affects the overall performance and response speed of quantum-classical hybrid computing services.

[0060] Therefore, the urgent technical problem to be solved is to propose a new information processing method that can effectively transmit batch quantum variational circuits, so that quantum circuits can transmit data efficiently from the client to the server, thereby improving the overall processing capability of quantum-classical hybrid computing services.

[0061] See Figure 2 , Figure 2 A flowchart of an information processing method for isomorphic quantum circuits provided in an embodiment of the present invention, the method comprising the following steps:

[0062] Step S201: Based on the mapping relationship between the quantum circuit and the target byte, the isomorphic quantum circuit is compressed and encoded into the target byte to generate a target byte stream.

[0063] Among them, a byte stream refers to a sequence of bytes that can be recognized by a computer system and used for subsequent data transmission and processing; a homogeneous quantum circuit refers to a quantum circuit that has the same structure but contains different parameters.

[0064] Specifically, based on the predefined mapping relationship between quantum circuits and target bytes, isomorphic quantum circuits are compressed and encoded, and then converted into target byte sequences.

[0065] For example, suppose there is a series of isomorphic quantum circuits, all composed of the same quantum gates (such as Pauli-X gate X), each quantum gate acting on different qubits. To store and transmit these quantum circuits, a compression coding method is used to compress each quantum circuit into one or several bytes, ensuring that the total number of bytes after compression is less than the number of bytes required for direct encoding. First, a mapping rule is defined: each Pauli-X gate X acting on qubit q_n is mapped to one byte. The lower n bits of the byte are used to represent the index of the qubit, while the remaining higher bits can be used as reserved bits or to represent additional control information. Suppose there are 8 qubits, using 3 bits of one byte to represent the qubit index, and the remaining 5 bits can be reserved for future use or set to a fixed value (such as all 0s). Suppose there are three... Homogeneous quantum circuits, each containing a Pauli-X gate acting on different qubits, X(q_0) of circuit 1, X(q_1) of circuit 2, and X(q_2) of circuit 3, are encoded into the following bytes according to the mapping rules: circuit 1 is encoded as 00000001 (in reality, only the 3 bits 001 are needed to represent q_0, and the remaining bits are set to 0), circuit 2 is encoded as 00000010 (again, only 010 is needed), and circuit 3 is encoded as 00000100 (only 100 is needed). To achieve the compression effect, only the necessary bits are used for encoding, i.e., circuit 1 is encoded as 001, circuit 2 as 010, and circuit 3 as 100. In actual storage or transmission, only the necessary byte portion (such as the effective bits in 001 010 100) can be stored or transmitted to generate the target byte stream.

[0066] Step S202: Transmit the target byte stream from the client to the server.

[0067] In summary, this invention first compresses and encodes the isomorphic quantum circuit into the target byte based on the mapping relationship between the quantum circuit and the target byte to generate a target byte stream. By converting the quantum circuit into the target byte form through the mapping relationship, effective data compression is achieved, which not only simplifies the data expression method but also reduces the data storage requirements. By compressing and encoding the quantum circuit into a target byte stream with a smaller data volume, the network bandwidth resources occupied during data transmission can be significantly reduced. This is especially important for application scenarios with limited network conditions or cost sensitivity. In addition, smaller data packets mean faster transmission speeds, thereby improving the response time and processing capacity of the entire system. By encrypting the data through compression encoding, data security is improved.

[0068] In one embodiment of this application, before compressing and encoding the isomorphic quantum circuit into the target byte according to the mapping relationship between the quantum circuit and the target byte to generate the target byte stream, the method further includes:

[0069] Receive isomorphic quantum circuits submitted by users.

[0070] Determine the parametric quantum logic gate of the isomorphic quantum circuit; wherein the parametric quantum logic gate includes the quantum logic gate structure and the quantum logic gate parameters.

[0071] Specifically, the data compression and encoding are performed by separating the parametric quantum logic gates of the quantum circuit into data and circuit structure.

[0072] For example, suppose a user submits a batch of isomorphic quantum circuits containing various parametric quantum logic gates, such as rotation gates (e.g., Rx, Ry, Rz) and controlled NOT gates (CNOT). To effectively compress the quantum circuits, they are first decomposed into two parts: data and circuit structure. Huffman coding is then applied for optimization, replacing the parameter data in the quantum circuits with their corresponding Huffman codes. At the same time, the structural information of the quantum circuits is also encoded. The encoded quantum circuit data and structural information are then combined into a target byte stream for efficient storage or transmission.

[0073] In summary, by separating the parametric quantum logic gates into data and circuit structures for subsequent data compression encoding, the network bandwidth resources occupied during data transmission can be significantly reduced, the overall data transmission volume can be decreased, and thus the response time and data transmission speed of the entire system can be improved.

[0074] See Figure 3 , Figure 3 A flowchart of a target byte stream generation method provided in an embodiment of the present invention, the method comprising the following steps:

[0075] Step S301: Determine the mapping relationship between the quantum circuit and the target byte; wherein, the mapping relationship is used to characterize the correspondence between the parameters of the isomorphic quantum circuit and the target byte; wherein, the parameters of the isomorphic quantum circuit include the number of isomorphic quantum circuits, the number of qubits required for the isomorphic quantum circuit, the quantum logic gates contained in the isomorphic quantum circuit, the quantum logic gate parameters, the index relationship between the quantum logic gates and the quantum logic gate parameters, and the interaction relationship between the quantum logic gates and the qubits.

[0076] Among them, the parameters of the isomorphic quantum circuit refer to the specific objects involved in compression encoding in the isomorphic quantum circuit; the index relationship between quantum logic gates and their parameters refers to finding the corresponding position relationship of the parameters of each parameterized quantum logic gate in the isomorphic quantum circuit from the byte stream information of the parameter values ​​of the parameterized quantum logic gates.

[0077] Specifically, a mapping relationship is first predefined, which describes how isomorphic quantum circuits and their parametric quantum logic gates are mapped to the target byte.

[0078] For example, see Figure 4 , Figure 4 This is a schematic diagram of client-side encoding provided in an embodiment of the present invention. First, the number of qubits and classical bits of the quantum circuit, the number of isomorphic quantum circuits submitted by the user in batches, and the starting byte position of the stored data are mapped to the header information represented by the first to sixth bytes of the target byte stream. The number of parameters of a single quantum circuit is mapped to the total number of parameters in a single circuit, represented by the seventh to eighth bytes of the target byte stream. The quantum logic gate type is mapped to the gate type information, represented by the ninth byte of the target byte stream. The qubits involved in the quantum logic gate are mapped to the action bit information, represented by the tenth to eleventh bytes of the target byte stream. The parameter index position of the quantum logic gate is mapped to the parameter index information, represented by the twelfth to thirteenth bytes of the target byte stream.

[0079] It is important to emphasize that the logic gate mapping process represented by bytes 9 to 13 is repeated in a loop to achieve the mapping process of all quantum logic gate statements; after all quantum logic gate statements are mapped, the parameter data of the quantum circuit is mapped into the target byte stream.

[0080] Step S302: Determine the byte order and / or the number of bytes required for parameter compression encoding of the isomorphic quantum circuit according to the mapping relationship.

[0081] Specifically, the mapping rules defined in step S301 above are used to further determine the byte order and number of bytes required for compressing and encoding isomorphic quantum circuits and their parametric quantum logic gates into target bytes.

[0082] For example, see Figure 4 First, the number of qubits and classical bits of the quantum circuit are encoded to obtain the first to fourth bytes of compressed information. Then, the number of isomorphic quantum circuits submitted in batches and the starting byte position of the stored data are encoded to obtain the fifth and sixth bytes of compressed information, respectively. The number of parameters of a single quantum circuit is encoded to obtain the seventh to eighth bytes of compressed information. The type of quantum logic gate is encoded to obtain the ninth byte of compressed information. The qubits acting on the quantum logic gate are encoded to obtain the tenth to eleventh bytes of compressed information. The index position of the parameter acting on the quantum logic gate is encoded to obtain the twelfth to thirteenth bytes of compressed information. The encoding process of the ninth to thirteenth bytes is repeated to achieve the compression of all quantum logic gate statements. After all quantum logic gate statements are encoded, the parameter data of the quantum circuit is encoded and stored.

[0083] Step S303: Arrange the compressed and encoded target bytes in a certain byte order to generate a target byte stream.

[0084] Specifically, the target byte information encoded by compression in step S302 is arranged in a predetermined byte order to obtain the target byte stream.

[0085] For example, see Figure 4 The header information processed by compression encoding in step S302, the total number of parameters in a single quantum circuit, the logic gate type, the active bit, the parameter index, the program terminator, and the specific quantum logic gate parameter values ​​are arranged in a predetermined byte order to obtain the target byte stream information.

[0086] In summary, by first determining the mapping relationship between the quantum circuit and the target byte, the consistency and predictability of the compression encoding process can be guaranteed. Then, based on the mapping relationship, the byte order and / or the number of bytes required for the parameter compression encoding of the isomorphic quantum circuit are determined. By further determining the byte order and number of bytes required for the compression encoding of the isomorphic quantum circuit and its parametric quantum logic gates, effective compression of the quantum circuit is achieved, which not only reduces the storage space requirement but also reduces the bandwidth resources required during data transmission, thus improving data transmission efficiency. Finally, the compressed target bytes are arranged in a certain byte order to generate a target byte stream. The ordered byte stream reduces the complexity of subsequent decoding on the server side and also helps maintain the integrity and accuracy of the data. If errors are encountered during data transmission over the network, they can be more easily detected and corrected, enhancing the security and reliability of the system during data transmission.

[0087] In one embodiment of this application, determining the byte order and / or the number of bytes required for parameter compression encoding of the isomorphic quantum circuit according to the mapping relationship includes:

[0088] Determine the initial byte position for storing the parameters of the isomorphic quantum circuit.

[0089] The initial byte position of the parameters of the isomorphic quantum circuit refers to the header information represented by the first byte in the target byte stream, which is the qubit required to encode the isomorphic quantum circuit.

[0090] Specifically, by determining the initial byte positions of the parameters of the isomorphic quantum circuit, the compression encoding and storage of the initial byte position information of the parameters of the isomorphic quantum circuit are initiated.

[0091] Based on the initial byte position and mapping relationship, the number of individual quantum circuits contained in the isomorphic quantum circuit and the number of qubits required by the isomorphic quantum circuit are mapped to the header information represented by a first number of bytes.

[0092] The header information represented by the first number of bytes refers to the parameters of the compressed and encoded isomorphic quantum circuit being represented by the first to sixth bytes of header information.

[0093] Specifically, based on the initial byte position information and mapping relationship determined in the previous step, the relevant parameters of the isomorphic quantum circuit, including the number of individual quantum circuits and the qubits required for the isomorphic quantum circuit, are compressed and encoded into header information represented by the first to sixth bytes.

[0094] The quantum logic gates contained in the isomorphic quantum circuit, the quantum logic gate parameters, the index relationship between the quantum logic gates and the quantum logic gate parameters, and the interaction relationship between the quantum logic gates and the qubits are mapped to the logic gate information represented by a second number of bytes.

[0095] The second number of bytes representing the logic gate information refers to the logic gate information represented by the compressed encoded parameters of the isomorphic quantum circuit in the ninth to thirteenth bytes.

[0096] Specifically, the relevant parameters of the isomorphic quantum circuit, including quantum logic gates, quantum logic gate parameters, the index relationship between quantum logic gates and their parameters, and the interaction relationship between quantum logic gates and qubits, are compressed and encoded into the logic gate information represented by the ninth to thirteenth bytes.

[0097] In summary, firstly, determining the initial byte position of the parameters of the isomorphic quantum circuit ensures that the starting position of the parameter data can be accurately located during the decoding process, avoiding decoding errors caused by unclear positions. Through the above encoding method, the compression efficiency and transmission efficiency of quantum circuit data can be significantly improved, while reducing the complexity of the decoding process.

[0098] See Figure 5 , Figure 5 A flowchart of another information processing method for isomorphic quantum circuits provided in an embodiment of the present invention, the method comprising the following steps:

[0099] Step S501: Based on the mapping relationship between the target byte and the quantum circuit before compression encoding, the target byte stream is decoded to generate the original quantum circuit information.

[0100] Specifically, based on the predefined mapping relationship between the target byte and the quantum circuit during the compression encoding process, the target byte stream is decoded to obtain the original quantum circuit information.

[0101] For example, suppose the server receives the target byte stream "AB12CD34". According to the predefined mapping relationship, "A" may represent a Hadamard gate, "B" may represent a CNOT gate, "12" indicates that these two gates act on qubit 1 and qubit 2 respectively, "CD" represents another set of gate types, and "34" indicates that these gates act on qubit 3 and qubit 4. Through decoding, the original quantum circuit information is recovered, and then the quantum algorithm is executed on the quantum computing platform.

[0102] In summary, when the client encodes the quantum circuit, it converts the quantum circuit into a target byte stream according to a certain mapping relationship. Based on the same mapping relationship, after the server receives the target byte stream, it can easily reconstruct the structure and parameters of the quantum circuit, ensuring that the server can further perform quantum computing tasks on the quantum circuit submitted by the client.

[0103] In one embodiment of this application, before decoding the target byte stream according to the mapping relationship between the target byte and the quantum circuit before compression encoding to generate the original quantum circuit information, the method further includes:

[0104] Obtain the target byte stream from the client.

[0105] Determine the byte stream structure of the target byte stream; wherein the byte stream structure includes the byte order and / or the required number of bytes.

[0106] In this context, byte stream structure refers to a series of rules or attributes that govern how target bytes are composed or arranged.

[0107] Specifically, assuming the quantum circuit is compressed and encoded into a target byte stream on the client side, the server receives the target byte stream to determine its organization, decodes the byte order and the number of bytes occupied by the quantum circuit's operation, and further obtains the original quantum circuit information.

[0108] In summary, by first determining the byte order of the target byte stream and the number of bytes occupied by the quantum circuit operation through the pre-decoding steps, the server can accurately understand the organization of the byte stream sent by the client, providing a solid foundation for the subsequent decoding process. This allows the original quantum circuit information before compression encoding to be accurately restored during the decoding process, ensuring the integrity and accuracy of information transmission. The decoded quantum circuit information is then executed by quantum computing hardware or simulators, providing reliable data support for subsequent quantum computing tasks.

[0109] See Figure 6 , Figure 6 A flowchart of a method for generating raw quantum circuit information provided in an embodiment of the present invention, the method comprising the following steps:

[0110] Step S601: Determine the mapping relationship between the target byte and the quantum circuit; wherein the mapping relationship is used to characterize the correspondence between the target byte and the isomorphic quantum circuit and the parameterized quantum logic gate.

[0111] The mapping relationship is consistent with the correspondence in the compression encoding process.

[0112] Specifically, a predefined set of mapping rules describes how to map target bytes to isomorphic quantum circuits and their parametric quantum logic gates.

[0113] For example, see Figure 7 , Figure 7This is a schematic diagram of server-side decoding provided by an embodiment of the present invention. The process involves mapping the header information (bytes 1-6) of the target byte stream to the number of qubits and classical bits in the quantum circuit structure, the number of isomorphic quantum circuits submitted in batches, and the starting byte position of the stored data; mapping the parameter count information of a single quantum circuit (bytes 7-8) to the number of parameters in a single quantum circuit; mapping the quantum logic gate type information (byte 9) to the gate type of the quantum circuit; mapping the action bit information (bytes 10-11) to the qubits of the quantum logic gate; and mapping the parameter index information (bytes 12-13) to the parameter index position of the quantum logic gate. This mapping process is repeated from bytes 9 to 13 until all quantum logic gate statements in the quantum circuit complete the mapping operation.

[0114] Step S602: Decode the byte stream structure of the target byte stream according to the mapping relationship to obtain the decoded original quantum circuit information.

[0115] Specifically, based on the predefined mapping relationship in step S601 above, the byte order of the target byte stream, and the number of bytes occupied by the operation process of the quantum circuit, the specific information of the isomorphic quantum circuit and the parameterized quantum logic gate is determined.

[0116] For example, see Figure 7 The process involves decoding the compressed information of the first to fourth bytes of the target byte stream to obtain the number of qubits and classical bits of the quantum circuit structure, respectively; decoding the compressed information of the fifth and sixth bytes to obtain the number of submitted isomorphic quantum circuits and the byte position where the stored data begins, respectively; decoding the compressed information of the seventh and eighth bytes to obtain the number of parameters of a single quantum circuit; encoding the compressed information of the ninth byte to obtain the quantum logic gate type; decoding the compressed information of the tenth and eleventh bytes to obtain the qubits that function in the quantum logic gate; decoding the compressed information of the twelfth and thirteenth bytes to obtain the parameter index positions that function in the quantum logic gate; and repeating the decoding process from the ninth to the thirteenth bytes to complete the decoding of all quantum logic gate statements, thus obtaining all the original quantum circuit information.

[0117] In summary, the mapping relationship between target bytes and quantum circuits is first determined. This mapping relationship characterizes the correspondence between the target bytes and isomorphic quantum circuits and parametric quantum logic gates. By clarifying the mapping relationship, it is ensured that subsequent steps can accurately correspond the target bytes (usually compressed or encoded data) to the quantum circuits and their components (such as parametric quantum logic gates). Decoding based on the mapping relationship, byte order, and byte number allows for precise location and decoding of each element in the quantum circuit, including quantum logic gates and their parameters, ensuring the accuracy of the decoding process, reducing unnecessary intermediate steps, and improving the efficiency of the decoding process. Organizing the decoded quantum circuits into a batch isomorphic form simplifies the steps for subsequent quantum circuit analysis or optimization operations and reduces the overall complexity of the data transmission process.

[0118] See Figure 8 , Figure 8 An information processing device for a homogeneous quantum circuit, provided in an embodiment of the present invention, is applied to a client. The device may include an encoding unit 801 and a transmission unit 802, wherein:

[0119] The encoding unit 801 is used to compress and encode the isomorphic quantum circuit into the target byte according to the mapping relationship between the quantum circuit and the target byte, so as to generate a target byte stream.

[0120] Among them, a byte stream refers to a sequence of bytes that can be recognized by a computer system and used for subsequent data transmission and processing; a homogeneous quantum circuit refers to a quantum circuit that has the same structure but contains different parameters.

[0121] Specifically, before compressing and encoding the isomorphic quantum circuit into the target byte according to the mapping relationship between the quantum circuit and the target byte to generate the target byte stream, the method further includes:

[0122] Receive isomorphic quantum circuits submitted by users.

[0123] Determine the parametric quantum logic gate of the isomorphic quantum circuit; wherein the parametric quantum logic gate includes the quantum logic gate structure and the quantum logic gate parameters.

[0124] Specifically, the step of compressing and encoding the isomorphic quantum circuit into the target byte according to the mapping relationship between the quantum circuit and the target byte to generate the target byte stream includes:

[0125] Determine the mapping relationship between quantum circuits and target bytes; wherein the mapping relationship is used to characterize the correspondence between the parameters of the isomorphic quantum circuit and the target byte; wherein the parameters of the isomorphic quantum circuit include the number of isomorphic quantum circuits, the number of qubits required for the isomorphic quantum circuit, the quantum logic gates contained in the isomorphic quantum circuit, the quantum logic gate parameters, the index relationship between the quantum logic gates and the quantum logic gate parameters, and the interaction relationship between the quantum logic gates and the qubits.

[0126] The required byte order and / or number of bytes for parameter compression encoding of the isomorphic quantum circuit are determined based on the mapping relationship.

[0127] The compressed and encoded target bytes are arranged in a certain byte order to generate a target byte stream.

[0128] Specifically, determining the byte order and / or the number of bytes required for parameter compression encoding of the isomorphic quantum circuit based on the mapping relationship includes:

[0129] Determine the initial byte position for storing the parameters of the isomorphic quantum circuit.

[0130] Based on the initial byte position and mapping relationship, the number of individual quantum circuits contained in the isomorphic quantum circuit and the number of qubits required by the isomorphic quantum circuit are mapped to the header information represented by a first number of bytes.

[0131] The quantum logic gates contained in the isomorphic quantum circuit, the quantum logic gate parameters, the index relationship between the quantum logic gates and the quantum logic gate parameters, and the interaction relationship between the quantum logic gates and the qubits are mapped to the logic gate information represented by a second number of bytes.

[0132] The transmission unit 802 is used to transmit the target byte stream from the client to the server.

[0133] See Figure 9 , Figure 9 Another information processing device for isomorphic quantum circuits provided in this embodiment of the invention, applied to a server, the device may include an encoding unit 901, wherein:

[0134] Decoding unit 901 is used to decode the target byte stream according to the mapping relationship between the target byte and the quantum circuit before compression encoding, so as to generate the original quantum circuit information.

[0135] Specifically, before decoding the target byte stream according to the mapping relationship between the target byte and the quantum circuit before compression encoding to generate the original quantum circuit information, the method further includes:

[0136] Obtain the target byte stream from the client.

[0137] Determine the byte stream structure of the target byte stream; wherein the byte stream structure includes the byte order and / or the required number of bytes.

[0138] Specifically, the step of decoding the target byte stream based on the mapping relationship between the target bytes and the quantum circuit before compression encoding to generate the original quantum circuit information includes:

[0139] Determine the mapping relationship between the target byte and the quantum circuit; wherein the mapping relationship is used to characterize the correspondence between the target byte and the isomorphic quantum circuit and the parameterized quantum logic gate.

[0140] The original quantum circuit information is obtained by decoding the byte stream structure of the target byte stream according to the mapping relationship.

[0141] The specific functions and effects of the information processing device based on the aforementioned isomorphic quantum circuits can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the isomorphic quantum circuit information processing device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or it can be stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0142] Please see Figure 10 This specification also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement an information processing method for a homogeneous quantum circuit according to any of the above embodiments. Please refer to [link to documentation]. Figure 10 The computer device can be a classical computer or a quantum computer.

[0143] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform an information processing method for a homogeneous quantum circuit according to any of the above embodiments.

[0144] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0145] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0146] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0147] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0148] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0149] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0150] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0151] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0152] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0153] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0154] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0155] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0156] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. An information processing method of an isomorphic quantum circuit, characterized by, The method applied to the client comprises: According to the mapping relationship between the quantum circuit and the target byte, the isomorphic quantum circuit is compressed and encoded into the target byte to generate a target byte stream; The target byte stream is transmitted from the client to the server.

2. The method of claim 1, wherein, Before the step of according to the mapping relationship between the quantum circuit and the target byte, the isomorphic quantum circuit is compressed and encoded into the target byte to generate a target byte stream, the method further comprises: Receiving the isomorphic quantum circuit submitted by the user; Determining the parametric quantum logic gate of the isomorphic quantum circuit; wherein the parametric quantum logic gate comprises a quantum logic gate structure and a quantum logic gate parameter.

3. The method of claim 1, wherein, The step of according to the mapping relationship between the quantum circuit and the target byte, the isomorphic quantum circuit is compressed and encoded into the target byte to generate a target byte stream comprises: Determining the mapping relationship between the quantum circuit and the target byte; wherein the mapping relationship is used to represent the corresponding relationship between the parameters of the isomorphic quantum circuit and the target byte; wherein the parameters of the isomorphic quantum circuit comprise the number of isomorphic quantum circuits, the number of quantum bits required by the isomorphic quantum circuit, the quantum logic gate contained in the isomorphic quantum circuit, the quantum logic gate parameter, the index relationship between the quantum logic gate and the quantum logic gate parameter, and the action relationship between the quantum logic gate and the quantum bit; According to the mapping relationship, determining the byte order required for parameter compression encoding of the isomorphic quantum circuit and / or the number of bytes required; Arranging the compressed and encoded target byte according to a certain byte order to generate a target byte stream.

4. The method of claim 3, wherein, The step of according to the mapping relationship, determining the byte order required for parameter compression encoding of the isomorphic quantum circuit and / or the number of bytes required comprises: Determining the initial byte position for storing the parameters of the isomorphic quantum circuit; According to the initial byte position and the mapping relationship, mapping the number of single quantum circuits contained in the isomorphic quantum circuit and the number of quantum bits required by the isomorphic quantum circuit into the header information represented by the first number of bytes; Mapping the quantum logic gate contained in the isomorphic quantum circuit, the quantum logic gate parameter, the index relationship between the quantum logic gate and the quantum logic gate parameter, and the action relationship between the quantum logic gate and the quantum bit into the logic gate information represented by the second number of bytes.

5. An information processing method of a homogeneous quantum circuit, characterized by, The method applied to the server comprises: According to the mapping relationship between the target byte and the quantum circuit before compression encoding, the target byte stream is decoded and processed to generate original quantum circuit information.

6. The method of claim 5, wherein, Before the step of according to the mapping relationship between the target byte and the quantum circuit before compression encoding, the target byte stream is decoded and processed to generate original quantum circuit information, the method further comprises: Obtaining the target byte stream of the client; Determining the byte stream structure of the target byte stream; wherein the byte stream structure comprises byte order and / or the number of bytes required.

7. The method of claim 5, wherein, The step of according to the mapping relationship between the target byte and the quantum circuit before compression encoding, the target byte stream is decoded and processed to generate original quantum circuit information comprises: Determining the mapping relationship between the target byte and the quantum circuit; wherein the mapping relationship is used to represent the corresponding relationship between the target byte and the isomorphic quantum circuit and the parametric quantum logic gate; According to the mapping relationship, a byte stream structure of a target byte stream is decoded to obtain decoded original quantum circuit information.

8. An information processing apparatus of a homogeneous quantum circuit, characterized by comprising: The device is applied to a client and includes: An encoding unit configured to compress and encode the same quantum circuit into the target byte according to a mapping relationship between the quantum circuit and the target byte to generate a target byte stream; A transmission unit configured to transmit the target byte stream from the client to a server.

9. An information processing apparatus of a homogeneous quantum circuit, characterized by comprising: The device is applied to a server and includes: A decoding unit configured to decode the target byte stream according to a mapping relationship between the target byte and the quantum circuit before compression and encoding to generate original quantum circuit information.

10. An electronic device, comprising: The device includes: A processor and a memory; The processor and the memory are connected, wherein the memory is configured to store a computer program, and the processor is configured to call the computer program to execute the method in any one of claims 1-4 or 5-7.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program includes program instructions, which, when executed by a processor, execute the method in any one of claims 1-4 or 5-7.

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