Gating circuit, driving circuit, display integrated circuit and display panel

Abstract

The embodiment of the invention provides a gating circuit, a driving circuit, a display integrated circuit and a display panel. The power consumption of a display screen for picture display can be reduced. The gating circuit comprises a reading circuit and an output circuit, the first input end of the reading circuit is coupled with the output end of the generation circuit, and the reading circuit receives the first control signal; the second input end of the reading circuit is used for receiving a first refreshing control signal; the output end of the reading circuit is coupled with the first input end of the output circuit; the output end of the output circuit is coupled with the output end of the gating circuit and is used for outputting a second control signal; the reading circuit is used for transmitting a first refresh control signal to a first input end of the output circuit when the first control signal is a first level signal; and the output circuit is used for outputting the first level signal as a second control signal when the first refresh control signal is a third level signal, and outputting the second level signal as the second control signal when the first refresh control signal is a fourth level signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate-on circuit, a driving circuit, a display integrated circuit and a display panel. BACKGROUND

[0002] A display screen arranged in an electronic device (for example, a mobile phone) is used to display pictures to a user. The display screen includes a display panel, and a plurality of pixel circuits are arranged on the display panel. When the display screen displays pictures, the pixel circuits can be driven to work by a driving circuit at a certain refresh rate. At present, the power consumption of the display screen is high when the display screen displays pictures. SUMMARY

[0003] The present application provides a gate-on circuit, a driving circuit, a display integrated circuit and a display panel, which can reduce the power consumption of the display screen when the display screen displays pictures.

[0004] In a first aspect, an embodiment of the present application provides a gate-on circuit, which is applied to a gate driving circuit including a generating circuit, and an output end of the generating circuit is used to output a first control signal; the first control signal is a first level signal or a second level signal, the first level signal can control a target transistor in a pixel circuit corresponding to the generating circuit to be turned off, and the second level signal can control the target transistor in the pixel circuit to be turned on; the gate-on circuit includes a reading circuit and an output circuit, wherein a first input end of the reading circuit is coupled with the output end of the generating circuit to receive the first control signal; a second input end of the reading circuit is used to receive a first refresh control signal, the first refresh control signal is a third level signal or a fourth level signal, the third level signal is used to instruct the pixel circuit to refresh, and the fourth level signal is used to instruct the pixel circuit not to refresh; an output end of the reading circuit is coupled with a first input end of the output circuit; an output end of the output circuit is coupled with an output end of the gate-on circuit, and is used to output a second control signal; the reading circuit is used to: when the first control signal is the first level signal, transmit the first refresh control signal to the first input end of the output circuit; and the output circuit is used to: when the first refresh control signal is the third level signal, output the first control signal as the second control signal, and when the first refresh control signal is the fourth level signal, output the first level signal as the second control signal. The gate-on circuit can support the display screen to use different refresh rates for picture refresh in different regions, thereby reducing the power consumption of the display screen when the display screen displays pictures.

[0005] For example, when the target transistor to be controlled in the pixel circuit is an IGZO TFT that is turned on at a high voltage, the first level signal can be a low level signal, and the second level signal can be a high level signal.

[0006] For example, the third level signal of the first refresh control signal can be a low level signal, and the fourth level signal can be a high level signal.

[0007] In one possible implementation, the output circuit specifically includes a switching sub-circuit and an output sub-circuit. The first input terminal of the switching sub-circuit is coupled to the first input terminal of the output circuit to receive a first refresh control signal. The output terminal of the output sub-circuit is coupled to the output terminal of the output circuit. The switching sub-circuit is configured to: operate the control signal output sub-circuit when the first refresh control signal is a third-level signal, and stop operating the control signal output sub-circuit when the first refresh control signal is a fourth-level signal. The output sub-circuit is configured to: output the first control signal as a second control signal when operating, and output the first-level signal as a second control signal when stopping. This implementation provides a more specific structure for the output circuit, enabling it to output the first control signal as a second control signal when the first refresh control signal is a third-level signal, and to output the first-level signal as a second control signal when the first refresh control signal is a fourth-level signal.

[0008] In one possible implementation, the generation circuit includes: a first transistor, a second transistor, and a third transistor. The first terminals of the first and third transistors are coupled to a high-voltage supply terminal. The second terminals of the first and second transistors are coupled to the output terminal of the generation circuit. The second terminal of the second transistor is coupled to a low-voltage supply terminal. The second terminal of the third transistor is coupled to the gate of the first transistor. The gating circuit further includes: a second input terminal of a switching sub-circuit coupled to the gate of the first transistor, and an output terminal coupled to the first input terminal of a signal output sub-circuit. The output sub-circuit includes: a fourth transistor, a fifth transistor, and a sixth transistor. The first terminals of the fourth and sixth transistors are coupled to the high-voltage supply terminal. The second terminals of the fourth and fifth transistors are coupled to the output terminal of the output sub-circuit. The second terminal of the fifth transistor is coupled to the low-voltage supply terminal. The second terminal of the sixth transistor and the gate of the fourth transistor are coupled to the first input terminal of the output sub-circuit. The gate of the fifth transistor is used to couple to the gate of the second transistor. The gate of the sixth transistor is used to couple to the gate of the third transistor. This implementation provides a specific structure for the output sub-circuit, enabling it to output a first control signal as a second control signal when it is working, and to output a first level signal as a second control signal when it stops working.

[0009] In one possible implementation, the switching sub-circuit includes a seventh transistor; wherein the gate of the seventh transistor is coupled to a first input terminal of the switching sub-circuit, the first terminal of the seventh transistor is coupled to a second input terminal of the switching sub-circuit, and the second terminal of the seventh transistor is coupled to the output terminal of the switching sub-circuit. This implementation provides a specific structure for the switching sub-circuit, enabling it to operate when the first refresh control signal is a third-level signal and to deactivate when the first refresh control signal is a fourth-level signal.

[0010] In one possible implementation, the readout circuit includes an eighth transistor, wherein the gate of the eighth transistor is coupled to a first input terminal of the readout circuit, a first terminal of the eighth transistor is coupled to a second input terminal of the readout circuit, and a second terminal of the eighth transistor is coupled to an output terminal of the readout circuit. The eighth transistor can be implemented using an LTPS TFT or an IGZO TFT.

[0011] In one possible implementation, the readout circuit further includes: a ninth transistor; a first terminal of the eighth transistor is coupled to a second input terminal of the readout circuit, comprising: the first terminal of the eighth transistor being coupled to the first terminal of the ninth transistor, and the second terminal of the ninth transistor being coupled to the second input terminal of the readout circuit; the gate of the ninth transistor is used to receive a first signal, the first signal being used to control the ninth transistor to conduct before the first control signal changes from a first level signal to a second level signal. The ninth transistor can be implemented using an LTPS TFT or an IGZO TFT.

[0012] In one possible implementation, the readout circuit further includes: a tenth transistor and a first capacitor; a first terminal of the eighth transistor is coupled to a second input terminal of the readout circuit, including: the first terminal of the eighth transistor is coupled to the first terminal of the tenth transistor, and the second terminal of the tenth transistor is coupled to the second input terminal of the readout circuit; a first terminal of the first capacitor is coupled to the second terminal of the eighth transistor, and the second terminal of the first capacitor is coupled to a high-voltage supply terminal; the gate of the tenth transistor is used to receive a second signal, the second signal being used to control the tenth transistor to be turned on for at least a preset first duration before the first control signal is converted from a first level signal to a second level signal. The tenth transistor can be implemented using an LTPS TFT or an IGZO TFT.

[0013] In one possible implementation, the gating circuit further includes a voltage regulator circuit, the first input terminal of which is coupled to the output terminal of the output circuit; the voltage regulator circuit is used to: regulate the voltage of the second control signal output by the output circuit to obtain a third control signal.

[0014] In one possible implementation, the voltage regulator circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor. The first terminal of the eleventh transistor is coupled to the first input and output terminals of the voltage regulator circuit, and its second terminal is coupled to a low-voltage supply terminal. Its gate is coupled to the first terminal of the twelfth transistor, and the second terminal of the twelfth transistor is coupled to the first terminal of the thirteenth transistor. The second terminal of the thirteenth transistor is used to receive a second refresh control signal, which is out of phase with the first refresh control signal. The first terminal of the second capacitor is coupled to the gate of the eleventh transistor, and its second terminal is coupled to the low-voltage supply terminal. The gate of the twelfth transistor is used to receive a first control signal, and the gate of the thirteenth transistor is used to receive a third signal. The third signal is used to control the thirteenth transistor to be turned on for at least a preset first duration before the first control signal changes from a first level signal to a second level signal.

[0015] In one possible implementation, the voltage regulator circuit includes: a fourteenth transistor, the gate of which is coupled to the output of the readout circuit, a first terminal of which is coupled to a low voltage supply terminal, and a second terminal of which is coupled to the first input and output of the output circuit.

[0016] In one possible implementation, the system further includes a pixel circuit comprising a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a third capacitor. The first terminal of the third capacitor and the first terminal of the twentieth transistor are respectively coupled to a first power supply terminal. The first terminal of the eighteenth transistor, the second terminal of the nineteenth transistor, and the second terminal of the twentieth transistor are coupled together. The second terminal of the third capacitor, the gate of the eighteenth transistor, and the first terminal of the twenty-first transistor are coupled together. The second terminal of the fifteenth transistor, the first terminal of the sixteenth transistor, and the second terminal of the twenty-first transistor are coupled together. The first terminal of the fifteenth transistor, the first terminal of the seventeenth transistor, and the second terminal of the eighteenth transistor are coupled together. The second terminal of the seventeenth transistor is used to couple to the anode of a light-emitting diode. The second terminal of the sixteenth transistor is coupled to a first reference voltage. Specifically, the aforementioned 21st transistor can be turned off before the 15th transistor is turned off, thereby ensuring that the recoil effect caused by the falling edge change of the gate drive signal of the 15th transistor will not affect the gate voltage of the 18th transistor. Moreover, the 21st transistor can maintain perfect consistency in the transitions of the hold frame and the data write frame, while simultaneously being turned on during the light emission process. This ensures that the voltage disturbance written to the gate of the 18th transistor in the hold frame and the data write frame is consistent, and that the stress state of the 21st transistor is consistent. This reduces the impact of the 21st transistor's transitions on the gate voltage of the 18th transistor, thereby reducing or eliminating screen splitting issues after partition refresh (RA).

[0017] In one possible implementation, it also includes: a twenty-second transistor, the first terminal of which is coupled to the first terminal of the eighteenth transistor, and the second terminal of which is coupled to a third reference voltage.

[0018] In one possible implementation, it also includes: a twenty-third transistor, the first terminal of which is coupled to the second terminal of the seventeenth transistor, the second terminal of which is coupled to a second reference voltage.

[0019] Secondly, embodiments of this application provide a pixel circuit, comprising: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a third capacitor. The first terminal of the third capacitor and the first terminal of the twentieth transistor are respectively coupled to a first power supply terminal. The first terminal of the eighteenth transistor, the second terminal of the nineteenth transistor, and the second terminal of the twentieth transistor are coupled together. The second terminal of the third capacitor, the gate of the eighteenth transistor, and the first terminal of the twenty-first transistor are coupled together. The second terminal of the fifteenth transistor, the first terminal of the sixteenth transistor, and the second terminal of the twenty-first transistor are coupled together. The first terminal of the fifteenth transistor, the first terminal of the seventeenth transistor, and the second terminal of the eighteenth transistor are coupled together. The second terminal of the seventeenth transistor is used to couple to the anode of a light-emitting diode. The second terminal of the sixteenth transistor is coupled to a first reference voltage. This pixel circuit is applicable to displays that use the same refresh rate, and is particularly suitable for displays that use different refresh rates for different zones. Specifically, the aforementioned 21st transistor can be turned off before the 15th transistor is turned off, thereby ensuring that the recoil effect caused by the falling edge change of the gate drive signal of the 15th transistor will not affect the gate voltage of the 18th transistor. Moreover, the 21st transistor can maintain perfect consistency in the transitions of the hold frame and the data write frame, while simultaneously being turned on during the light emission process. This ensures that the voltage disturbance written to the gate of the 18th transistor in the hold frame and the data write frame is consistent, and that the stress state of the 21st transistor is consistent. This reduces the impact of the 21st transistor's transitions on the gate voltage of the 18th transistor, thereby reducing or eliminating screen splitting issues after partition refresh (RA).

[0020] In one possible implementation, it also includes: a twenty-second transistor, the first terminal of which is coupled to the first terminal of the eighteenth transistor, and the second terminal of which is coupled to a third reference voltage.

[0021] In one possible implementation, it also includes: a twenty-third transistor, the first terminal of which is coupled to the second terminal of the seventeenth transistor, the second terminal of which is coupled to a second reference voltage.

[0022] Thirdly, embodiments of this application provide a driving circuit, including the gating circuit of any one of the first aspects.

[0023] Fourthly, embodiments of this application provide a display integrated circuit, including the gating circuit of any one of the first aspects.

[0024] Fifthly, embodiments of this application provide a display panel including the gating circuit of any one of the first aspects.

[0025] In a sixth aspect, embodiments of this application provide a display panel including the pixel circuitry of any of the second aspects.

[0026] In a seventh aspect, embodiments of this application provide an electronic device including the gating circuit of any one of the first aspects.

[0027] Eighthly, embodiments of this application provide an electronic device including the pixel circuit of any of the second aspects. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0030] Figure 2A This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0031] Figure 2B Provided for the embodiments of this application Figure 2A The diagram shows the timing sequence of the pixel circuit.

[0032] Figure 3A This is a schematic diagram of the pixel circuit driving principle provided in an embodiment of this application;

[0033] Figure 3B A schematic diagram illustrating the connection relationship between the gate driving circuit and the pixel circuit in the display panel provided in an embodiment of this application;

[0034] Figure 3C A schematic diagram of the gate drive signal of transistor T1 in the pixel circuit during the progressive drive pixel circuit refresh provided in the embodiments of this application;

[0035] Figure 4A This is a schematic diagram of high and low frequency region division provided in an embodiment of this application;

[0036] Figure 4B A schematic diagram of the refresh control signal provided in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram of the gate drive signal of transistor T1 in each row pixel circuit when different refresh rates are achieved in high and low frequency regions, as provided in an embodiment of this application.

[0038] Figure 6 A schematic diagram illustrating the connection relationship between the gate driving circuit and the pixel circuit in the display panel after adding a gating circuit, as provided in the embodiments of this application.

[0039] Figure 7 A schematic diagram of a gating circuit provided in an embodiment of this application;

[0040] Figure 8 Another schematic diagram of the gating circuit provided in the embodiments of this application;

[0041] Figure 9 This is a schematic diagram of a third structure of the gating circuit provided in an embodiment of this application;

[0042] Figure 10A and Figure 10B A schematic diagram illustrating a possible implementation of the GOAX signal provided in an embodiment of this application;

[0043] Figure 11 This is a schematic diagram of a fourth structure of the gating circuit provided in the embodiments of this application;

[0044] Figure 12 This is a schematic diagram of a fourth structure of the gating circuit provided in the embodiments of this application;

[0045] Figure 13 This is a schematic diagram of a fourth structure of the gating circuit provided in the embodiments of this application;

[0046] Figure 14 This is a schematic diagram of a fourth structure of the gating circuit provided in the embodiments of this application;

[0047] Figure 15 A schematic diagram of the generation circuit provided in an embodiment of this application;

[0048] Figure 16 Examples provided for embodiments of this application Figure 2A The diagram shows a simulation of the pixel circuit's operation.

[0049] Figure 17 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0050] Figure 18 Provided for the embodiments of this application Figure 17 The diagram shows the timing sequence of the pixel circuit during the data writing frame.

[0051] Figure 19 Provided for the embodiments of this application Figure 17 The diagram shows the timing sequence of the pixel circuit in the holding frame.

[0052] Figure 20 Provided for the embodiments of this application Figure 17 The diagram shows a simulation of the pixel circuit's operation. Detailed Implementation

[0053] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.

[0054] The gating circuit, driving circuit, display integrated circuit, and display panel of this application embodiment can be applied to electronic devices equipped with a display screen, such as mobile phones, personal computers (PCs), tablet computers (PADs), wearable devices, smart screens, and in-vehicle devices.

[0055] Figure 1 A schematic diagram of the structure of an electronic device 100 is shown. The electronic device 100 may include a processor 110, an internal memory 121, a display screen 194, etc.

[0056] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware. For example, as shown in 1, the electronic device 100 may also include: an external memory interface 120, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0057] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0058] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0059] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0060] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0061] It is understood that the interface connection relationships between the modules illustrated in the embodiments of the present invention are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0062] Internal memory 121 can be used to store computer executable program code, which includes instructions. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.), etc. The data storage area may store data created during the use of electronic device 100 (such as audio data, phonebook, etc.). Furthermore, internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. Processor 110 executes various functional applications and data processing of electronic device 100 by running instructions stored in internal memory 121 and / or instructions stored in memory located in the processor.

[0063] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 100 may include one or N displays 194, where N is a positive integer greater than 1.

[0064] A display panel can include multiple pixel circuits. Taking a low-temperature polycrystalline oxide (LTPO) screen as an example, each pixel circuit can be implemented using an 8T1C structure, meaning the pixel circuit includes eight transistors (T) and one capacitor (C). Figure 2AAs shown, the pixel circuit of 8T1C may include transistors T1 to T8 and capacitor C0. In some embodiments, light-emitting diode D is part of the pixel circuit; in other embodiments, the pixel circuit may not include light-emitting diode D.

[0065] like Figure 2A As shown, transistors T1 and T2 can specifically be indium gallium zinc oxide (IGZO) TFTs, and transistors T3 to T8 can be low-temperature polycrystalline silicon (LTPS) TFTs. Among the aforementioned transistors T1 to T8, transistor T4 can specifically be a driving thin-film transistor (DTFT) used to drive the light-emitting diode D to emit light, while the other transistors can be switching thin-film transistors (STFTs) used to control the on / off state of their respective circuits.

[0066] The aforementioned thin-film transistor (TFT) belongs to the field-effect transistor (FET) family; therefore, the three electrodes of a TFT are the source, gate, and drain. The TFT can be controlled to turn on and off using a control signal input from the gate. Each transistor in the following embodiments of this application includes a first terminal, a second terminal, and a gate. If the first terminal of a transistor is the source, then the second terminal is the drain. Alternatively, if the first terminal of a transistor is the drain, then the second terminal is the source. Whether the first terminal of each transistor is specifically the source or the drain can be determined based on the actual function implemented by the transistor in the circuit. Similarly, whether the second terminal of each transistor is specifically the source or the drain is also determined based on the actual function implemented by the transistor in the circuit. The specific electrode attributes of the first and second terminals are not limited in the description of the embodiments of this application.

[0067] The coupling referred to in the embodiments of this application can be a direct connection, an indirect connection through devices (such as capacitors, resistors, or inductors) or circuits, or an indirect coupling connection, etc., and the embodiments of this application are not limited thereto. The aforementioned indirect coupling connection refers to the interaction between two devices through the transmission of electromagnetic fields or electromagnetic waves. For example, the interaction between devices such as transformers and inductive couplers in a circuit is indirect coupling.

[0068] See Figure 2AThe pixel circuit of the 8T1C specifically includes: the first terminal of capacitor C0 and the first terminal of transistor T6 are respectively coupled to the first power supply terminal VDD; the first terminal of transistor T4, the second terminal of transistor T5, the second terminal of transistor T6, and the first terminal of transistor T7 are coupled to point A1; the second terminal of capacitor C, the gate of transistor T4, the second terminal of transistor T1, and the first terminal of transistor T2 are coupled to point A2; the first terminal of transistor T1, the second terminal of transistor T4, and the first terminal of transistor T3 are coupled to point A3; the second terminal of transistor T3, the anode of light-emitting diode D, and the first terminal of transistor T8 are coupled to point A4; the second terminal of transistor T2 is coupled to the first reference voltage Vre. f1, the second terminal of transistor T8 is coupled to the second reference voltage Vref2, the second terminal of transistor T7 is coupled to the third reference voltage Vref3, and the cathode of light-emitting diode D is coupled to the second power supply terminal VSS; the gates of transistors T3 and T6 are used to receive the dimming signal EM, the gate of transistor T1 is used to receive the gate control signal Ngate, the gates of transistors T7 and T8 are used to receive the positive voltage reset signal ResetH, the gate of transistor T2 is used to receive the gate reset signal ResetN, and the gate of transistor T5 is used to receive the data write signal Pgate; the second terminal of transistor T5 is used to receive the drive signal Data of the pixel circuit. The dimming signal EM can be, for example, a PWM dimming signal. The gate reset signal Reset N is specifically used to control the gate of transistor T4 (i.e., the DTFT in the pixel circuit) when transistor T2 is turned on. The data write signal Pgate is used to control transistor T5 to be turned on, thereby writing the drive signal Data into the pixel circuit.

[0069] Figure 2A The timing diagram of the pixel circuit shown is as follows: Figure 2B As shown, it will not be elaborated further here.

[0070] It should be noted that the above display panel types and pixel circuit structures are merely examples. The gating circuit of this application embodiment can be applied to any display screen that requires regional division and adaptive refresh rate settings for different regions.

[0071] like Figure 3AAs shown, the display screen's display process includes: the processor can pre-set the screen's brightness; the Display Driver IC (DDIC) stores the corresponding brightness information; after the processor sends the display data to the DDIC, the DDIC determines the corresponding source data and gate driven on array (GOA) data based on the brightness information and the display data, and transmits the source data and GOA data to the pixel circuits in the display panel. The source data includes the drive signal Data for each pixel circuit; the GOA data includes the aforementioned dimming signal EM, gate control signal Ngate, positive voltage reset signal Reset H, gate reset signal Reset N, data write signal Pgate, etc., as well as the first reference voltage Vref1 to the third reference voltage Vref3. Furthermore, the DDIC can also provide the pixel circuits with the aforementioned first power supply terminal VDD and second power supply terminal VSS.

[0072] In some embodiments, the DDIC may specifically include: a gate drive circuit, a source drive circuit, and a display power management chip (PMIC). The gate drive circuit can be used to generate GOA data, the source drive circuit can be used to generate source data, and the PMIC can be used to provide a first power supply terminal VDD and a second power supply terminal VSS.

[0073] In some embodiments, the gate driving circuit is responsible for horizontal operation, used to control the switching of transistors in a row of pixel circuits in the display panel; the source driving circuit is responsible for vertical operation, and can control the brightness, grayscale, color, etc. of individual pixel circuits (pixels) through voltage. It is understood that in some other embodiments, the gate driving circuit can also control the switching of transistors in each pixel circuit in the display panel, and the embodiments of this application are not limited thereto.

[0074] like Figure 3B As shown, if transistor switching control is performed on a row of pixel circuits in a display panel, the gate driving circuit can provide a generation circuit 1 for generating a gate control signal Ngate for each row of pixel circuits. The output of generation circuit 1 can be coupled to the gate of transistor T1 of each pixel circuit in the corresponding row. The gate driving circuit can also provide a generation circuit 2 for generating a gate reset signal ResetN for each row of pixel circuits. The output of generation circuit 2 can be coupled to the gate of transistor T2 of each pixel circuit in the corresponding row.

[0075] Understandably, if transistor switching control is performed for each pixel circuit in the display panel, the gate driving circuit can be equipped with a generation circuit 1 for generating a gate control signal Ngate for each pixel circuit, and the output of the generation circuit 1 can be coupled to the gate of the transistor T1 of the corresponding pixel circuit; the gate driving circuit can be equipped with a generation circuit 2 for generating a gate reset signal ResetN for each pixel circuit, and the output of the generation circuit 2 can be coupled to the gate of the transistor T2 of the corresponding pixel circuit.

[0076] It should be noted that, for ease of explanation in subsequent embodiments, the signal generated by generation circuit 1 in this embodiment is distinguished from the signal received by the gate of transistor T1 corresponding to generation circuit 1. The gate control signal generated by generation circuit 1 is referred to as the original gate control signal, denoted by Ngate-1, while the signal received by the gate of transistor T1 in the pixel circuit corresponding to generation circuit 1 is still referred to as the gate control signal, denoted by Ngate. Similarly, in this embodiment, the gate reset signal generated by generation circuit 2 is referred to as the original gate reset signal, denoted by ResetN-1, while the signal received by the gate of transistor T2 in the pixel circuit corresponding to generation circuit 2 is still referred to as the gate reset signal, denoted by ResetN. See [link to relevant documentation] for details. Figure 3B As shown in the image.

[0077] It should be noted that in some embodiments, when the display screen refreshes the image, the pixel circuits in each row are generally refreshed sequentially. Therefore, the time it takes for different row pixel circuits to receive the same signal is different. For this reason, in Figure 3B In Ngate(i), Ngate-1(i), ResetN(i), and ResetN-1(i), i represents the corresponding row (pixel circuit) in the display screen to distinguish signals from different rows. For example, Ngate(1) represents the gate control signal Ngate received by transistor T1 of the pixel circuit in the first row, Ngate(m) represents the gate control signal Ngate received by transistor T1 of the pixel circuit in the m-th row, and so on.

[0078] Refresh rate is an important parameter for display screens. It refers to the number of times the screen updates its display per second. A higher refresh rate means faster image updates and a smoother visual experience. Refresh rate is usually expressed in Hertz (Hz).

[0079] In some embodiments, the entire display uses the same refresh rate. That is, the entire screen updates its image at the same refresh rate, for example... Figure 3BThe gate drive circuit shown can achieve the same refresh frequency for all pixel circuits in the display screen. Taking the display screen refreshed sequentially line by line as an example, the gate control signal Ngate(i) received by the transistor T1 of each line of pixel circuit is... Figure 3B For example, the gate control signal Ngate-1(i) output by the generation circuit 1 corresponding to each row of pixel circuits. Figure 3C As shown.

[0080] However, for the images displayed on a screen, some areas are relatively static, while others are dynamic. Therefore, to reduce power consumption during image display, some embodiments can adaptively refresh the screen at different refresh rates for different areas, achieving precise control over the screen's refresh rate. In some examples, the screen can be divided into zones based on the "row" pixel circuitry of the display.

[0081] Taking a mobile phone as an example, in some embodiments, as shown in Figure 4, the phone's display screen can be divided into three areas from top to bottom: low-frequency area 1, high-frequency area, and low-frequency area 2. Low-frequency area 1 displays relatively static images, such as the status bar; the high-frequency area displays dynamic images, such as videos; and low-frequency area 2 displays static images, such as the back button and home button. Each of these three areas can be updated using its corresponding refresh rate. Specifically, the faster the image changes, the higher the refresh rate. For example, low-frequency area 1 and low-frequency area 2 have relatively static images with a refresh rate of 10Hz, while the high-frequency area has dynamic images with a refresh rate of 120Hz.

[0082] It should be noted that, Figure 4A The high and low frequency division shown is merely an example. The number, size, and refresh rate of each division can adapt to different screen displays. In other words, for the same row of pixels on the screen, it might be located in the area with refresh rate a1 when displaying image 1, but in the area with refresh rate a2 when displaying image 2. The specific division of different frequency areas on the screen can be implemented by the display IC or the processor of the electronic device, such as the AP.

[0083] By using different refresh rates for different areas of the display, the power consumption of the display can be reduced while ensuring the display effect.

[0084] To enable different regions to refresh the screen using corresponding refresh rates, this embodiment provides a first refresh control signal SW1 for each region based on its refresh rate. High and low levels indicate whether the pixel circuitry in that region is refreshed. In related technologies, if the display area is divided into only two refresh rate regions—high-frequency and low-frequency—the first refresh control signal SW1 can also be called a high / low frequency region control signal. This embodiment does not limit the provider of the first refresh control signal SW1 in its implementation. For example, the first refresh control signal SW1 can be provided by the display IC or the processor of the electronic device, such as an application processor (AP).

[0085] See Figure 4B In the following embodiments of this application, a high-level signal of the first refresh control signal SW1 indicates that the pixel circuits in the region are not refreshed, and a low-level signal indicates that the pixel circuits in the region are refreshed. It can be understood that in other embodiments, the first refresh control signal SW1 can indicate that the pixel circuits in the region are not refreshed by a low-level signal, and that the pixel circuits in the region are refreshed by a high-level signal.

[0086] In some subsequent embodiments, a second refresh control signal SW2 is also used, which is combined here. Figure 4B First, an exemplary description is provided. The second refresh control signal SW2 can also be provided by the region according to the refresh rate of the region. The second refresh control signal SW2 can be the inverted signal of the first refresh control signal SW1. That is, when the first refresh control signal SW1 is a high-level signal, the second refresh control signal SW2 is a low-level signal, and when the first refresh control signal SW1 is a low-level signal, the second refresh control signal SW2 is a high-level signal. In specific implementations, this application embodiment does not limit who provides the above-mentioned second refresh control signal SW2. For example, the above-mentioned second refresh control signal SW2 can also be provided by the display IC or the processor of the electronic device, such as the AP. Alternatively, the second refresh control signal SW2 can also be obtained by inverting the first refresh control signal SW1.

[0087] Furthermore, in order to achieve screen refresh using corresponding refresh rates in different regions, the gate drive circuit needs to output GOA data normally for pixel circuits in areas that require refresh (e.g., high-frequency regions), and not output GOA data for pixel circuits in areas that do not require refresh (e.g., low-frequency regions). Figure 2ATaking the pixel circuit shown as an example, the pixel circuit located in the low-frequency region needs to provide a low-level signal as the gate control signal Ngate to transistor T1 and a low-level signal as the gate reset signal ResetN to transistor T2. The pixel circuit located in the high-frequency region needs to provide a normal gate control signal Ngate to transistor T1 and a normal gate reset signal ResetN to transistor T2.

[0088] See Figure 5 The diagram illustrates the relationship between the gate control signal Ngate and the first refresh control signal SW1 received by transistor T1 in each row of pixel circuits. Assuming the display screen has n rows of pixels, and refresh is performed on a row-by-row basis, a low level of the first refresh control signal SW1 indicates that the pixel circuit in that area is being refreshed, while a high level indicates that the pixel circuit in that area is not being refreshed. Therefore, in the low-frequency region 1 (rows 1 to m1-1) and the low-frequency region 2 (rows m2+1 to n), the first refresh control signal SW1 can be high. In this case, the gate drive circuit needs to provide a low-level signal as the gate control signal Ngate to transistor T1 in each row of pixel circuits. In the high-frequency region (rows m1 to m2), the first refresh control signal SW1 can be low, and the gate drive circuit needs to provide a normal gate control signal Ngate to transistor T1 in each row of pixel circuits. The control logic between the gate control signal ResetN of transistor T2 and the first refresh control signal SW1 is similar to that of the gate control signal Ngate of transistor T1, and will not be listed separately here.

[0089] To implement the above logic and support different refresh rates for different areas of the display screen, a gating circuit is provided in this embodiment.

[0090] by Figure 2A Taking the pixel circuit shown as an example, a gating circuit needs to be set between the gate of transistor T1 in each pixel circuit and its corresponding generation circuit 1, and a gating circuit needs to be set between the gate of transistor T2 in each pixel circuit and its corresponding generation circuit 2. It can be understood that if the display screen is controlled according to a row of pixel circuits, that is, each row of pixel circuits has one generation circuit, then a common gating circuit can be set for transistor T1 in each row of pixel circuits, and a common gating circuit can be set for transistor T2 in each row of pixel circuits.

[0091] In some embodiments, the gating circuit can be disposed in the gate driving circuit, for example... Figure 6 As shown. Figure 6 The text specifically illustrates the use of... Figure 3BThe gate driving circuit shown is an example of a gate driving circuit with an added gating circuit. Each row of pixel circuits has one gating circuit 1 and one gating circuit 2. The input of gating circuit 1 for each row of pixel circuits is coupled to the output of the generation circuit 1 for that row of pixel circuits, and the output of gating circuit 1 is coupled to the gate of transistor T1 in each pixel circuit of that row. The input of gating circuit 2 for each row of pixel circuits is coupled to the output of the generation circuit 2 for that row of pixel circuits, and the output of gating circuit 2 is coupled to the gate of transistor T2 in each pixel circuit of that row.

[0092] exist Figure 6 In the gate drive circuit, generation circuit 1 and generation circuit 2 of each row of pixel circuits aim to refresh the pixel circuit of that row normally, and generate normally respectively. Figure 3B The original gate drive signal Ngate-1 and the original gate reset signal ResetN-1 shown in the figure mean that, Figure 6 The generation circuit 1 and generation circuit 2 of each row of pixel circuits are connected to Figure 3B The generation circuit 1 and generation circuit 2 in the diagram have the same function and output the same signal.

[0093] The gating circuit 1 is used to continuously output a low-level signal when the first refresh control signal SW1 is high, as the gate control signal Ngate of transistor T1. When the first refresh control signal SW1 is low, it normally outputs the original gate control signal Ngate-1, including possible low-level signals and high pulse signals of the original gate control signal Ngate-1, as the gate control signal Ngate of transistor T1. When the first refresh control signal SW1 changes, it performs judgment and output to avoid the currently displayed row high pulse being abnormally cut off.

[0094] The gating circuit 2 is used to continuously output a low-level signal when the first refresh control signal SW1 is high, as the gate reset signal ResetN of transistor T2. When the first refresh control signal SW1 is low, it normally outputs the original gate reset signal Reset N-1, including possible low-level signals and high pulse signals of the original gate reset signal Reset N-1, as the gate reset signal ResetN of transistor T2. When the first refresh control signal SW1 changes, it performs judgment and output to avoid the currently displayed row high pulse being abnormally cut off.

[0095] It should be noted that, Figure 6The example of setting one gating circuit 1 and one gating circuit 2 per row is merely illustrative, based on the premise that the screen refresh of each area is controlled on a per-row pixel circuit basis. In other embodiments, if the screen refresh of each area is controlled according to other control units such as half-row pixel circuits, pixel circuit groups composed of a preset number of pixel circuits, or individual pixel circuits, then one gating circuit 1 and one gating circuit 2 can be set for each control unit. For specific circuit structures, please refer to [reference needed]. Figure 6 Adaptive adjustments have been made, and the embodiments in this application will not be listed one by one.

[0096] It should be noted that, Figure 6 The inclusion of the gating circuit within the gate drive circuit is merely an example. In other embodiments, the gating circuit may be independent of the gate drive circuit. For instance, all gating circuits of the display panel may be configured as a single gating device within the DDIC, or independently of the DDIC.

[0097] It should be noted that the above embodiments use pixel circuits as an example. Figure 2A Taking the circuit shown as an example, in other pixel circuits, the transistors T1 and T2 mentioned above can be replaced with transistors in other pixel circuits that determine whether the other pixel circuit is refreshed. Correspondingly, the generation circuit mentioned above can also be replaced with a circuit that outputs a control signal to the gate of the transistor.

[0098] The following provides an exemplary description of the implementation of the gating circuit.

[0099] Figure 7 This is a schematic diagram of one implementation structure of a gating circuit. For example... Figure 7 As shown, the gating circuit includes: a reading circuit 71 and an output circuit 72.

[0100] Specifically, the first input terminal in11 of the reading circuit 71 is coupled to the output terminal out1 of the generation circuit corresponding to the gating circuit, and receives the first control signal ctrl1; the second input terminal in12 of the reading circuit is used to receive the first refresh control signal SW1, which is either a third-level signal or a fourth-level signal. The third-level signal is used to indicate that the pixel circuit is refreshed, and the fourth-level signal is used to indicate that the pixel circuit is not refreshed; the output terminal out11 of the reading circuit 71 is coupled to the first input terminal in21 of the output circuit 72; the output terminal out21 of the output circuit 72 is coupled to the output terminal out of the gating circuit, and is used to output the second control signal ctrl2.

[0101] The reading circuit 71 is used to: transmit the first refresh control signal SW1 to the first input terminal in21 of the output circuit 72 when the first control signal ctrl1 is a first level signal;

[0102] The output circuit 72 is used to: output the first control signal ctrl1 as the second control signal ctrl2 when the first refresh control signal SW1 is the third level signal, and output the first level signal as the second control signal ctrl2 when the first refresh control signal SW1 is the fourth level signal.

[0103] In some embodiments, such as Figure 8 As shown, the gating circuit may further include a voltage regulator circuit 73. In this case, the output terminal out21 of the output circuit 72 is coupled to the first input terminal in31 of the voltage regulator circuit 73, and the output terminal out31 of the voltage regulator circuit 73 is coupled to the output terminal out of the gating circuit. The voltage regulator circuit 73 is used to regulate the voltage of the second control signal ctrl2 output by the output circuit 71. At this time, the output of the voltage regulator circuit 73 is the regulated second control signal, which is referred to as the third control signal ctrl3 in this embodiment.

[0104] Understandably, in the case of the gating circuit as Figure 6 When the gating circuit 1 of the i-th row pixel circuit corresponds to the generation circuit 1 of the i-th row pixel circuit, the received first control signal ctrl1 is the Ngate-1(i) signal output by the generation circuit 1 of the i-th row pixel circuit. The second control signal ctrl2 or the third control signal ctrl3 output by the gating circuit is output to the gate of the transistor T1 of the i-th row pixel circuit, serving as the gate control signal Ngate(i) of the transistor T1. Figure 6 When the gating circuit 2 of the i-th row pixel circuit corresponds to the generation circuit 2 of the i-th row pixel circuit, the received first control signal ctrl1 is the ResetN-1(i) signal output by the generation circuit 2. The second control signal ctrl2 or the third control signal ctrl3 output by the gating circuit is output to the gate of the transistor T2 of the i-th row pixel circuit as the gate control signal ResetN(i) of the transistor T2. When the first control signal ctrl1 is the Ngate-1(i) signal output by the generation circuit 1 of the i-th row pixel circuit or the ResetN-1(i) signal output by the generation circuit 2, the first control signal will also be referred to as ctrl1(i) in the following embodiments of this application.

[0105] In some embodiments, the first level signal can be a low level signal, and the second level signal can be a high level signal. It is understood that the pixel circuit described above uses an IGZO TFT where transistors T1 and T2 are high-level conducting as an example. In other embodiments, if transistors T1 and T2 are implemented using a low-level conducting TFT, such as an LTPS TFT, then the first level signal can be a high level signal, and the second level signal can be a low level signal. In the following embodiments, an example is provided where the first level signal is low and the second level signal is high.

[0106] In some embodiments, the third level signal can be a low level signal and the fourth level signal can be a high level signal. The specific voltage values ​​of the high and low level signals are not limited in this application embodiment. It is understood that the third level signal can also be a high level signal and the fourth level signal can be a low level signal, as long as the level signals can distinguish whether the corresponding pixel circuit needs to be refreshed. In the following embodiments, an example is given where the third level signal is low and the fourth level signal is high.

[0107] like Figure 9 As shown, in some embodiments, the output circuit 72 may include a switching sub-circuit 721 and an output sub-circuit 722, wherein,

[0108] The first input terminal of the switch sub-circuit 721 is coupled to the first input terminal in21 of the output circuit 72;

[0109] The output terminal of the switch sub-circuit 721 is coupled to the first input terminal of the output sub-circuit 722;

[0110] The output terminal of the output sub-circuit 722 is coupled to the output terminal out21 of the output circuit 72.

[0111] The switching sub-circuit 721 is used to: control the output sub-circuit 722 to work when the first refresh control signal is a third level signal, and control the output sub-circuit 722 to not work when the first refresh control signal is a fourth level signal.

[0112] The output sub-circuit 722 is used to: output a first level signal as a second control signal when not in operation, and output the first control signal ctrl1 as the second control signal ctrl2 when in operation.

[0113] like Figure 9 As shown, in some embodiments, the read circuit 71 may further include a third input terminal in13 for receiving a start control signal GOAX, which is used to control whether the read circuit reads the first refresh control signal SW1.

[0114] It is understood that the transistor control in the pixel circuit has a certain timing sequence to enable the pixel circuit to operate in the initialization phase, charging phase, data refresh phase, and data holding phase, etc. In related technologies, the data refresh phase of the pixel circuit can also be called the data write frame, and the data holding phase can also be called the data hold frame or the pause frame, etc. Therefore, the gating circuit in the embodiments of this application can also control the read circuit to read the first refresh control signal SW1 at an appropriate time based on different controlled transistors.

[0115] Taking the second control signal ctrl2 or the third control signal ctrl3 output by the gating circuit to control transistor T1 of the i-th row pixel circuit as an example, the start control signal GOAX of the gating circuit can be determined according to the data write signal Pgate of transistor T5 in the i-th row pixel circuit. For example, the pulse signal of the data write signal Pgate can be preset with a first duration, such as a first number of rows k1, to obtain the start control signal GOAX. The pulse signal of the start control signal GOAX (shown in the red dashed box in the figure) can be located before the original gate drive signal Ngate-1 of the i-th row pixel circuit changes from a low level signal (first level signal) to a high level signal (second level signal), for example... Figure 10A As shown.

[0116] Taking the second control signal ctrl2 or the third control signal ctrl3 output by the gating circuit to control transistor T2 of the i-th row pixel circuit as an example, the start control signal GOAX of the gating circuit can be determined according to the data write signal Pgate of transistor T5 in the i-th row pixel circuit. For example, the pulse signal of the data write signal Pgate can be preset with a second duration, such as a second number of rows k2, to obtain the start control signal GOAX. The pulse signal of the start control signal GOAX (shown in the red dashed box in the figure) can be located before the original gate reset signal ResetN-1 of the i-th row changes from a low level signal (first level signal) to a high level signal (second level signal), for example... Figure 10B As shown; alternatively, the start control signal GOAX of the gating circuit can be determined based on the positive voltage reset signals ResetH of transistors T7 and T8 in the i-th row pixel circuit. For example, the positive voltage reset signal ResetH of the i-th row (shown in the red dashed box in the figure) can be used as the GOAX signal. Figure 10B As shown.

[0117] Figure 11 This is another schematic diagram of the selection circuit in the embodiment of this application.

[0118] See Figure 11The read circuit 71 may include: transistor T100, transistor T101, and capacitor C1. The first terminal of transistor T100 is coupled to the second input terminal in12 of the read circuit 71, the second terminal is coupled to the first terminal of transistor T101, and the gate is coupled to the third input terminal in13 of the read circuit 71. The second terminal of transistor T101 is coupled to the output terminal out11 of the read circuit 71, and the gate is coupled to the first input terminal 11 of the read circuit 71. The first terminal of capacitor C1 is coupled to the second terminal of transistor T101, and the second terminal of capacitor C1 is coupled to the high voltage supply terminal VGH. Figure 11 The example uses transistors 100 and 101 as low-voltage gated LTPS TFTs.

[0119] See Figure 11 The switching sub-circuit 721 may include a transistor T102, wherein the first end of the transistor T102 is coupled to the gate of the transistor T10 in the signal output sub-circuit of the generation circuit, the second end is coupled to the output terminal of the switching sub-circuit 721, and the gate is coupled to the first input terminal in21 of the switching sub-circuit 721.

[0120] In some embodiments, in order for the output sub-circuit 722 to output a first control signal ctrl1 when it is working and to output a first level signal (e.g., a low voltage signal) when it is not working, the output sub-circuit 722 can be configured according to the circuit of the signal output section in the generation circuit in this embodiment. For example, see Figure 11 The generation circuit may include a signal output sub-circuit, which includes transistors T10 to T12. The first terminal of transistor T10 is coupled to a high-voltage supply terminal VGH, and its second terminal is coupled to the first terminal of transistor T11. The second terminal of transistor T11 is coupled to a low-voltage supply terminal VGL. The gate of transistor T10 is coupled to the first terminal of transistor T12, and the second terminal of transistor T12 is coupled to the high-voltage supply terminal VGH. The second terminal of transistor T10 is also coupled to the output terminal of the generation circuit. Furthermore, the gates of transistors T10, T11, and T12 are respectively coupled to other circuit structures of the generation circuit to achieve the output of a first control signal ctrl1 through the signal output sub-circuit.

[0121] Based on the signal output sub-circuit in the generation circuit, the output sub-circuit 722 provided in this application embodiment may include: transistor T103, transistor T104, and transistor T105, wherein...

[0122] The first terminal of transistor T103 is coupled to the high voltage supply terminal VGH, and the second terminal is coupled to the output terminal of output sub-circuit 722 and the first terminal of transistor T104. The second terminal of transistor T104 is coupled to the low voltage supply terminal VGL. The gate of transistor T103 is coupled to the first terminal of transistor T104 and the output terminal of switch sub-circuit 721.

[0123] The gate of transistor T10 is connected to the gate of transistor T104 in the signal output sub-circuit of the generation circuit, and the gate of transistor T11 is connected to the gate of transistor T105 in the signal output sub-circuit of the generation circuit.

[0124] It should be noted that the signal output sub-circuit in the generation circuit may also include other devices and circuit structures. The embodiments of this application only show the relevant circuit structure in which the first control signal ctrl1 is output through the output terminal out.

[0125] It should be noted that the signal output sub-circuit in the generation circuit can be implemented by other circuit structures. Therefore, the output sub-circuit 722 in this embodiment can also be adapted to change, as long as it can ensure that the output sub-circuit 722 can output the first control signal ctrl1 when working and output the first level signal (e.g., low voltage signal) when not working.

[0126] based on Figure 11 It can be seen that the switching sub-circuit is set between the gate of transistor T10 in the signal output sub-circuit of the generation circuit and the gate of transistor T103 in the output sub-circuit 722, and controls the on / off of the line between the gate of transistor T10 and the gate of transistor T103 based on the signal received at the first input terminal in21.

[0127] See Figure 11 The voltage regulator circuit 73 may further include: a second input terminal for receiving a second refresh control signal SW2; a third input terminal for receiving a first control signal ctrl1; and a fourth input terminal for receiving a start control signal GOAX. The second refresh control signal SW2 can be a third-level signal or a fourth-level signal, and the second refresh control signal SW2 is inverted from the first refresh control signal SW1. That is, when the first refresh control signal SW1 is a third-level signal, the second refresh control signal SW2 is a fourth-level signal, and vice versa. Accordingly, the voltage regulator circuit 73 can specifically be used to regulate the voltage of the second control signal ctrl2 based on the received second refresh control signal SW2, first control signal ctrl1, and start control signal GOAX.

[0128] See Figure 11As shown, the voltage regulator circuit 73 may specifically include: transistors T106 to T108 and capacitor C2, wherein,

[0129] The first terminal of transistor T106 is coupled to the first input terminal in31 and the output terminal out31 of voltage regulator circuit 73, respectively. The second terminal of transistor T106 is coupled to the low voltage supply terminal VGL and the first terminal of capacitor C2, respectively. The gate of transistor T106 is coupled to the second terminal of capacitor C2 and the first terminal of transistor T107, respectively.

[0130] The second terminal of transistor T107 is coupled to the first terminal of transistor T108, and the second terminal of transistor T108 is coupled to the second input terminal of the voltage regulator circuit.

[0131] The gate of transistor T107 is coupled to the third input terminal of voltage regulator circuit 73, and the fourth input terminal of transistor T108 is coupled to the fourth input terminal of voltage regulator circuit 73.

[0132] The following is about Figure 11 The implementation principle of the gating circuit shown is briefly explained below:

[0133] When Ctrl1 is a low-level signal (first level signal), if there is no selection circuit, Ctrl1 can control the corresponding transistor T1 or T2 to turn off, and the pixel circuit will not refresh. When Ctrl1 is a high-level signal (second level signal), if there is no selection circuit, Ctrl1 can control the corresponding transistor T1 or T2 to turn on, and the pixel circuit will refresh.

[0134] After adding the gating circuit, for the pixel circuit of the area that needs to be refreshed (such as the high-frequency area mentioned above), the first refresh control signal SW1 is a low-level signal (third-level signal), and SW2 is a high-level signal (fourth-level signal). When both the start control signal GOAX and the first control signal ctrl1 are low-level signals (first-level signals), transistors T100 and T101 are turned on. The low-level signal of the first refresh control signal SW1 is written into capacitor C1, thereby controlling transistor T102 to turn on. The circuit between the gates of transistors T10 and T103... When the transistor is turned on, the voltage received at the gate of transistor T103 is the same as the voltage received at the gate of transistor T10. The second control signal ctrl2 output by the output sub-circuit 722 is the same as the first control signal ctrl1. After the first control signal ctrl1 becomes a high-level signal, since the second control signal ctrl2 output by the output sub-circuit 722 is the same as the first control signal ctrl1, the second control signal ctrl2 also becomes a high-level signal accordingly. In other words, the output sub-circuit 711 can output the normal first control signal ctrl1. Furthermore, the third control signal ctrl3 obtained after processing by the voltage regulator circuit is also a high-level signal. The third control signal ctrl3 can control the corresponding transistor T1 or transistor T2 in the pixel circuit to turn on, realizing the data writing or reset operation of the pixel circuit, that is, realizing the normal refresh of the pixel circuit in the area that needs to be refreshed.

[0135] After adding the gating circuit, for pixel circuits in areas that do not require refreshing (such as the aforementioned low-frequency area), the first refresh control signal SW1 is a high-level signal (fourth-level signal), and SW2 is a low-level signal (third-level signal). When both the start control signal GOAX and the first control signal ctrl1 are low-level signals (first-level signal), transistors T100 and T101 are turned on. The high-level signal of the first refresh control signal SW1 is written into capacitor C1, thereby controlling transistor T102 to turn off, and the line between the gates of transistors T10 and T103 is disconnected. After the first control signal ctrl1 becomes a high-level signal, transistor T103 remains off, so the second control signal ctrl2 output by the output sub-circuit 722 is a low-level signal. Consequently, the third control signal ctrl3 obtained after passing through the voltage regulator circuit is also a low-level signal. The third control signal ctrl3 cannot control the corresponding transistor T1 or transistor T2 in the pixel circuit to turn on, and the pixel circuit does not perform data writing and reset operations, that is, the pixel circuit in the area that does not require refreshing is not refreshed.

[0136] Furthermore, for the voltage regulator circuit 73, for the pixel circuit of the area that needs to be refreshed (such as the high-frequency area mentioned above), when both the start control signal GOAX and the first control signal ctrl1 are low-level signals (first-level signals), transistors T107 and T108 are turned on, the high-level signal of SW2 is written to capacitor C2, and transistor T106 is turned off. After the first control signal ctrl1 becomes a high-level signal, transistor T106 can remain off.

[0137] For pixel circuits in areas that do not require refreshing (such as the low-frequency area mentioned above), when both the start control signal GOAX and the first control signal ctrl1 are low-level signals (first-level signals), transistors T107 and T108 are turned on. The low-level signal of SW2 is written into capacitor C2, and transistor T106 is turned on. After the first control signal ctrl1 becomes a high-level signal, transistor T107 is turned off, but transistor T106 can remain on to maintain the second control signal ctrl2 in a low-voltage state, that is, to stabilize the voltage of the second control signal ctrl2 and prevent the second control signal ctrl2 from floating, which would cause the pixel circuit to start refreshing abnormally.

[0138] Furthermore, since capacitor C1 is located between the high voltage supply terminal VGH and the gate of transistor 103, a judgment output can be made when the start control signal SW1 changes, thus preventing the currently displayed high line pulse from being abnormally cut off.

[0139] like Figure 12 As shown, in some embodiments, the above Figure 11 The transistor T100 in the diagram can also be implemented using an IGZO TFT. In this case, the signal GOAX input to the gate of the transistor T100 can be implemented using ctrl1 in the previous row. Taking ctrl1 as ctrl1(i) in the i-th row as an example, GOAX can specifically be ctrl1(i-1) in the i-th row.

[0140] like Figure 12 As shown, in some embodiments, the above Figure 11 The transistor T107 in the diagram can also be implemented using an IGZO TFT. In this case, the signal ctrl1 input to the gate of transistor T107 can be implemented using the ctrl1 in the previous row. Taking ctrl1 as ctrl1(i) in the i-th row as an example, GOAX can specifically be ctrl1(i-1) in the i-th row.

[0141] like Figure 13 As shown, in some embodiments, the voltage regulator circuit 73 can also be replaced by the following circuit structure:

[0142] The gate of transistor T109 is coupled to the first terminal of capacitor C1 in read circuit 71, which is also the second terminal of transistor T101, or the output terminal of read circuit 71.

[0143] The first terminal of transistor T109 is coupled to the low voltage supply terminal VGL, and the second terminal is coupled to the first input terminal and the output terminal of voltage regulator circuit 73, respectively.

[0144] like Figure 13 As shown, transistor T109 can be a high-voltage IGZO TFT.

[0145] like Figure 14 As shown, in some embodiments, the second terminal of capacitor C1 in the read circuit 71 can also be coupled to the low voltage supply terminal VGL.

[0146] like Figure 14 As shown, in some embodiments, the output sub-circuit 722 may further include a capacitor C3, with its first terminal coupled to the gate of transistor T103 and its second terminal coupled to the high-voltage supply terminal VGH. The capacitor C3 is used to perform filtering.

[0147] Figure 15 This is a schematic diagram of a generation circuit provided in an embodiment of this application, which includes the aforementioned signal output sub-circuit. It is understood that... Figure 15 The generation circuit shown is merely an example. The structure of the generation circuit can be adapted in other embodiments, and the embodiments of this application are not limited thereto.

[0148] In the above technical solutions, when implementing refresh in different regions, in relatively high-frequency regions (such as the high-frequency region mentioned above), transistors T1 and T2 implemented by IGZO TFT switch frequently. Taking the refresh rate of 120Hz in the high-frequency region as an example, transistors T1 and T2 of each pixel circuit in the high-frequency region switch once every 1 / 120s of a frame. The TFT device is subjected to positive bias temperature stress (PBTS) and positive bias temperature stress (NBTS), so the gate threshold voltage Vth is more positively biased. In relatively low-frequency regions (such as the low-frequency region mentioned above), transistors T1 and T2 implemented by IGZO TFT switch less frequently. Taking the refresh rate of 1Hz in the low-frequency region as an example, transistors T1 and T2 of each pixel circuit in the low-frequency region switch once every 1s (1Hz), and are subjected to less PBTS. Therefore, the positive bias of the gate threshold voltage Vth is not obvious. This difference in gate threshold voltage Vth will cause a difference in the gate position of the DTFT, i.e., transistor T4, when transistors T1 and T2 are switched off due to kickback factors, thus triggering the screen splitting problem after partition refresh (RA). Figure 2A The simulation diagram of the pixel circuit shown is as follows: Figure 16As shown, in the relatively high frequency region, transistor T1 undergoes a turn-on and turn-off process, experiencing PBTS when turned on and NBTS when turned off.

[0149] Therefore, embodiments of this application, for example... Figure 2A The pixel circuit structure has been improved by adding transistor T9. The improved pixel circuit implementation structure is as follows: Figure 17 As shown. The pixel circuit includes:

[0150] The first terminal of capacitor C0 and the first terminal of transistor T6 are respectively coupled to the first power supply terminal VDD. The first terminal of transistor T4, the second terminal of transistor T5, the second terminal of transistor T6, and the first terminal of transistor T7 are coupled to point A1. The second terminal of capacitor C, the gate of transistor T4, and the first terminal of transistor T9 are coupled to point A2. The second terminal of transistor T1, the first terminal of transistor T2, and the second terminal of transistor T9 are coupled to point A4. The first terminal of transistor T1, the second terminal of transistor T4, and the first terminal of transistor T3 are coupled to point A3. The second terminal of transistor T3, the anode of light-emitting diode D, and the first terminal of transistor T8 are coupled to point A4. The second terminal of transistor T2 is coupled to the first reference voltage Vref1. The second terminal of transistor T8 is coupled to the second reference voltage Vref2. The second terminal of transistor T7 is coupled to the third reference voltage Vref3. The cathode of light-emitting diode D is coupled to the second power supply terminal VSS. The gates of transistors T3 and T6 are used to receive control signals EM, the gate of transistor T1 is used to receive gate control signal Ngate, the gates of transistors T7 and T8 are used to receive control signals Reset H, the gate of transistor T2 is used to receive gate reset signal ResetN, and the gate of transistor T5 is used to receive control signal Pgate1; the second terminal of transistor T5 is used to receive the drive signal Data of the pixel circuit; and the gate of transistor T9 is used to receive control signal Pgate2.

[0151] like Figure 17 As shown, transistor T9 can be implemented using an LTPS TFT.

[0152] Among them, transistor T7 is an optional device, and transistor T8 is also an optional device; in other words... Figure 17 The pixel circuit shown may also exclude transistor T7 and / or transistor T8.

[0153] The working principle of the pixel circuit in the refresh and hold phases is combined Figure 16 and Figure 17 The signal timing diagram is illustrated as an example.

[0154] Figure 18This is a timing diagram of the pixel circuit during the refresh phase, which can also be called the data writing frame.

[0155] exist Figure 18 The process of writing data into a frame is further divided into stages 1 through 7. These are explained below:

[0156] Throughout the refresh phase, transistors T3 and T6 remain off, and will not be described further in the following phases.

[0157] In stage 1: transistors T1, T2, T5, T7, and T8 are turned off, and transistor T9 is turned on;

[0158] In stage 2: transistors T2 and T5 remain off, transistor T9 remains on, and transistors T1, T7, and T8 switch to on, achieving high-voltage reset of the pixel circuit, improving the display effect. In addition, transistor T8 can achieve anode reset of the pixel circuit. At the end of stage 2, transistors T7 and T8 switch to off.

[0159] In stage 3: transistors T1 and T9 remain on, transistor T5 remains off, transistors T7 and T8 are off, and transistor T2 switches to on, thereby resetting the gate of transistor T4 (i.e., DTFT) and eliminating the influence of the previous frame image display.

[0160] In stage 4: transistors T1 and T9 remain on, transistors T5, T7 and T8 remain off, transistor T2 switches off, transistor T5 briefly turns on, data is written to node A2, and Vth compensation of transistor T4 is completed at the same time.

[0161] In stage 5: transistors T2, T5, T7, and T8 remain off, transistor T1 is turned on first and then switched off, and transistor T9 switches off.

[0162] In stage 6: transistors T1, T2, and T5 remain off; transistors T7 and T8 are first turned off and then switched on; transistor T9 switches on. This stage enables a second high-voltage reset and anode reset of the pixel circuit, thereby improving the dynamic display function of the screen.

[0163] The switching on and off of the transistors in stage 7 is the same as in stage 1, so it will not be repeated here.

[0164] Figure 19 This is a timing diagram of the pixel circuit during the hold phase, which can also be called the hold frame.

[0165] existFigure 19 The process of writing data into a frame is further divided into stages 1 through 7. These are explained below:

[0166] Throughout the hold phase, transistors T1, T2, T3, and T6 remain off, and will not be described further in the following phases.

[0167] In stage 1: transistors T5, T7, and T8 are turned off, and transistor T9 is turned on;

[0168] In stage 2: transistor T5 remains off, transistor T9 remains on, and transistors T7 and T8 switch to on, realizing high-voltage reset of the pixel circuit, improving the display effect. In addition, transistor T8 can realize anode reset of the pixel circuit.

[0169] In stage 3: transistor T9 remains on, transistor T5 remains off, and transistors T7 and T8 switch off, thereby resetting the gate of transistor T4 (i.e., DTFT) and eliminating the influence of the previous frame image display.

[0170] In phase 4: transistor T9 remains on, transistors T5, T7 and T8 remain off, transistor T5 briefly turns on, but because transistor T1 is off, data cannot be written to node A2.

[0171] In phase 5: transistors T5, T7, and T8 remain off, while transistor T9 switches off.

[0172] In stage 6: transistor T5 remains off, transistors 7 and T8 are first turned off and then switched on; transistor T9 switches on. This stage enables a second high-voltage reset and anode reset of the pixel circuit, thereby improving the dynamic display function of the screen.

[0173] The switching on and off of the transistors in stage 7 is the same as in stage 1, so it will not be repeated here.

[0174] The pixel circuit provided in this application embodiment, by adding transistor T9 and driving it with gate drive signal Pgate2, has the following advantages:

[0175] 1. Transistor T9 is turned off before transistor T1 is turned off, ensuring that the kickback effect caused by the falling edge change of the gate drive signal Ngate of transistor T1 will not affect node A2;

[0176] 2. Transistor T9 maintains perfect consistency in the transitions between the hold frame and the data write frame. Simultaneously, transistor T9 is turned on during the light emission process, ensuring that the disturbance of node A2 in the hold frame and the data write frame is consistent, and that the stress state of transistor T9 is consistent, thereby reducing the impact of transistor T9 transitions on node A2.

[0177] Simulation diagrams of pixel circuits in embodiments of this application are as follows: Figure 20 As shown, when the gate threshold voltage Vth difference between transistor T1 and transistor T2 is 1V, the voltage difference of node A2 is reduced from the original 80mV to <10mV, thereby reducing or eliminating the screen splitting problem after partition refresh (RA).

[0178] It should be noted that the embodiments provided in this application... Figure 17 The pixel circuit shown can be used in conjunction with the aforementioned generation circuit and gating circuit to achieve regional refresh rate settings for the display screen. However, the pixel circuit provided in this application embodiment is not limited to use in conjunction with the aforementioned generation circuit and gating circuit. In other words, the pixel circuit provided in this application embodiment can also be applied to other display screens that do not perform regional refresh, serving as the pixel circuit in that display screen.

[0179] This application provides a driving circuit, including the gating circuit provided in this application embodiment.

[0180] This application provides a display integrated circuit, including the gating circuit provided in this application embodiment.

[0181] This application provides a display panel, including the gating circuit provided in this application embodiment.

[0182] This application provides a display screen, including the gating circuit provided in this application embodiment.

[0183] This application provides a display panel, including the pixel circuit provided in this application embodiment.

[0184] This application provides a display screen, including the pixel circuit provided in this application embodiment.

[0185] This application also provides an electronic device, including the gating circuit provided in this application embodiment.

[0186] This application also provides an electronic device, including the pixel circuit provided in this application embodiment.

[0187] This application also provides an electronic device, including the gating circuit and pixel circuit provided in this application embodiment.

[0188] This application also provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to execute the method provided in this application.

[0189] This application also provides a computer program product, which includes a computer program that, when run on a computer, causes the computer to perform the method provided in this application.

[0190] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, A and B simultaneously, or B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0191] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0192] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0193] In the several embodiments provided in this application, any function, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0194] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A gating circuit, comprising: The application is applied to a gate drive circuit including a generation circuit, an output end of the generation circuit is used for outputting a first control signal; the first control signal is a first level signal or a second level signal, the first level signal can control a target transistor in a pixel circuit corresponding to the generation circuit to be turned off, and the second level signal can control the target transistor in the pixel circuit to be turned on; The gate-on circuit includes a reading circuit and an output circuit, wherein, a first input end of the reading circuit is coupled with an output end of the generation circuit to receive the first control signal; a second input end of the reading circuit is used for receiving a first refresh control signal; the first refresh control signal is a third level signal or a fourth level signal; the third level signal is used for indicating that the pixel circuit is refreshed; the fourth level signal is used for indicating that the pixel circuit is not refreshed; an output end of the reading circuit is coupled with a first input end of the output circuit; and an output end of the output circuit is coupled with an output end of the gate-on circuit to output a second control signal. The reading circuit is used for transmitting the first refresh control signal to the first input end of the output circuit when the first control signal is the first level signal. The output circuit is used for outputting the first control signal as the second control signal when the first refresh control signal is the third level signal, and outputting the first level signal as the second control signal when the first refresh control signal is the fourth level signal.

2. The gating circuit of claim 1, wherein, The output circuit specifically includes a switch sub-circuit and an output sub-circuit, wherein, a first input end of the switch sub-circuit is used for coupling the first input end of the output circuit to receive the first refresh control signal; and an output end of the output sub-circuit is coupled with the output end of the output circuit. The switch sub-circuit is used for controlling the signal output sub-circuit to work when the first refresh control signal is the third level signal, and controlling the output sub-circuit to stop working when the first refresh control signal is the fourth level signal. The output sub-circuit is used for outputting the first control signal as the second control signal when working, and outputting the first level signal as the second control signal when stopping working.

3. A gating circuit according to claim 2, characterised in that The generation circuit includes a first transistor, a second transistor and a third transistor; a first end of the first transistor and a first end of the third transistor are coupled with a high-voltage providing end; a second end of the first transistor and a first end of the second transistor are coupled with an output end of the generation circuit; a second end of the second transistor is coupled with a low-voltage providing end; and a second end of the third transistor is coupled with a gate of the first transistor. The gate-on circuit further includes a second input end of the switch sub-circuit coupled with the gate of the first transistor, and an output end of the switch sub-circuit coupled with a first input end of the signal output sub-circuit. The output sub-circuit comprises a fourth transistor, a fifth transistor and a sixth transistor; a first end of the fourth transistor and a first end of the sixth transistor are coupled to the high-voltage supply end; a second end of the fourth transistor and a first end of the fifth transistor are coupled to an output end of the output sub-circuit; a second end of the fifth transistor is coupled to the low-voltage supply end; a second end of the sixth transistor and a gate of the fourth transistor are coupled to a first input end of the output sub-circuit; a gate of the fifth transistor is used for coupling to a gate of the second transistor; and a gate of the sixth transistor is used for coupling to a gate of the third transistor.

4. A gating circuit according to claim 3, characterised in that The switch sub-circuit comprises a seventh transistor; wherein A gate of the seventh transistor is coupled to a first input end of the switch sub-circuit; a first end of the seventh transistor is coupled to a second input end of the switch sub-circuit; and a second end of the seventh transistor is coupled to an output end of the switch sub-circuit.

5. A gating circuit according to any one of claims 1 to 4, characterized in that The read circuit comprises an eighth transistor, wherein A gate of the eighth transistor is coupled to a first input end of the read circuit; a first end of the eighth transistor is coupled to a second input end of the read circuit; and a second end of the eighth transistor is coupled to an output end of the read circuit.

6. A gating circuit according to claim 5, wherein, The read circuit further comprises a ninth transistor; The first end of the eighth transistor is coupled to the second input end of the read circuit, comprising: The first end of the eighth transistor is coupled to a first end of the ninth transistor; a second end of the ninth transistor is coupled to the second input end of the read circuit; A gate of the ninth transistor is used for receiving a first signal; the first signal is used for controlling the ninth transistor to be turned on before the first control signal is converted from the first voltage signal to the second voltage signal.

7. The gating circuit of claim 5, wherein, The read circuit further comprises a tenth transistor and a first capacitor; The first end of the eighth transistor is coupled to the second input end of the read circuit, comprising: The first end of the eighth transistor is coupled to a first end of the tenth transistor; a second end of the tenth transistor is coupled to the second input end of the read circuit; A first end of the first capacitor is coupled to a second end of the eighth transistor; and a second end of the first capacitor is coupled to the high-voltage supply end; A gate of the tenth transistor is used for receiving a second signal; the second signal is used for controlling the tenth transistor to be turned on for at least a preset first time length before the first control signal is converted from the first voltage signal to the second voltage signal.

8. The gating circuit according to any one of claims 1 to 7, characterized in that The gating circuit further comprises a voltage stabilizing circuit; a first input end of the voltage stabilizing circuit is coupled to an output end of the output circuit. The voltage stabilizing circuit is used for performing voltage stabilizing processing on a second control signal output by the output circuit to obtain a third control signal.

9. The gating circuit of claim 8, wherein, The voltage stabilizing circuit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor and a second capacitor, wherein A first end of the eleventh transistor is coupled to a first input end and an output end of the voltage stabilizing circuit, a second end is coupled to a low voltage providing end, a gate is coupled to a first end of the twelfth transistor, a second end of the twelfth transistor is coupled to a first end of the thirteenth transistor, a second end of the thirteenth transistor is used for receiving a second refresh control signal, the second refresh control signal and the first refresh control signal are opposite in phase; A first end of the second capacitor is coupled to a gate of the eleventh transistor, a second end is coupled to the low voltage providing end; A gate of the twelfth transistor is used for receiving the first control signal, a gate of the thirteenth transistor is used for receiving a third signal, the third signal is used for controlling the thirteenth transistor to be turned on for at least a preset first time length before the first control signal is converted from the first level signal to the second level signal.

10. The gating circuit of claim 8, wherein, The voltage stabilizing circuit comprises: A fourteenth transistor, a gate of the fourteenth transistor is coupled to an output end of the reading circuit, a first end of the fourteenth transistor is coupled to a low voltage providing end, a second end is coupled to a first input end and an output end of the output circuit.

11. A gating circuit according to any one of claims 1 to 10, characterized in that Further comprising: A pixel circuit, the pixel circuit comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a third capacitor, wherein A first end of the third capacitor and a first end of the twentieth transistor are respectively coupled to a first power supply end, a first end of the eighteenth transistor, a second end of the nineteenth transistor and a second end of the twentieth transistor are coupled, a second end of the third capacitor, a gate of the eighteenth transistor and a first end of the twenty-first transistor are coupled, a second end of the fifteenth transistor, a first end of the sixteenth transistor and a second end of the twenty-first transistor are coupled, a first end of the fifteenth transistor, a first end of the seventeenth transistor and a second end of the eighteenth transistor are coupled, a second end of the seventeenth transistor is used for coupling an anode of a light emitting diode, and a second end of the sixteenth transistor is coupled to a first reference voltage.

12. The gating circuit of claim 11, wherein, Further comprising: A twenty-second transistor, a first end of the twenty-second transistor is coupled to the first end of the eighteenth transistor, and a second end is coupled to a third reference voltage.

13. The gating circuit of claim 11, wherein, Further comprising: A twenty-third transistor, a first end of the twenty-third transistor is coupled to the second end of the seventeenth transistor, and a second end is coupled to a second reference voltage.

14. A pixel circuit, characterized in that, The pixel circuit comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a third capacitor, wherein A first end of the third capacitor, a first end of the twentieth transistor are coupled to a first power supply end, a first end of the eighteenth transistor, a second end of the nineteenth transistor, and a second end of the twentieth transistor are coupled, a second end of the third capacitor, a gate of the eighteenth transistor, and a first end of the twenty-first transistor are coupled, a second end of the fifteenth transistor, a first end of the sixteenth transistor, and a second end of the twenty-first transistor are coupled, a first end of the fifteenth transistor, a first end of the seventeenth transistor, and a second end of the eighteenth transistor are coupled, a second end of the seventeenth transistor is configured to couple to an anode of the light emitting diode; a second end of the sixteenth transistor is coupled to a first reference voltage.

15. The pixel circuit of claim 14, wherein, Further comprising: a twenty-second transistor, a first end of the twenty-second transistor is coupled to the first end of the eighteenth transistor, and a second end of the twenty-second transistor is coupled to a third reference voltage.

16. The pixel circuit according to claim 14 or 15, characterized in that, Further comprising: a twenty-third transistor, a first end of the twenty-third transistor is coupled to the second end of the seventeenth transistor, and a second end of the twenty-third transistor is coupled to a second reference voltage.

17. A drive circuit, characterized by The pixel circuit according to any one of claims 1 to 13.

18. A display integrated circuit, comprising: The pixel circuit according to any one of claims 1 to 13.

19. A display panel, characterized by The pixel circuit according to any one of claims 1 to 13.

20. A display panel comprising: The pixel circuit according to any one of claims 14 to 16.

21. An electronic device, comprising: The pixel circuit according to any one of claims 1 to 13.

22. An electronic device, comprising: The pixel circuit according to any one of claims 14 to 16.

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