Three-dimensional asymmetric photonic crystal laser and preparation method thereof

Abstract

The application discloses a three-dimensional asymmetric photonic crystal laser and a preparation method. x1 In 1‑x1 As the upper confining layer, the quantum well active region, the P-type Al y1 In 1‑y 1As the electron blocking layer, the P-type Ga z1 In 1‑z 1As z2 P 1‑z2 functional layer, the P-type Al x2 In 1‑x2 As the lower confining layer, the P-type InP connecting layer, the bottom insulating layer and the P-type electrode; wherein the P-type GaInAsP functional layer is etched with a three-dimensional asymmetric photonic crystal, the chiral characteristic is introduced by destroying the symmetry of the photonic crystal, and the three-dimensional asymmetric photonic crystal laser emits a single-mode light beam with left-handed or right-handed circular polarization vertically. The application realizes the high-efficiency output of the circularly polarized light beam by designing the asymmetric photonic crystal structure, significantly improves the polarization selectivity and the light beam quality, and has the advantages of low divergence angle and high light beam stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser technology, specifically to a three-dimensional asymmetric photonic crystal laser and its fabrication method. Background Technology

[0002] Photonic-Crystal Surface-Emitting Lasers (PCSELs) utilize the unique structure of photonic crystals to achieve vertically oriented single-mode, large-area coherent beam output, offering superior beam quality and emission efficiency compared to traditional edge-emitting lasers and vertical-cavity surface-emitting lasers. However, existing PCSEL chips generally employ symmetrical photonic crystal structures, which still exhibit significant limitations in polarization control, particularly in the generation of circularly polarized light.

[0003] With the rapid development of applications such as quantum communication, lidar, and biomedical imaging, the demand for circularly polarized laser sources is becoming increasingly urgent. Traditional methods, such as adding external polarization devices, usually lead to system complexity and additional losses. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a three-dimensional asymmetric photonic crystal laser and its fabrication method. It directly achieves efficient and stable circularly polarized light output through an asymmetric three-dimensional photonic crystal structure, meeting the higher performance requirements of modern optoelectronic devices.

[0005] This invention discloses a three-dimensional asymmetric photonic crystal laser. The epitaxial structure of the laser includes, from top to bottom, an N-type electrode, an N-type InP substrate, and an N-type Al electrode. x1 In 1-x1 As upper confinement layer, quantum well active region, p-type Al y In 1- y As electron blocking layer, P-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer, P-type Al x2 In 1-x2 An As-type confinement layer, a P-type InP interconnect layer, and a bottom insulating layer and a P-type electrode at the bottom layer; wherein, the P-type Ga... z1 In 1-z1 As z2 P 1-z2 A three-dimensional asymmetric photonic crystal is etched on the functional layer. By breaking the symmetry of the photonic crystal, chiral properties are introduced, enabling the chip to emit single-mode beams with left-handed or right-handed circular polarization perpendicularly.

[0006] As a further improvement of the present invention, the three-dimensional asymmetric photonic crystal includes one of a single-lattice photonic crystal, a dual-lattice photonic crystal, and a multi-lattice photonic crystal, with the characteristic size of different lattice units being 300nm~500nm.

[0007] As a further improvement of the present invention, the lattice unit of the three-dimensional asymmetric photonic crystal is composed of air holes of different shapes, including one or more of circular, triangular, elliptical, trapezoidal, hexagonal and polygonal shapes. Different lattice units are composed of air holes of different etching depths and shapes. The etching depth of the lattice unit is 300nm~1100nm.

[0008] As a further improvement of the present invention, electrode contact holes for forming P-type electrodes are etched on the bottom insulating layer. The P-type electrodes are sputtered in the electrode contact holes and connected to the P-type InP interconnect layer. The bottom insulating layer is made of dielectric material to reduce current leakage and improve the electrical performance of the chip. The material of the bottom insulating layer includes SiO2, Si3N4 or Al2O3, and the thickness is 100nm~500nm.

[0009] As a further improvement of the present invention, the three-dimensional asymmetric photonic crystal is formed in the following manner: on the basis of a two-dimensional photonic crystal, the XY plane symmetry is broken by adjusting the arrangement of the lattice units or changing the shape and size of the air holes; in the Z direction, the symmetry is further broken by changing the depth, shape or arrangement direction of the air holes, thereby realizing an overall three-dimensional asymmetric structure; wherein, the asymmetric characteristics are used to optimize the photonic bandgap characteristics and improve the polarization selectivity and chiral control capability of the vertically emitted light.

[0010] As a further improvement of the present invention, the polarization control mechanism of the three-dimensional asymmetric photonic crystal is realized based on the phase difference condition; wherein, and are respectively the electric fields inside the lattice face. E y and E x The additional phase introduced by the component, the phase difference being caused by the shape asymmetry of the lattice unit, the difference in etching depth, and the tilt angle of the air hole. θ A joint decision.

[0011] As a further improvement of the present invention, the lattice constant of the three-dimensional asymmetric photonic crystal is 400nm~450nm, the etching depth is 400nm~600nm, the hole wall inclination angle is 5°~32°, and the air hole duty cycle is 35%~65%.

[0012] As a further improvement of the present invention, in the epitaxial structure, the N-type doping source includes one or more of Si2H6, SiH4, Fe(C2H5)2, TMGa, and TEGa, and the P-type doping source includes one or more of BeMe2, DMZn, CBr4, Cp2Mg, and (CH3)2Mg.

[0013] As a further improvement of the present invention The active region of the quantum well is a multi-quantum-well structure, grown using AlGaInAs materials with different compositions, wherein the thickness of the quantum well is 5nm~10nm and the thickness of the quantum barrier is 7nm~12nm. In the N-type Al x1 In 1-x1 In the upper confinement layer of As, x1 is 0.3~0.6; In the P-type Al x2 In 1-x2 In the lower confinement layer of As, x2 is 0.3~0.6; In the P-type Al y In 1-y In the As electron blocking layer, y is 0.3~0.6; In the P-type Ga z1 In 1-z1 As z2 P 1-z2 In the functional layer, z1 is 0.1~0.3 and z2 is 0.2~0.4.

[0014] This invention also discloses a method for fabricating a three-dimensional asymmetric photonic crystal laser, comprising: Select an N-type InP substrate; N-type Al was sequentially grown on the N-type InP substrate using molecular beam epitaxy, liquid phase epitaxy, or organometallic vapor phase epitaxy. x1 In 1-x1 As upper confinement layer, quantum well active region, p-type Al y In 1-y As electron blocking layer and p-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer; Electron beam lithography was used in the study of P-type Ga z1 In 1-z1 As z2 P 1-z2 A three-dimensional asymmetric photonic crystal pattern is defined on the functional layer, and then the three-dimensional asymmetric photonic crystal is etched using inductively coupled plasma etching technology. Continue growing P-type Al on the etched three-dimensional asymmetric photonic crystal surfacex2 In 1-x2 As lower confinement layer and P-type InP connection layer; After depositing a bottom insulating layer on the surface of the P-type InP interconnect layer, electrode contact holes of the P-type electrode are formed by photoresist mask and ultraviolet exposure technology, and then P-type electrodes are deposited at the electrode contact holes by magnetron sputtering technology. The back of the chip is thinned and polished by chemical mechanical polishing. Then, an N-type electrode window pattern is obtained on the surface of the N-type InP substrate using photoresist mask and ultraviolet exposure technology. Finally, N-type electrodes are sputtered on the surface of the N-type InP substrate using magnetron sputtering technology. The chip is then cleaved, wire-bonded, and packaged.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves chiral control within a PCSEL chip by designing a three-dimensional asymmetric photonic crystal structure, enabling the chip to directly output a highly efficient and stable circularly polarized single-mode beam. This significantly improves the purity and beam quality of the circularly polarized light, reduces the beam divergence angle, and solves the problem that traditional PCSELs have difficulty in effectively generating and controlling circularly polarized light. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of the three-dimensional asymmetric photonic crystal laser disclosed in this invention; Figure 2 This is a top view of the dual-lattice three-dimensional asymmetric photonic crystal and its periodic unit disclosed in this invention; Figure 3 This is a schematic diagram of the structure of the dual-lattice three-dimensional asymmetric photonic crystal disclosed in this invention; Figure 4 This is a schematic diagram of the structure of the single-lattice three-dimensional asymmetric photonic crystal disclosed in this invention; Figure 5 This is a schematic diagram of the structure of the three-dimensional asymmetric photonic crystal with a three-lattice structure disclosed in this invention; Figure 6 This is a flowchart of the fabrication method of the three-dimensional asymmetric photonic crystal PCSEL disclosed in this invention.

[0017] In the picture: 1: P-type electrode; 2: P-type InP bonding layer; 3: P-type Al x2 In 1-x2 As lower confinement layer; 4: P-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer; 5: P-type Al y In 1-y As electron blocking layer; 6: quantum well active region; 7: N-type Alx1 In 1-x1 8: Confinement layer on top; 9: N-type InP substrate; 10: N-type electrode; 11: Three-dimensional asymmetric photonic crystal; 22: Bottom insulating layer. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The present invention will now be described in further detail with reference to the accompanying drawings: like Figure 1 As shown, the present invention provides a three-dimensional asymmetric photonic crystal laser, comprising: a bottom-emitting 1310nm three-dimensional asymmetric photonic crystal PCSEL chip; The epitaxial structure of the bottom-emission 1310nm three-dimensional asymmetric photonic crystal PCSEL chip of the present invention includes, from bottom to top, a P-type electrode 1, a bottom insulating layer 11, a P-type InP interconnect layer 2, and a P-type Al layer. x2 In 1-x2 As lower confinement layer 3, P-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer 4, P-type Al y In 1-y 5. As electron blocking layer; 6. Quantum well active region; 7. N-type Al x1 In 1-x1 As confinement layer 7 and N-type InP substrate 8, the N-type InP substrate 8 has a top insulating layer and N-type electrode 9, wherein the P-type Ga z1 In 1- z1 As z2 P 1-z2 Functional layer 4 is etched with a three-dimensional asymmetric photonic crystal 10. By disrupting the symmetry of the photonic crystal structure, the chip emits a single-mode beam with left- or right-hand circular polarization perpendicularly, such as... Figure 1 As shown.

[0020] Specifically: like Figure 2 , 3As shown in Figures 4 and 5, the three-dimensional asymmetric photonic crystal 10 of the present invention includes one or more of single-lattice photonic crystals, dual-lattice photonic crystals, and triple-lattice photonic crystals, with characteristic parameters of different lattice units ranging from 300 nm to 500 nm. The single-lattice photonic crystal, dual-lattice photonic crystal, and triple-lattice photonic crystal are respectively composed of one, two, and three types of air holes of the same or different shapes. Figure 2 , Figure 3 Taking the dual-lattice three-dimensional asymmetric photonic crystal shown as an example, it consists of two circular air holes of different diameters, arranged periodically in the X and Y directions, and the three-dimensional asymmetry of the photonic crystal is achieved through the tilted hole structure.

[0021] The lattice unit of the three-dimensional asymmetric photonic crystal 10 of the present invention is composed of air holes of different shapes, including one or more combinations of circles, triangles, ellipses, trapezoids, hexagons, polygons, etc. The shape of the air holes can also be superimposed or combined by multiple shapes. Different lattice units have different etching depths and tilt angles, with etching depths of 300nm~1100nm and tilt angles of 5°~32°.

[0022] In the epitaxial structure of the present invention, the N-type doping source includes one or more of Si2H6, SiH4, Fe(C2H5)2, TMGa, and TEGa, and the P-type doping source includes one or more of BeMe2, DMZn, CBr4, Cp2Mg, and (CH3)2Mg.

[0023] The active region 6 of the quantum well in this invention is a multi-quantum-well structure, which is grown using AlGaInAs materials with different compositions. The thickness of the quantum well is 5nm~10nm, and the thickness of the quantum barrier is 7nm~12nm.

[0024] This invention is based on N-type Al x1 In 1-x1 In the upper confinement layer 7 of As, x1 is 0.3~0.6; in the P-type Al x2 In 1-x2 In the lower confinement layer 3 of As, x2 is 0.3~0.6; in the P-type Al y In 1-y In As electron blocking layer 5, y is 0.3~0.6; in p-type Ga z1 In 1-z1 As z2 P 1-z2 In functional layer 4, z1 is 0.1~0.3 and z2 is 0.2~0.4. Different components directly affect the refractive index of the material, which in turn affects the output wavelength and circularly polarized light output characteristics of the chip.

[0025] like Figure 1 , 6As shown, this invention provides a method for fabricating a three-dimensional asymmetric photonic crystal PCSEL chip, comprising: Step 1: Select an N-type InP substrate 8; Step 2: Grow the epitaxial structure of the PCSEL chip using molecular beam epitaxy (MBE), liquid phase epitaxy, or metal-organic chemical vapor deposition (MOCVD), specifically: grow N-type Al from bottom to top on the surface of the N-type InP substrate 8. x1 In 1-x1 As upper confinement layer 7, quantum well active region 6, P-type Al y In 1-y As electron blocking layer 5 and p-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer 4; Step 3: Using electron beam lithography (EBL), on P-type Ga... z1 In 1-z1 As z2 P 1-z2 A three-dimensional asymmetric photonic crystal pattern was obtained on functional layer 4, and then the three-dimensional asymmetric photonic crystal pattern was etched using inductively coupled plasma etching (ICP) to obtain three-dimensional asymmetric photonic crystal 10. Step 4: On the surface of the three-dimensional asymmetric photonic crystal 10, continue to grow P-type Al from bottom to top using molecular beam epitaxy, liquid phase epitaxy, or metal-organic vapor phase epitaxy. x2 In 1-x2 As lower confinement layer 3 and P-type InP connection layer 2; Step 5: After depositing the bottom insulating layer 11 on the surface of the P-type InP interconnect layer 2, the P-type electrode contact hole is formed using photoresist mask and ultraviolet exposure technology. Step 6: Sputter P-type electrode 1 at the contact hole using magnetron sputtering technology, and perform chemical mechanical polishing to thin the N-type InP substrate 8 on the back of the chip. Step 7: Sputter N-type electrodes 9 on the back side of the thinned N-type InP substrate 8, and then cleave and package the chip. Example 1:

[0026] A method for fabricating a 1310nm dual-lattice PCSEL chip based on a three-dimensional asymmetric photonic crystal, comprising: S11. Select an N-type InP substrate 8 and immerse it in deionized water for 5-10 minutes to remove surface impurities. Then, place the substrate in a beaker containing acetone and ultrasonically clean it for 2 minutes to remove grease and other organic matter soluble in acetone. Next, place the substrate in a beaker containing ethanol and ultrasonically clean the acetone on the surface. Finally, immerse it in deionized water for 2 minutes to remove residual alcohol and dry the substrate with a nitrogen gun. S12. The epitaxial structure of the PCSEL chip is grown using metal-organic chemical vapor deposition (MOCVD). By controlling process parameters such as reaction temperature, precursor flow rate, carrier gas flow rate, reaction pressure, and deposition time, materials of different thicknesses and doping levels are obtained. N-type Al is sequentially grown from bottom to top on the surface of the N-type InP substrate 8. x1 In 1-x1 As upper confinement layer 7, quantum well active region 6, P-type Al y In 1-y As electron blocking layer 5 and p-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer 4; S13. A SiO2 layer with a thickness of 100nm~200nm was deposited as a mask for the P-type functional layer 4 using plasma-enhanced chemical vapor deposition (PECVD). A ZEP (Zero-Electron Polymer Extraction) layer with a thickness of 260nm~300nm was then spin-coated using a spin coater at a speed of 2500-3000 rpm. Electron beam lithography (EBL) was used to expose and develop the image, resulting in a dual-lattice photonic crystal pattern. The SiO2 mask was then etched using inductively coupled plasma etching (ICP) to obtain the pattern. The ZEP was removed using plasma 300 remover, with an O2 flow rate of 0 ml / min, an N2 flow rate of 300 ml / min, and a power of 300W. ICP etching of the P-type functional layer 4 was then continued to obtain the dual-lattice three-dimensional asymmetric photonic crystal 10. Figure 2 , 3 As shown, the periodic unit cells of this photonic crystal consist of two different sizes of air holes, with lattice constants ranging from 380 nm to 430 nm and hole diameters of da and db respectively. A =320nm, d B =410nm, etching depth of 400nm~600nm, and air hole tilt angle of 5°~32°. The SiO2 mask was then removed using reactive ion etching. S14. On the surface of the dual-lattice three-dimensional asymmetric photonic crystal 10, P-type Al is further grown from bottom to top using MOCVD. x2 In 1-x2 As lower confinement layer 3 and P-type InP connection layer 2; S15. Using photoresist mask and ultraviolet exposure technology, an electrode contact hole pattern is formed on the surface of the P-type InP interconnect layer 2. After depositing SiO2 with a thickness of 2μm~4μm, a bottom insulating layer 11 is formed by wet etching technology. S16. Using magnetron sputtering technology, titanium (50nm~100nm) and gold (450nm~550nm) are sequentially sputtered at the electrode contact holes of the P-type InP interconnect layer 2 to form a P-type electrode 1. Subsequently, acetone is used to remove the surface photoresist and the metal layer in the non-electrode areas is stripped. S17. The back side of the N-type InP substrate 8 is thinned and polished using a chemical mechanical polishing machine to remove surface defects and obtain a smooth mirror finish. S18. Using magnetron sputtering technology, germanium (50nm~100nm) and gold (450nm~550nm) are sequentially sputtered on the back side of the thinned N-type InP substrate 8 to form an N-type electrode 9; S19. Use a dicing machine to cut the epitaxial wafer into individual chips, then use a wire bonding machine to connect the chips to the packaging base, perform packaging, and complete optical and electrical function tests to ensure that the chip has 1310nm high-power circularly polarized single-mode vertical light output capability. Example 2:

[0027] A method for fabricating a 1310nm single-lattice PCSEL composite chip based on a three-dimensional asymmetric photonic crystal, comprising: S21. Select an N-type InP substrate 8, immerse it in deionized water for 5-10 minutes to remove surface impurities, then place the substrate in a beaker containing acetone and ultrasonically clean it for 2 minutes to remove grease and other organic matter soluble in acetone. Next, place the substrate in a beaker containing ethanol and ultrasonically clean the acetone on the surface. Finally, immerse it in deionized water for 2 minutes to remove residual alcohol on the surface, and dry the substrate with a nitrogen gun. S22. PCSEL chip epitaxial structures are grown using metal-organic chemical vapor phase epitaxy (MOCVE). By controlling process parameters such as reaction temperature, precursor flow rate, carrier gas flow rate, reaction pressure, and deposition time, materials of different thicknesses and doping levels are obtained. N-type Al₂O₃ is sequentially grown from bottom to top on the surface of an N-type InP substrate 8. x1 In 1-x1 As upper confinement layer 7, quantum well active region 6, P-type Al y In 1-y As electron blocking layer 5 and p-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer 4; S23. A SiO2 layer with a thickness of 100nm~200nm was deposited as a mask for the P-type functional layer 4 using plasma-enhanced chemical vapor deposition (PECVD). A ZEP (Zero-Electronic Photonic Etching) layer with a thickness of 260nm~300nm was then spin-coated at a speed of 2500rpm~3000rpm. After exposure and development using electron beam lithography (EBRT), a single-lattice photonic crystal pattern was obtained. The SiO2 mask was then etched using inductively coupled plasma etching (ICP-lithography) to form the pattern. The ZEP was removed using plasma 300 (O2 flow rate 0 ml / min, N2 flow rate 300 ml / min, power 300W). The P-type functional layer 4 was then etched to form the single-lattice three-dimensional asymmetric photonic crystal 10. Figure 4 As shown, the periodic unit cell of this photonic crystal is an equilateral triangular air-hole structure with a lattice constant of 400 nm to 450 nm, a side length of 360 nm to 410 nm for the equilateral triangles, an etching depth of 400 nm to 600 nm, and an aperture wall tilt angle of 5° to 32°. The deposited SiO2 mask is then removed using reactive ion etching (RIE). S24. On the surface of a single-lattice three-dimensional asymmetric photonic crystal 10, P-type Al is further grown from bottom to top using MOCVD. x2 In 1-x2 As lower confinement layer 3 and P-type InP connection layer 2; S25. Using photoresist mask and ultraviolet exposure technology, an electrode contact hole pattern is formed on the surface of the P-type InP interconnect layer 2. After depositing SiO2 with a thickness of 2μm~4μm, a bottom insulating layer 11 is formed by wet etching technology. S26. Using magnetron sputtering technology, titanium (50nm~100nm) and gold (450nm~550nm) are sequentially sputtered at the electrode contact holes of the P-type InP interconnect layer 2 to form a P-type electrode 1. Subsequently, acetone is used to remove the surface photoresist and the metal layer in the non-electrode areas is stripped. S27. The back side of the N-type InP substrate 8 is thinned and polished using a chemical mechanical polishing machine to remove surface defects and obtain a smooth mirror finish. S28. Using magnetron sputtering technology, germanium (50nm~100nm) and gold (450nm~550nm) are sequentially sputtered on the back side of the thinned N-type InP substrate 8 to form an N-type electrode 9; S29. Use a dicing machine to cut the epitaxial wafer into individual chips, then use a wire bonding machine to connect the chips to the packaging base, package them, and complete optical and electrical function tests to ensure that the chips have 1310nm high-power circularly polarized single-mode vertical light output capability. Example 3:

[0028] A method for fabricating a 1310nm three-lattice PCSEL composite chip based on a three-dimensional asymmetric photonic crystal, comprising: S31. Select an N-type InP substrate 8, immerse it in deionized water for 5-10 minutes to remove surface impurities, then place the substrate in a beaker containing acetone and ultrasonically clean it for 2 minutes to remove grease and other organic matter soluble in acetone. Next, place the substrate in a beaker containing ethanol and ultrasonically clean the acetone on the surface. Finally, immerse it in deionized water for 2 minutes to remove residual alcohol on the surface, and dry the substrate with a nitrogen gun. S32. A PCSEL chip epitaxial structure is grown using metal-organic chemical vapor phase epitaxy (MOCVE). By controlling process parameters such as reaction temperature, precursor flow rate, carrier gas flow rate, reaction pressure, and deposition time, materials of different thicknesses and doping levels are obtained. N-type Al₂O₃ is sequentially grown from bottom to top on the surface of an N-type InP substrate 2. x1 In 1-x1 As lower confinement layer 3, quantum well active region 4, P-type Al y In 1-y As electron blocking layer 5 and p-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer 6; S33. A SiO2 layer with a thickness of 100nm~200nm was deposited as a mask for the P-type functional layer 4 using plasma-enhanced chemical vapor deposition (PECVD). A ZEP (Zero-Electronic Photonic Etching) layer with a thickness of 260nm~300nm was then spin-coated at a speed of 2500rpm~3000rpm. After exposure and development using electron beam lithography (EBRT), a three-lattice photonic crystal pattern was obtained. The SiO2 mask was then etched using inductively coupled plasma etching (ICP-lithography) to form the pattern. The ZEP was removed using plasma 300 (O2 flow rate 0 ml / min, N2 flow rate 300 ml / min, power 300W). The P-type functional layer 4 was then etched to form the three-lattice three-dimensional asymmetric photonic crystal 10. Figure 6 As shown, the lattice unit of the three-lattice two-dimensional photonic crystal consists of elliptical air holes with a lattice constant of 380 nm to 430 nm, a major axis of 200 nm to 240 nm, and a minor axis of 100 nm to 140 nm. The three air holes can have the same or different sizes. The etching depth is 400 nm to 600 nm, and the hole wall tilt angle is 5° to 32°. The etching depth of the three air holes can be the same or different. The deposited SiO2 mask is then removed using reactive ion etching (RIE). S34. On the surface of the dual-lattice three-dimensional asymmetric photonic crystal 10, P-type Al is further grown from bottom to top using MOCVD. x2 In 1-x2 As lower confinement layer 3 and P-type InP connection layer 2; S35. Using photoresist mask and ultraviolet exposure technology, an electrode contact hole pattern is formed on the surface of the P-type InP interconnect layer 2. After depositing SiO2 with a thickness of 2μm~4μm, a bottom insulating layer 11 is formed by wet etching technology. S36. Using magnetron sputtering technology, titanium (50nm~100nm) and gold (450nm~550nm) are sequentially sputtered at the electrode contact holes of the P-type InP interconnect layer 2 to form a P-type electrode 1. Subsequently, acetone is used to remove the surface photoresist and the metal layer in the non-electrode areas is stripped. S37. The back side of the N-type InP substrate 8 is thinned and polished using a chemical mechanical polishing machine to remove surface defects and obtain a smooth mirror finish. S38. Using magnetron sputtering technology, germanium (50nm~100nm) and gold (450nm~550nm) are sequentially sputtered on the back side of the thinned N-type InP substrate 8 to form an N-type electrode 9; S39. Use a dicing machine to cut the epitaxial wafer into individual chips, then use a wire bonding machine to connect the chips to the packaging base, package them, and complete optical and electrical function tests to ensure that the chips have 1310nm high-power circularly polarized single-mode vertical light output capability.

[0029] The advantages of this invention are: This invention creates a vertically emitting laser chip with an asymmetric feedback mechanism by etching a three-dimensional asymmetric photonic crystal structure in the P-type functional layer region of a PCSEL chip, effectively suppressing high-order transverse mode and multimode interference. The three-lattice photonic crystal is composed of air holes of different sizes and shapes. By introducing in-plane and vertical structural asymmetry, selective coupling and polarization control of the emitted mode are achieved. This structure significantly improves the purity of circularly polarized light, optimizes the laser's directionality and single-mode stability, and ultimately realizes PCSEL laser output with high polarization selectivity, low divergence angle, and high beam quality.

[0030] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A three-dimensional asymmetric photonic crystal laser, characterized in that, The epitaxial structure of the laser includes, from top to bottom, an N-type electrode, an N-type InP substrate, and an N-type Al electrode. x1 In 1-x1 As upper confinement layer, quantum well active region, p-type Al y In 1-y As electron blocking layer, P-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer, P-type Al x2 In 1-x2 An As-type confinement layer, a P-type InP interconnect layer, and a bottom insulating layer and a P-type electrode at the bottom layer; wherein, the P-type Ga... z1 In 1-z1 As z2 P 1-z2 A three-dimensional asymmetric photonic crystal is etched on the functional layer. By breaking the symmetry of the photonic crystal, chiral properties are introduced, enabling the chip to emit a single-mode beam with left-handed or right-handed circular polarization perpendicularly. The three-dimensional asymmetric photonic crystal is formed in the following way: based on a two-dimensional photonic crystal, the XY plane symmetry is broken by adjusting the arrangement of lattice units or changing the shape and size of air holes; in the Z direction, the symmetry is further broken by changing the depth, shape, or arrangement direction of the air holes, thereby realizing an overall three-dimensional asymmetric structure; wherein, the three-dimensional asymmetric structure is used to optimize the photonic bandgap characteristics and improve the polarization selectivity and chiral control capability of vertically emitted light; The polarization control mechanism of the three-dimensional asymmetric photonic crystal is based on the phase difference condition; where and are the electric fields inside the lattice face, respectively. E y and E x The additional phase introduced by the component, the phase difference being caused by the shape asymmetry of the lattice unit, the difference in etching depth, and the tilt angle of the air hole. θ A joint decision.

2. The three-dimensional asymmetric photonic crystal laser as described in claim 1, characterized in that, The three-dimensional asymmetric photonic crystal includes one of single-lattice photonic crystal, dual-lattice photonic crystal and multi-lattice photonic crystal, with the characteristic size of different lattice units ranging from 300 nm to 500 nm.

3. The three-dimensional asymmetric photonic crystal laser as described in claim 1 or 2, characterized in that, The lattice unit of the three-dimensional asymmetric photonic crystal is composed of air holes of different shapes, including one or more of circular, triangular, elliptical, trapezoidal and hexagonal shapes. Different lattice units are composed of air holes of different etching depths and shapes. The etching depth of the lattice unit is 300nm~1100nm.

4. The three-dimensional asymmetric photonic crystal laser as described in claim 1, characterized in that, The bottom insulating layer is etched with electrode contact holes to form P-type electrodes. The P-type electrodes are sputtered into the electrode contact holes and connected to the P-type InP interconnect layer. The bottom insulating layer is made of dielectric material to reduce current leakage and improve the electrical performance of the chip. The material of the bottom insulating layer includes SiO2, Si3N4 or Al2O3, and the thickness is 100nm~500nm.

5. The three-dimensional asymmetric photonic crystal laser as described in claim 1, characterized in that, The lattice constant of the three-dimensional asymmetric photonic crystal is 400nm~450nm, the etching depth is 400nm~600nm, the hole wall inclination angle is 5°~32°, and the air hole duty cycle is 35%~65%.

6. The three-dimensional asymmetric photonic crystal laser as described in claim 1, characterized in that, In the epitaxial structure, the N-type doping source includes one or more of Si2H6, SiH4, Fe(C2H5)2, TMGa, and TEGa, and the P-type doping source includes one or more of BeMe2, DMZn, CBr4, Cp2Mg, and (CH3)2Mg.

7. The three-dimensional asymmetric photonic crystal laser as described in claim 1, characterized in that, The active region of the quantum well is a multi-quantum-well structure, grown using AlGaInAs materials with different compositions, wherein the thickness of the quantum well is 5nm~10nm and the thickness of the quantum barrier is 7nm~12nm. In the N-type Al x1 In 1-x1 In the upper confinement layer of As, x1 is 0.3~0.6; In the P-type Al x2 In 1-x2 In the lower confinement layer of As, x2 is 0.3~0.6; In the P-type Al y In 1-y In the As electron blocking layer, y is 0.3~0.6; In the P-type Ga z1 In 1-z1 As z2 P 1-z2 In the functional layer, z1 is 0.1~0.3 and z2 is 0.2~0.

4.

8. A method for fabricating a three-dimensional asymmetric photonic crystal laser as described in any one of claims 1 to 7, characterized in that, include: Select an N-type InP substrate; N-type Al was sequentially grown on the N-type InP substrate using molecular beam epitaxy, liquid phase epitaxy, or organometallic vapor phase epitaxy. x1 In 1-x1 As upper confinement layer, quantum well active region, p-type Al y In 1-y As electron blocking layer and p-type Ga z1 In 1-z1 As z2 P 1-z2 Functional layer; Electron beam lithography was used in the study of P-type Ga z1 In 1-z1 As z2 P 1-z2 A three-dimensional asymmetric photonic crystal pattern is defined on the functional layer, and then the three-dimensional asymmetric photonic crystal is etched using inductively coupled plasma etching technology. Continue growing P-type Al on the etched three-dimensional asymmetric photonic crystal surface x2 In 1-x2 As lower confinement layer and P-type InP connection layer; After depositing a bottom insulating layer on the surface of the P-type InP interconnect layer, electrode contact holes of the P-type electrode are formed by photoresist mask and ultraviolet exposure technology, and then P-type electrodes are deposited at the electrode contact holes by magnetron sputtering technology. The back of the chip is thinned and polished by chemical mechanical polishing. Then, an N-type electrode window pattern is obtained on the surface of the N-type InP substrate using photoresist mask and ultraviolet exposure technology. Finally, N-type electrodes are sputtered on the surface of the N-type InP substrate using magnetron sputtering technology. The chip is then cleaved, wire-bonded, and packaged.

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