Multi-channel parallel operation equipment synchronization control method based on EtherCAT distributed clock

Abstract

The invention provides a multi-channel parallel operation equipment synchronous control method based on an EtherCAT distributed clock, and the method is used for controlling a plurality of charging and discharging channels which are connected in parallel to synchronously execute the starting, switching or stopping operation of current, and the plurality of charging and discharging channels serve as EtherCAT slave stations to be connected to an EtherCAT master station. The method comprises the following steps: S1, configuring the EtherCAT master station and all the EtherCAT slave stations to be in a DC distributed clock synchronization mode, so that each EtherCAT slave station aligns a distributed clock with a reference clock to realize nanosecond-level time synchronization precision; wherein the distributed clock has a nanosecond level time resolution; and high-precision time alignment between the master station and each slave station can be realized by utilizing a DC distributed clock technology of EtherCAT. And at a set moment, all EtherCAT slave stations almost simultaneously trigger DC clock interruption, and switching operation of a current target value of a controller is executed in the high-priority interruption service function, so that synchronous control of current starting, switching and stopping among a plurality of channels is realized, and a synchronization error can reach a nanosecond level.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic control, more particularly, to a multi-channel parallel machine equipment synchronization control method based on EtherCAT distributed clock. BACKGROUND

[0002] In a large-current charge-discharge equipment parallel system based on the EtherCAT (Ethernet for Control Automation Technology) protocol, multiple EtherCAT slave stations (i.e. independent channels) realize high-speed and real-time communication and control through an EtherCAT bus. Each EtherCAT slave station node is in a RunFree working mode in normal operation, that is, each independently executes a charge-discharge task according to local logic without the need for continuous intervention of the master station. When the master station issues a unified start command, the synchronization manager (SM) of each EtherCAT slave station will receive a synchronization event signal (SM Event), triggering a local interrupt service program (ISR).

[0003] However, under the existing implementation mechanism, the interrupt service function is only responsible for temporarily storing the start command and related parameters issued by the master station in the local buffer, and does not immediately execute the actual start operation. The real start action needs to wait for the triggering of the timing polling task inside each EtherCAT slave station, and the task period is usually set to about 1ms. Since the timing tasks of each EtherCAT slave station are independent of each other and are not strictly aligned, there is a maximum time deviation of about 1ms in the actual start time.

[0004] In addition, physical layer factors further exacerbate the start synchronization error. Each EtherCAT slave station node is usually equipped with two EtherCAT network interfaces, and the hardware processing delay is about 1μs when data is forwarded between adjacent nodes; as the number of parallel channels increases, this delay accumulates in a linear topology. At the same time, the actual length of the connecting network cable also introduces additional transmission delay (typical value about 5ns / m), which cannot be ignored in large-scale deployment or multi-node connected systems.

[0005] In summary, the synchronization accuracy of the current system in the multi-channel parallel machine start process is restricted by the following multiple factors: Inconsistent phase of local timing polling tasks of each EtherCAT slave station; Cumulative hardware delay generated by EtherCAT frame transmission between multiple nodes; Propagation delay introduced by the physical length of the network cable; Non-deterministic interval between interrupt response and task scheduling.

[0006] These factors together make it difficult for high-current charging and discharging equipment to achieve high-precision time synchronization at startup, which may affect the overall dynamic response consistency, current balance and safety of the system. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a synchronous control method for multi-channel parallel devices based on EtherCAT distributed clock, which solves the problem of asynchronous control of multi-channel parallel devices, in order to address the shortcomings of the above-mentioned technical solutions.

[0008] This invention provides a method for synchronous control of multi-channel parallel devices based on an EtherCAT distributed clock, used to control multiple parallel charging and discharging channels to synchronously perform current start, switching, or stop operations, wherein the multiple charging and discharging channels are connected as EtherCAT slave stations to an EtherCAT master station; the method includes the following steps: S1, Configure the EtherCAT master station and all EtherCAT slave stations in DC distributed clock synchronization mode, so that each EtherCAT slave station aligns the distributed clock with the reference clock to achieve nanosecond-level time synchronization accuracy; wherein, the distributed clock has nanosecond-level time resolution. S2, the EtherCAT master station sends process data object (PDO) messages at fixed intervals. The PDO message contains a target step instruction, which includes at least the working mode, current setting value, and working start flag. When two adjacent steps have the same working mode, their working start flags are different to distinguish consecutive identical working modes. S3, Configure Sync0 synchronization interrupt in each of the EtherCAT slave stations, and set the trigger time of the Sync0 synchronization interrupt to a preset offset time point within the PDO cycle, so that all EtherCAT slave stations trigger the Sync0 synchronization interrupt synchronously at the same absolute time in DC distributed clock synchronization mode. S4, in the Sync0 synchronous interrupt service function, each EtherCAT slave station determines whether it has received a new target step instruction; if it has, it immediately updates the current target value of the local controller and synchronously executes the current start, switch or stop operation based on the current target value.

[0009] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, the transmission period of the PDO message in step S2 is 100 microseconds to 500 microseconds.

[0010] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, the working start flag in step S2 is an integer value in the range of 0 to 255, and it increases monotonically in sequence or cyclically in modulo 256 in the working step sequence.

[0011] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, the working mode in step S2 is any one of the following: standby mode, constant current mode, constant voltage mode, constant power mode, constant resistance mode, standby mode, constant current and constant voltage mode, pulse mode, ramp mode, DC internal resistance test mode, or operating condition simulation mode.

[0012] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, the current setting value in step S2 is issued in the form of an integer multiple of 1000, where a positive value represents the charging current and a negative value represents the discharging current.

[0013] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, in step S3, the PDO message flows sequentially through each of the EtherCAT slave stations via the network cable. Each time it passes through an EtherCAT slave station, a hardware transmission delay of about 1 microsecond is generated. However, the hardware transmission delay is compensated by the DC distributed clock synchronization mode, so that the Sync0 synchronization interrupt of each of the EtherCAT slave stations can still be triggered at the same absolute moment.

[0014] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, after each EtherCAT slave station receives the PDO message in step S3, it triggers an interrupt service function through an SM Event to cache the target step instruction, and then reads and applies the target step instruction in the subsequently triggered Sync0 synchronization interrupt.

[0015] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, the preset offset time point in step S3 is not less than the maximum transmission delay required for the PDO message to flow through all EtherCAT slaves, so as to ensure that each EtherCAT slave has completed the reception of the target step instruction before triggering the Sync0 synchronization interrupt; wherein, the maximum transmission delay is N×1 microseconds, N is the number of EtherCAT slaves, and the PDO message generates a hardware transmission delay of about 1 microsecond for each EtherCAT slave.

[0016] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, the operation of updating the current target value in the Sync0 synchronous interrupt service function in step S3 is performed in a high-priority interrupt context to ensure that the operation is not interrupted by other low-priority tasks or interrupts.

[0017] In the multi-channel parallel device synchronization control method based on EtherCAT distributed clock described in this invention, the number of the multiple charging and discharging channels is 2 to 32, and each charging and discharging channel is connected in parallel as an independent EtherCAT slave station, respectively outputting current. , , and .

[0018] The present invention provides a multi-channel parallel equipment synchronization control method based on EtherCAT distributed clock, which utilizes EtherCAT's DC distributed clock technology to achieve high-precision time alignment between the master station and each slave station. At a set time, all EtherCAT slave stations trigger a DC clock interrupt almost simultaneously, and execute a switching operation of the controller current target value within the high-priority interrupt service function. This achieves synchronous control of current start-up, switching, and stopping among multiple channels, with synchronization errors reaching the nanosecond level. Applying this method to high-current parallel equipment significantly improves the dynamic current response speed and effectively solves the problem of uneven current during startup. While achieving rapid start-up and shutdown, the equipment's operational safety is enhanced, and the failure rate during startup is further reduced. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating an embodiment of the multi-channel parallel device synchronization control method based on EtherCAT distributed clock of the present invention; Figure 2 This is a schematic diagram of the PDO message structure in the multi-channel parallel device synchronization control method based on EtherCAT distributed clock of the present invention; Figure 3 This is the Sync0 interrupt triggering timing diagram in the multi-channel parallel device synchronization control method based on EtherCAT distributed clock of the present invention; Figure 4 This is a schematic diagram of the hardware topology and current synchronization response in the multi-channel parallel device synchronization control method based on EtherCAT distributed clock of the present invention; Figure 5 This is a comparison chart of the current start-up curves of multi-channel parallel devices under no-synchronization and synchronous control in the multi-channel parallel device synchronization control method based on EtherCAT distributed clock of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] like Figures 1-5 As shown, Figure 1 This is a flowchart illustrating an embodiment of a multi-channel parallel device synchronization control method based on an EtherCAT distributed clock according to the present invention. The method provides a multi-channel parallel device synchronization control method based on an EtherCAT distributed clock, used to control multiple parallel charging / discharging channels to synchronously perform current start, switching, or stop operations, wherein the multiple charging / discharging channels are connected as EtherCAT slave stations to an EtherCAT master station; the method includes the following steps: In step S1, the EtherCAT master station and all EtherCAT slave stations are configured in DC distributed clock synchronization mode, so that each EtherCAT slave station aligns the distributed clock with the reference clock to achieve nanosecond-level time synchronization accuracy; wherein, the distributed clock has nanosecond-level time resolution. In step S2, the EtherCAT master station sends process data object (PDO) messages at fixed intervals. The PDO message contains a target step instruction, which includes at least the operating mode, current setting value, and operating start flag. When two adjacent steps have the same operating mode, their operating start flags are different to distinguish consecutive identical operating modes. In step S3, a Sync0 synchronization interrupt is configured in each of the EtherCAT slave stations, and the trigger time of the Sync0 synchronization interrupt is set to a preset offset time point within the PDO cycle, so that all EtherCAT slave stations trigger the Sync0 synchronization interrupt synchronously at the same absolute time in DC distributed clock synchronization mode. In step S4, within the Sync0 synchronous interrupt service function, each EtherCAT slave station determines whether it has received a new target step instruction; if so, it immediately updates the current target value of the local controller and synchronously executes the current start, switch, or stop operation based on the current target value.

[0023] In one embodiment, the transmission period of the PDO message in step S2 is 100 microseconds to 500 microseconds.

[0024] In one embodiment, the work start flag in step S2 is an integer value in the range of 0 to 255, and it is monotonically increased sequentially or cyclically increased modulo 256 in the work step sequence.

[0025] In one embodiment, the operating mode in step S2 is any one of the following: standby mode, constant current mode, constant voltage mode, constant power mode, constant resistance mode, standby mode, constant current and constant voltage mode, pulse mode, ramp mode, DC internal resistance test mode, or operating condition simulation mode.

[0026] In one embodiment, the current setting value in step S2 is issued in the form of an integer multiple of 1000, where a positive value represents the charging current and a negative value represents the discharging current.

[0027] In one embodiment, in step S3, the PDO message flows sequentially through each of the EtherCAT slave stations via the network cable. Each time it passes through an EtherCAT slave station, a hardware transmission delay of about 1 microsecond is generated. However, the hardware transmission delay is compensated by the DC distributed clock synchronization mode, so that the Sync0 synchronization interrupt of each of the EtherCAT slave stations can still be triggered at the same absolute moment.

[0028] In one embodiment, after each EtherCAT slave receives the PDO message in step S3, it triggers an interrupt service function through an SM Event to cache the target step instruction, and then reads and applies the target step instruction in the subsequently triggered Sync0 synchronization interrupt.

[0029] In one embodiment, the preset offset time point in step S3 is not less than the maximum transmission delay required for the PDO message to flow through all EtherCAT slaves, so as to ensure that each EtherCAT slave has completed the reception of the target step instruction before triggering the Sync0 synchronization interrupt; wherein, the maximum transmission delay is N×1 microseconds, N is the number of EtherCAT slaves, and the PDO message generates a hardware transmission delay of about 1 microsecond for each EtherCAT slave it passes through.

[0030] In one embodiment, the operation of updating the current target value in the Sync0 synchronous interrupt service function in step S3 is performed in a high-priority interrupt context to ensure that the operation is not interrupted by other low-priority tasks or interrupts.

[0031] In one embodiment, the number of the plurality of charging and discharging channels is 2 to 32, and each charging and discharging channel is connected in parallel as an independent EtherCAT slave station, and outputs current respectively. , , and .

[0032] This invention relates to a battery charging and discharging test system applied in the field of power electronics, aiming to solve the problem of asynchronous current start-up, switching, or stopping during multi-channel parallel operation.

[0033] The multi-channel parallel device in this embodiment consists of four independent charging / discharging channels (Channel 1 to Channel 4) connected in parallel. Each channel acts as an EtherCAT slave station, connected in series with the EtherCAT master station via standard Ethernet cables, forming a typical linear topology. Each channel outputs its own signal. , , and Together, they provide or absorb large currents to the battery under test.

[0034] All EtherCAT slaves use EtherCAT slave controller (ESC) chips that support DC functionality and have a built-in 64-bit high-precision hardware clock; the master station uses an industrial PC or embedded controller that supports DC synchronization.

[0035] First, the EtherCAT master and all EtherCAT slaves are configured in DC distributed clock synchronization mode. During the initialization process, the master designates the first DC-enabled EtherCAT slave as the reference clock source, and the remaining EtherCAT slaves align their local 64-bit hardware clocks with this reference clock using DC distributed clock synchronization mode. After several synchronization cycles, the clock error between the EtherCAT slaves stabilizes at the nanosecond level (typically <100 ns), achieving a time resolution of 1 ns, laying the foundation for high-precision synchronization control.

[0036] The EtherCAT master station sends Process Data Object (PDO) messages to the EtherCAT slave station chain at fixed intervals. These messages use the standard EtherCAT frame format and flow sequentially through each EtherCAT slave station, with each slave station extracting its own PDO message. In this embodiment, the preferred PDO message transmission period is 200 microseconds.

[0037] Each channel's corresponding PDO message contains a target process step instruction, and its structure includes at least the following three fields: Operating mode (8 bits): Values ​​range from 0x00 to 0x0A, with specific definitions as follows: 0x00: Standby mode 0x01: Constant voltage mode (positive value indicates charging, negative value indicates discharging) 0x02: Constant current mode (positive value indicates charging, negative value indicates discharging) 0x03: Constant power mode (positive value indicates charging, negative value indicates discharging) 0x04: Constant resistance mode (positive value indicates charging, negative value indicates discharging) 0x05: Shelved Mode 0x06: Constant current and constant voltage mode (positive value indicates charging, negative value indicates discharging) 0x07: Pulse Mode 0x08: Ramp Mode 0x09: DC Internal Resistance Test Mode 0x0A: Operating Condition Simulation Mode Current setting (32-bit signed integer): Issued as a multiple of the actual current value, 1000 times. For example, +10000 represents a +10.0 A charging current. 5000 means 5.0 A discharge current.

[0038] Work start flag (8 bits): An integer ranging from 0 to 255, monotonically increasing sequentially in the work step sequence; after reaching 255, it wraps back to 0 and increments cyclically modulo 256. The key design feature is that when two adjacent work steps have the same working mode, their work start flags must be different. This ensures that the EtherCAT slave can accurately identify the arrival of a new target work step instruction, avoiding missed updates due to instruction duplication.

[0039] Configure a Sync0 synchronous interrupt in each EtherCAT slave station, and set its trigger time to a preset offset time point within the PDO cycle. In this embodiment, the PDO transmission cycle is 200 microseconds, and the preset offset time point is 30% of the PDO transmission cycle, which corresponds to a time of 60 microseconds.

[0040] It should be noted that PDO messages flow sequentially through each EtherCAT slave station on the physical link. Each EtherCAT slave station experiences a hardware transmission delay of approximately 1 microsecond due to ESC chip processing. For a system with N=4 EtherCAT slave stations, the maximum delay for the last EtherCAT slave station to receive the complete PDO message is approximately 4 microseconds. Since the Sync0 interrupt is triggered at 60 microseconds, which is much greater than this delay, all EtherCAT slave stations have already completed the reception and buffering of the PDO message via the SM Event before the Sync0 interrupt arrives.

[0041] More importantly, in DC distributed clock synchronization mode, despite the link transmission delay, the hardware clocks of all EtherCAT slaves are aligned, so they will trigger the Sync0 interrupt synchronously at the same absolute moment (e.g., t=k×200μs+60μs, where k is an integer), achieving global time alignment.

[0042] When the Sync0 synchronization interrupt is triggered, each EtherCAT slave station enters its interrupt service function. This interrupt is configured as the highest priority in the system and is not affected by other low-priority tasks or interrupts during execution. The following operations are performed within the interrupt service function: Determine whether a new target step instruction has been received (by detecting whether the work start flag has changed). If a new target step instruction is detected, the cached current setting value is immediately read and the current target value of the local controller PI is updated. The local controller PI adjusts the PWM duty cycle based on the new current target value to drive the power circuit and synchronously execute the current start, switching or stop operations.

[0043] Thus, all channels update their outputs at the same time based on the same target step instructions, achieving highly synchronized current waveform control.

[0044] In DC distributed clock synchronization mode, the current response curves of the four channels almost completely overlap, with a rise / fall time deviation of less than 500 nanoseconds. In contrast, in the traditional RunFree mode (where each EtherCAT slave station relies on 1ms software timer polling), the start-up deviation between channels can reach the order of 1 millisecond, leading to a serious problem of uneven start-up current.

[0045] This invention successfully reduces the multi-channel current synchronization control error from the millisecond level to the nanosecond level, significantly improving the current dynamic response speed, optimizing the start-up current sharing performance, and reducing the risk of failure during equipment start-up and shutdown.

[0046] Furthermore, the operating modes of the above embodiments include, but are not limited to, the aforementioned 11 modes. Taking 4 channels, 200μs PDO period, and 60μs Sync0 offset as an example, the present invention is not limited thereto. Those skilled in the art can adjust them according to actual needs.

[0047] By configuring the EtherCAT master and EtherCAT slave stations to DC distributed clock synchronization mode and combining this with the Sync0 high-priority interrupt service mechanism, nanosecond-level precision current synchronization control is achieved in a multi-channel parallel charging and discharging system. Compared with existing technologies, this invention has the following significant technical advantages: By aligning the 64-bit hardware clocks of each EtherCAT slave station using the DC distributed clock synchronization mode, all channels can trigger the Sync0 interrupt synchronously in absolute time. The current target value is updated uniformly in the interrupt service function, thereby reducing the synchronization error of multi-channel current start-up, switching or stopping from the millisecond level (typical value about 1 ms) of the traditional solution to the nanosecond level (measured <500 ns), which significantly improves the consistency of the system's dynamic response.

[0048] In high-current parallel operation scenarios, if the start-up times of each channel are inconsistent, it can lead to a severe imbalance in instantaneous current distribution, potentially triggering overcurrent protection or causing stress concentration in devices. This invention ensures that all channels begin adjusting their output at the same time, resulting in a uniform rise / fall of the parallel current. This optimizes the current sharing performance during the startup phase and improves system reliability and safety.

[0049] Although the PDO message will generate a cumulative transmission delay of about 1μs as it flows through each EtherCAT slave station on the physical link, this invention ensures that all EtherCAT slave stations have completed receiving the instruction before execution by reasonably setting the trigger offset time of the Sync0 interrupt (such as 30% of the PDO message transmission period); at the same time, the DC distributed clock synchronization mode compensates for the clock drift, so that the link delay no longer affects the absolute time consistency of the synchronization action.

[0050] Because the control commands take effect immediately in the high-priority Sync0 interrupt, the interference from operating system task scheduling jitter or low-priority interrupts is avoided, the current response is faster, and the dynamic waveform is closer to the ideal step characteristics, meeting the needs of demanding application scenarios such as high-precision battery testing and pulse condition simulation.

[0051] This invention is based on the standard EtherCAT protocol stack and a general-purpose ESC chip. It requires no additional hardware and can be deployed simply by configuring the DC distributed clock synchronization mode, Sync0 interrupt, and PDO mapping through software. It is suitable for various parallel charging and discharging devices with 2 to 32 channels and has good scalability and industrialization value.

[0052] It fundamentally solves the problem of current asynchrony caused by communication delay and asynchronous scheduling in multi-channel parallel equipment, which not only improves the system control performance, but also enhances the safety and stability of equipment operation. It is especially suitable for fields such as high-power battery testing systems, energy storage converters and high-precision programmable power supplies.

[0053] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0054] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0055] Therefore, the above description is only a preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for synchronously controlling a plurality of parallel charging and discharging channels based on EtherCAT distributed clock, for controlling the plurality of parallel charging and discharging channels to synchronously perform current starting, switching or stopping operation, wherein the plurality of charging and discharging channels are connected to an EtherCAT master station as EtherCAT slaves; characterized in that, The method comprises the following steps: S1, configure the EtherCAT master station and all EtherCAT slave stations into a DC distributed clock synchronization mode, so that each EtherCAT slave station aligns the distributed clock with the reference clock, and achieves nanosecond-level time synchronization accuracy; wherein the distributed clock has nanosecond-level time resolution; S2, the EtherCAT master station sends a process data object (PDO) message at a fixed period, the PDO message contains target step instructions, and the target step instructions at least include a working mode, a current set value, and a working start flag; wherein when the working modes of two adjacent steps are the same, the working start flags are different to distinguish continuous same working modes; S3, configure a Sync0 synchronization interrupt in each EtherCAT slave station, and set the trigger time of the Sync0 synchronization interrupt as a preset offset time point in the PDO period, so that all EtherCAT slave stations trigger the Sync0 synchronization interrupt at the same absolute time under the DC distributed clock synchronization mode; S4, in the Sync0 synchronization interrupt service function, each EtherCAT slave station judges whether a new target step instruction has been received; if received, immediately update the current target value of the local controller, and based on the current target value, synchronously execute the start, switching or stop operation of the current.

2. The EtherCAT distributed clock-based multi-channel parallel machine device synchronization control method of claim 1, wherein, The sending period of the PDO message in the step S2 is 100 microseconds to 500 microseconds.

3. The EtherCAT distributed clock-based multi-channel parallel machine device synchronization control method of claim 1, wherein, The working start flag in the step S2 is an integer value in the range of 0-255, and is monotonically increasing or cyclically increasing in a modulo 256 manner in the sequence of steps.

4. The EtherCAT distributed clock-based multi-channel parallel machine device synchronization control method of claim 1, wherein, The working mode in the step S2 is any one of the following: standby mode, constant current mode, constant voltage mode, constant power mode, constant resistance mode, standby mode, constant current and constant voltage mode, pulse mode, slope mode, direct current resistance test mode or working condition simulation mode.

5. The EtherCAT distributed clock based multi-channel parallel machine device synchronization control method of claim 1, wherein, The current set value in the step S2 is issued in the form of an integer of 1000 times, wherein a positive value represents a charging current and a negative value represents a discharging current.

6. The EtherCAT distributed clock-based multi-channel parallel machine device synchronization control method of claim 1, wherein, In the step S3, the PDO message flows through each EtherCAT slave station in turn via a network cable, and each EtherCAT slave station generates a hardware transmission delay of about 1 microsecond, but the hardware transmission delay is compensated by the DC distributed clock synchronization mode, so that the Sync0 synchronization interrupt of each EtherCAT slave station can still be triggered at the same absolute time.

7. The EtherCAT distributed clock-based multi-channel parallel machine device synchronization control method according to claim 6, characterized in that, In the step S3, after each EtherCAT slave station receives the PDO message, the target step instruction is cached by triggering an SM Event event interrupt service function, and the target step instruction is read and applied in the subsequently triggered Sync0 synchronization interrupt.

8. The EtherCAT distributed clock-based multi-channel parallel machine device synchronization control method of claim 7, wherein, In the step S3, the preset offset time point is not less than the maximum transmission delay required for the PDO message to pass through all EtherCAT slaves, so as to ensure that each EtherCAT slave has completed the reception of the target step instruction before triggering the Sync0 synchronization interrupt; wherein the maximum transmission delay is N*1 microsecond, N is the number of EtherCAT slaves, and the hardware transmission delay of about 1 microsecond is generated for each EtherCAT slave passed by the PDO message.

9. The EtherCAT distributed clock-based multi-channel parallel machine device synchronization control method of claim 8, wherein, In the step S3, the operation of updating the current target value in the Sync0 synchronization interrupt service function is executed in the context of a high-priority interrupt, so as to ensure that the operation is not interrupted by other low-priority tasks or interrupts.

10. The EtherCAT distributed clock based multi-channel parallel machine device synchronization control method of claim 1, wherein, The number of the plurality of charge-discharge channels is 2-32, each of the charge-discharge channels is connected in parallel as an independent EtherCAT slave station, and outputs current , , and .

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