GaN gate driver for EMI optimization during turn-on and turn-off

Abstract

An integrated circuit for driving a gate of a GaN power switching transistor in a switching power converter is provided. During a first portion of the on-period of the GaN power switch transistor, the integrated circuit charges the gate through a relatively high pull-up resistance. During a second portion of the on-period, the integrated circuit charges the gate through a relatively low pull-up resistance. During a first portion of an off period of the GaN power switch transistor, the integrated circuit discharges the gate through a relatively low pull-down resistor, and then discharges the gate through a relatively high pull-down resistor in response to a voltage of the gate falling below a threshold voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to switching power converters, and more particularly, to a gate driver for GaN power switching transistors that has EMI optimization functionality during both turn-on and turn-off. BACKGROUND

[0002] The use of gallium nitride (GaN) transistors has revolutionized power electronics systems. Similar GaN transistors have improved efficiency, higher power density, and faster switching capability compared to traditional metal oxide semiconductor field effect transistors (MOSFETs). However, the faster switching speed of GaN devices comes at the cost of increased electromagnetic interference (EMI) noise. The rapid voltage transitions brought on by increased switching speed can generate destructive EMI noise. For example, in a flyback converter, a power switching transistor can include an n-type GaN transistor with its drain connected to a primary winding and its source coupled to ground. Prior to the power switching transistor turning on, the drain is charged to the input voltage of the primary winding (or higher). The input voltage is rectified from an alternating current (AC) power supply and thus can exceed 100 V depending on the AC power supply cycle. With the power switching transistor fully on, the drain is grounded. Thus, the drain of the power switching transistor can experience a relatively high rate of voltage change (dV / dt) during the power switching transistor turn-on. A similar voltage change occurs during the power switching transistor turn-off. The rapid change in the drain voltage of the power switching transistor on turn-on and turn-off can result in undesirable levels of electromagnetic interference (EMI).

[0003] To reduce the EMI generated by power switching cycles, the conventional approach is to drive the power switching transistor on with a relatively complex drive circuit that includes a high voltage Miller capacitor, a bipolar junction transistor, a diode, and external resistors. The components of these drive circuits not only increase cost, but also take up board space. SUMMARY

[0004] According to one aspect of the disclosure, there is provided an integrated circuit for a switching power converter, the integrated circuit comprising: a gate drive circuit configured to charge a gate of a GaN power switching transistor through a variable pull-up resistance comprising a first pull-up resistance and a second pull-up resistance, and to discharge the gate of the GaN power switching transistor through a variable pull-down resistance comprising a first pull-down resistance and a second pull-down resistance, wherein the first pull-up resistance is greater than the second pull-up resistance, and wherein the second pull-down resistance is greater than the first pull-down resistance; and a gate drive control circuit configured to command the gate drive circuit to charge the gate through the first pull-up resistance during an initial first portion of an on period of the GaN power switching transistor, and to charge the gate through the second pull-up resistance during a second portion of the on period, wherein the gate drive control circuit is further configured to command the gate drive circuit to discharge the gate through the first pull-down resistance during an initial first portion of an off period of the GaN power switching transistor, and to discharge the gate through the second pull-down resistance during a second portion of the off period.

[0005] According to another aspect of the disclosure, there is provided a method of driving a gate of a GaN power switching transistor in a switching power converter, the method comprising: charging the gate through a first pull-up resistance during an initial portion of an on period of the GaN power switching transistor and while a gate voltage of the GaN power switching transistor is less than a first threshold voltage; charging the gate through a second pull-up resistance that is less than the first pull-up resistance during a second portion of the on period and while the gate voltage is greater than the first threshold voltage; discharging the gate through a first pull-down resistance during an initial portion of an off period of the GaN power switching transistor and while the gate voltage is greater than a first threshold voltage; and discharging the gate through a second pull-down resistance in response to the gate voltage falling below the first threshold voltage during a second portion of the off period, wherein the second pull-down resistance is greater than the first pull-down resistance.

[0006] According to another aspect of this disclosure, a switching power converter is provided, comprising: an inductor; a GaN power switching transistor connected to the inductor; and an integrated circuit configured to: charge the gate of the GaN power switching transistor through a first pull-up resistor during an initial first portion of an on-state period; charge the gate through a second pull-up resistor during a second portion of an on-state period; discharge the gate through a first pull-down resistor during an initial first portion of an off-state period; and discharge the gate through a second pull-down resistor during a second portion of an off-state period.

[0007] These and other aspects of the invention will be more fully understood after reading the following detailed description. Other aspects, features, and embodiments will become apparent to those skilled in the art upon reading the following description of specific exemplary embodiments in conjunction with the accompanying drawings. While features relating to certain embodiments and figures may be discussed below, all embodiments may include one or more advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more such features may also be used according to the various embodiments discussed herein. Similarly, while exemplary embodiments may be discussed below as embodiments of devices, systems, or methods, it should be understood that these exemplary embodiments can be implemented in various devices, systems, and methods. Attached Figure Description

[0008] Figure 1 A flyback converter according to one aspect of the present disclosure is shown, the flyback converter having an integrated circuit for driving the gate of a GaN power switching transistor.

[0009] Figure 2 This is based on one aspect of the disclosure. Figure 1 A more detailed view of the integrated circuit.

[0010] Figure 3 One aspect of this disclosure is shown. Figure 2 Some operating waveforms of integrated circuits.

[0011] The embodiments of this disclosure and their advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more figures. Detailed Implementation

[0012] To avoid the complexity of using Miller capacitors, adaptive gate drivers have been developed for driving the gate voltage of silicon-based switching power converters. In such adaptive gate drivers, the output impedance of the gate driver changes according to the gate voltage to reduce electromagnetic interference (EMI) noise during the conduction of the power switching transistor. The output impedance changes accordingly as the gate voltage passes through different threshold voltages. Some or all of the threshold voltages are based on the Miller plateau level of the gate voltage. As is known in the MOSFET field, a Miller plateau occurs after the gate-to-source voltage of the power switching transistor has reached the transistor threshold voltage. Then, the drain voltage begins to decrease due to channel conduction, which tends to pull the gate voltage down due to the gate-to-drain parasitic capacitance of the power switching transistor M1. The gate-to-drain parasitic capacitance is highly nonlinear, making it relatively small when the drain voltage begins to decrease, and increasing in size as the drain voltage approaches ground. The end result is that the gate voltage remains relatively constant during the Miller plateau period, which ends once the gate-to-drain capacitance discharges.

[0013] This dependence on the Miller plateau voltage complicates the transplantation of conventional adaptive gate drivers for silicon-based power switching transistors to drive the gate voltage of GaN power switching transistors. Compared to silicon-based power switching transistors, gallium nitride (GaN) power switching transistors offer improved efficiency, increased power density, and faster switching capabilities. Therefore, GaN power switching transistors have become a popular choice for AC-DC switching power converters, such as flyback converters. However, the Miller plateau voltage is relatively ambiguous for GaN devices. Consequently, due to the ambiguity of the Miller plateau voltage in GaN devices, conventional adaptive gate drivers face challenges in accurately setting their threshold voltage. This paper presents an improved gate driver for cycling GaN power switching transistors that is independent of detecting the Miller plateau voltage.

[0014] The following discussion will focus on the gate driver of a flyback converter implementation using GaN power switching transistors; however, it is understood that the improved gate driver disclosed herein can be advantageously used to drive any suitable GaN power switching transistor, such as GaN power switching transistors in buck or boost converters. Figure 1An example flyback converter 100 is shown, which includes an improved gate driver located in an integrated circuit 105. The flyback converter 100 includes a transformer T having a primary winding W1 and a secondary winding W2. During operation, the adaptive gate driver 105 charges the gate of an n-type GaN power switching transistor M1 connected to the primary winding W1 to turn on the power switching transistor M1 during its conduction period. The primary winding W1 is also connected to an input voltage rail carrying a rectified input voltage (Vin). When the power switching transistor M1 is cycled on, primary winding current begins to flow through the primary winding W1 and the power switching transistor M1 to ground. Once the desired peak winding current has been reached, a primary-side controller (not shown) can control the gate driver 105 to cycle off the power switching transistor M1. As used herein, “connection” refers to a direct electrical connection, such as a connection via a conductive wire, while “coupling” refers to an electrical connection where the connection may be via an intermediate element such as a resistor or diode.

[0015] The secondary-side controller U2 controls the synchronous rectifier (SR) switching transistor coupled between the return output terminal and the secondary winding W2. This SR control is in response to monitoring of the drain (D) to source (S) voltage (VDS) across the SR switching transistor. Based on the drain-to-source voltage VDS, the secondary-side controller 110 detects whether the power switching transistor M1 has been cycle-off, thereby enabling the SR switching transistor to turn on, allowing secondary winding current to flow and charging the output voltage Vout supported by the output capacitor C1.

[0016] Figure 2 Example gate driver 200 is shown in more detail. For ease of explanation and brevity, the corresponding flyback converter is represented only by node 201 of the gate voltage Vgs. Modulation control circuitry 220 provides modulation control signals to gate drive control circuitry 205. For example, modulation control circuitry 220 may be pulse width modulation (PWM) control circuitry that generates PWM control signals to control the desired on-time of the power switching transistor. Modulation control circuitry 210 may be part of a primary-side controller or a secondary-side controller. If modulation control circuitry 210 is located on the secondary side of a transformer, the PWM control signals will be transmitted through a ground isolation channel such as an opto-isolator. Regardless of its location, modulation control circuitry 210 generates PWM control signals in response to feedback from various operating signals such as output voltage Vout or input voltage Vin.

[0017] The adaptive gate driver 200 includes a gate drive circuit 215 that implements a variable gate drive resistance and a gate voltage monitor or sensing circuit 202 that monitors the gate voltage (which, since the source of the power switching transistor is grounded, is equivalent to the gate-to-source voltage Vgs of the power switching transistor). The gate voltage sensing circuit 202 includes comparators 225, 230, and 235 for comparing the gate voltage of the power switching transistor with respective threshold voltages. Specifically, comparator 230 uses a relatively low threshold voltage Vth_lo to assert the comparator output signal flag_Vth_lo when the gate voltage has risen to equal Vth_lo. During switch-off, the comparator output signal flag_Vth_low is de-asserted to indicate that the gate voltage has fallen below Vth_lo. Similarly, comparator 225 uses a relatively large reference voltage Vth_hi to assert the comparator output signal flag_Vth_hi when the gate voltage has risen to equal the high threshold voltage Vth_hi during the switch-on period. During the switch-off period, the comparator output signal flag_Vth_hi is deasserted to indicate that the gate voltage has fallen below Vth_hi. Therefore, there are three periods during the power switch transistor's on-time and during the power switch-off period. The first period T1 extends from the start of the on-time delay until the gate voltage has risen to equal Vth_lo. The second period T2 extends from the end of period T1 until the gate voltage has risen to equal Vth_hi (Vth_hi is greater than Vth_lo). The final on-time T3 extends from when the gate voltage has risen above Vth_hi until the end of the on-time.

[0018] The turn-off period following the turn-on period is similar, comprising period T4 extending from the end of the turn-on period to the point where the gate voltage drops below Vth_hi. At the end of period T4, period T5 extends from the end of period T4 to the end of the timing delay. Finally, period T6 extends from the end of period T5 to the point where the gate voltage discharges to ground.

[0019] During the switching-on period, the gate drive circuit 215 drives the gate voltage using a pull-up gate drive resistor, the variation of which of periods T1, T2, and T3 is active. Similarly, the gate drive circuit discharges the gate voltage using a pull-down gate drive resistor, the variation of which of periods T4, T5, and T6 is active. During periods T1 and T2 of the switching-on period, the gate drive circuit 215 charges the gate through a high pull-up resistor. However, during period T3, the gate drive circuit 215 charges the gate through a relatively low pull-up resistor, which is less than the relatively high pull-up resistor used during period T1. During period T4, the gate drive circuit 215 discharges the gate voltage through a relatively low pull-down resistor to reduce turn-off delay. Then, during period T5, the pull-down resistor is switched to a relatively high pull-down resistor. Finally, during period T6, the gate drive circuit 215 discharges the gate voltage again through a relatively low pull-down resistor. However, it should be noted that increasing the gate drive resistance may be undesirable during critical on-mode operation where a relatively large amount of power must be supplied to the load. Therefore, the pull-up gate drive resistance during periods T1 and T2 and the pull-down gate drive resistance during period T5 can be the same as or even lower than the values ​​used in discontinuous on-mode operation.

[0020] To implement various pull-up resistors, the gate drive circuit 215 includes a plurality of (n) PMOS pull-up transistors, ranging from the first PMOS pull-up transistor P1 to the nth PMOS pull-up transistor Pn, where n is a positive complex integer. The source of each pull-up transistor is coupled via a corresponding resistor to a power supply voltage rail, such as that supplied by the voltage clamp 240 through a corresponding resistor, and its drain is connected to the gate of the power switching transistor M1. For example, the source of transistor P1 is coupled to the voltage clamp 240 via resistor R1, and its drain is connected to the gate of the power switching transistor M1; the source of transistor P2 is coupled to the voltage clamp 240 via resistor R2, and its drain is connected to the gate of the power switching transistor M1; and so on, such that the source of the nth transistor Pn is coupled to the voltage clamp 240 via resistor Rn, and its drain is connected to the gate of the power switching transistor M1. In some embodiments, the resistors may be conceptual, as they will be provided by the on-resistance of the respective transistor. Alternatively, the resistors may be external to the transistors. In an alternative embodiment, the resistor may also be coupled between the drain of the respective transistor and the gate of the power switching transistor M1.

[0021] To generate low pull-up resistance, drive control circuit 305 can turn on each (or most) of the pull-up transistors P1 to Pn. As fewer transistors P1 to Pn are turned on, the gate drive pull-up resistance increases. To control the gate drive pull-up resistance based on whether periods T1, T2, or T3 are active, gate drive control circuit 205 may include logic circuit 245. Logic circuit 245 may include a state machine, microcontroller, or microprocessor. During the cycle of power switching transistor M1, logic circuit 245 responds to a PWM control signal and then turns on power switching transistor M1 for the desired on-time. For larger pulse widths, the on-time is relatively long, while for smaller pulse widths, the on-time is shorter. The start of the on-time can be coordinated by a clock signal from clock 250. Logic circuit 245 controls which of the pull-up transistors P1 to Pn is turned on via the corresponding gate drive signal. For example, logic circuit 245 grounds the gate drive signal g1_up to turn on pull-up transistor P1, grounds the gate drive signal g2_up to turn on pull-up transistor P2, and so on, such that logic circuit 245 grounds the gate drive signal gn_up to turn on pull-up transistor Pn. If one of the gate drive signals g1_up to gn_up is charged to the power supply voltage, the corresponding pull-up transistor is turned off. In an alternative embodiment, a current source can be used to control the gate drive resistance level during the conduction period of power switching transistor M1.

[0022] The pull-down resistor is implemented similarly, such as using multiple NMOS pull-down transistors, each with a source coupled to ground and a drain coupled to the gate of the power switching transistor M1. In the gate drive circuit 215, there are two pull-down transistors, ranging from the first pull-down transistor N1 to the second pull-down transistor N2; however, it is understood that in alternative embodiments, more than two pull-down transistors may be used. In the gate driver 200, the on-resistance of pull-down transistors N1 and N2 controls the gate drive pull-down resistance; however, it is understood that the pull-down transistors may be arranged in series with corresponding resistors, as shown with pull-up transistors. To generate a low gate drive pull-down resistance, the drive control circuit 205 can turn on each of the pull-down transistors N1 and N2. If only one of transistors N1 and N2 is turned on, the gate drive pull-down resistance increases. To control whether pull-down transistor M1 is turned on, the logic circuit 245 asserts the gate drive signal g1_dn to the supply voltage. Conversely, logic circuit 245 grounds the gate drive signal g1_dn to turn off the pull-down transistor M1. Similarly, logic circuit 245 asserts the gate drive signal g2_dn to the power supply voltage to turn on the pull-down transistor M2. Conversely, logic circuit 245 grounds the gate drive signal g2_dn to turn off the pull-down transistor M2.

[0023] During period T4, logic circuit 245 turns on both pull-down transistors M1 and M2 to generate the desired low pull-down impedance. In period T5, logic circuit 245 turns on only one of the pull-down transistors M1 and M2 to increase the pull-down impedance. Finally, in period T6, logic circuit 245 turns on both pull-down transistors again to generate the desired low pull-down impedance, thus ending the off period of power switching transistor M1.

[0024] Regarding the timing of periods T1 to T6, the threshold voltage used by the gate voltage monitor 240 is a fixed value. Since the nature of the Miller plateau voltage in GaN devices is undefined, the mismatch between the threshold voltage of the power switching transistor M1 and the Miller plateau gate voltage is highly advantageous. Setting a low threshold voltage Vth_lo ensures that the threshold voltage of the power switching transistor M1 has been reached once the comparator 230 asserts the flag_Vth_lo signal to signal the logic circuit 245 that the gate voltage has risen above the low threshold voltage Vth_lo. Therefore, the duration of period T1 from the start of the conduction period to the assertion of flag_Vth_lo constitutes the dominant on-delay of the power switching transistor M1. During periods T1 and T2, the gate drive circuit 215 implements a relatively high pull-up gate impedance, denoted here as Rg1. Regarding the setting of Rg1, the logic unit 245 can time the duration of period T1 to determine whether the dominant on-delay meets design requirements. If period T1 is too short, the corresponding rate of change of the drain voltage of the power switching transistor M1 may generate excessive EMI noise. Conversely, if the period T1 is too long, the switching speed of the power switching transistor M1 may be too slow to adequately regulate the output voltage of the corresponding switching power converter, resulting in high switching losses.

[0025] By considering Figure 3The example timing diagram shown provides a better understanding of period T1 (and the remaining periods T2 through T6). A PWM control signal is asserted to signal logic circuit 245, thereby controlling gate drive circuit 215 to begin charging the gate voltage through pull-up impedance Rg1 to initiate period T1, during which the gate voltage (Vgate) rises rapidly. Period T1 continues until the gate voltage rises to the low threshold voltage Vth_lo, at which point comparator 230 asserts the flag_Vth_lo signal to signal the start of period T2. Since the power switching transistor M1 has already met its threshold voltage at this point, the Miller plateau of the power switching transistor M1 begins during period T2. However, the Miller plateau of a GaN device is not defined, so the gate voltage continues to rise during period T2, but at a lower rate than during period T1. When the gate voltage rises above the high threshold voltage Vth_hi, period T2 ends, at which point comparator 225 asserts the flag_Vth_hi signal to begin period T3.

[0026] In response to the assertion of the flag_Vth_hi signal, logic circuit 245 controls gate drive circuit 215 to implement a lower gate drive pull-down resistor, denoted here as Rg2 (Rg1 is greater than Rg2), during period T3. Period T3 begins when the flag_Vth_hi signal is asserted and continues until the turn-on period of power switching transistor M1 ends. In some implementations, the gate resistor Rg2 is maintained until the end of period T3. However, gate leakage in GaN devices such as the enhancement mode of power switching transistor M1 is a significant problem. To detect excessive gate leakage current in power switching transistor M1, logic circuit 245 begins timing a leakage delay period in response to the assertion of the flag_Vth_hi signal. The range of the leakage delay period is such that the gate voltage is asserted as the supply voltage before the leakage delay period has ended (power switching transistor M1 is fully turned on).

[0027] During period T1 and at the beginning of period T2, the drain-to-source voltage Vds across the power switching transistor drops sharply, then begins to drop more slowly until the power switching transistor M1 is fully turned on and grounded. At the end of the leakage delay period, logic circuit 245 begins timing the leakage detection period and controls gate drive circuit 215 to increase the gate pull-up impedance from Rg2 to Rg3, where Rg3 is greater than Rg2. If excessive gate leakage exists, the increased gate pull-up impedance, combined with the leakage current, will cause the gate voltage to drop below the gate leakage threshold voltage Vth_leak during the leakage detection period. See again... Figure 2Comparator 235 asserts the flag_Vth_leak signal in response to a gate voltage exceeding the gate leakage threshold voltage Vth_leak. Before the end of the leakage delay period (while the gate pull-up impedance remains equal to Rg2), the gate voltage rises above the gate leakage threshold voltage to trigger the flag_Vth_leak signal assertion. However, at the end of the leakage delay period, the gate pull-up impedance increases to Rg3 during the leakage detection period, which, combined with excessive gate leakage, causes the gate voltage to drop below the gate leakage threshold voltage Vth_leak, thus canceling the flag_Vth_leak signal assertion. As used herein, when a binary signal is logically true, it is considered asserted regardless of whether the true state is represented by a high-active or low-active routine. Conversely, when a binary signal is logically false, it is considered canceled in this document, regardless of whether the false state is represented by a high-active or low-active routine.

[0028] Logic circuit 245 detects a leakage fault 220 as a cancellation assertion of the flag_Vth_leak signal during the leakage detection period. If a leakage fault 220 is detected within a consecutive cycle of the power switching transistor M1, logic circuit 245 can block subsequent cycles to protect the power switching transistor M1 from damage caused by excessive leakage current. For example, the gate leakage threshold voltage Vth_leak can be set such that a leakage fault 220 is considered detected if the leakage is within the milliampere range. At the end of the leakage detection period, logic circuit 245 controls gate drive circuit 215 to reduce the gate pull-up impedance to a value Rg4 less than Rg3. In some embodiments, Rg4 and Rg2 are equal. Alternatively, Rg4 may be less than Rg2.

[0029] In response to the cancellation assertion of the PWM control signal to end the on-time of the power switching transistor M1 and begin the off-time, logic circuit 245 initiates the off-time of the power switching transistor starting from period T4. During period T4, gate drive circuit 215 discharges the gate voltage through a relatively low gate drive pull-down resistor (denoted as Rgdn1). Due to this relatively low pull-down resistor, the gate voltage drops rapidly and thus falls below the high threshold voltage Vth_hi, causing comparator 225 to cancel the assertion of the flag_Vth_hi signal. Logic circuit 245 responds to this cancellation assertion by commanding gate drive circuit 215 to discharge the gate voltage through the gate drive pull-down resistor, denoted as Rgdn2, which is greater than Rgdn1, to begin period T5. Furthermore, logic circuit 245 begins a timing pull-down delay in response to the cancellation assertion of the flag_Vth_hi signal. During the pull-down delay period T5, and in period T6, logic circuit 245 again commands gate drive circuit 215 to discharge the gate voltage through pull-down resistor Rgdn1 to discharge the gate voltage quickly until the gate voltage is grounded, thereby completing the turn-off period.

[0030] Those skilled in the art will now understand that many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments shown and described herein, as they are merely examples, but rather should be fully consistent with the scope of the appended claims and their functional equivalents.

Claims

1. An integrated circuit for a switching power converter, the integrated circuit comprising: a gate drive circuit configured to charge a gate of a GaN power switching transistor through a variable pull-up resistance comprising a first pull-up resistance and a second pull-up resistance, and to discharge the gate of the GaN power switching transistor through a variable pull-down resistance comprising a first pull-down resistance and a second pull-down resistance, wherein the first pull-up resistance is greater than the second pull-up resistance, and wherein the second pull-down resistance is greater than the first pull-down resistance; and a gate drive control circuit configured to command the gate drive circuit to charge the gate through the first pull-up resistance during an initial first portion of an on period of the GaN power switching transistor, and to charge the gate through the second pull-up resistance during a second portion of the on period, wherein the gate drive control circuit is further configured to command the gate drive circuit to discharge the gate through the first pull-down resistance during an initial first portion of an off period of the GaN power switching transistor, and to discharge the gate through the second pull-down resistance during a second portion of the off period. The integrated circuit further comprises:

2. The integrated circuit of claim 1, wherein, a gate voltage monitor configured to monitor a gate voltage of the GaN power switching transistor, wherein the gate drive control circuit is further configured to time a main turn-on delay of the GaN power switching transistor in response to a comparison of the gate voltage to a first threshold voltage by the gate voltage monitor. The gate voltage monitor comprises:

3. The integrated circuit of claim 2, wherein, a first comparator configured to compare the gate voltage to the first threshold voltage, and wherein the gate drive control circuit is further configured to start timing of the main turn-on delay in response to an assertion of a pulse width modulation signal, and to stop timing of the main turn-on delay in response to an assertion of an output signal of the first comparator. The gate voltage monitor further comprises:

4. The integrated circuit of claim 3, wherein, a second comparator configured to compare the gate voltage to a second threshold voltage greater than the first threshold voltage, wherein the gate drive control circuit is further configured to command the gate drive circuit to charge the gate through the second pull-up resistance in response to an assertion of an output signal of the second comparator. The gate voltage monitor further comprises:

5. The integrated circuit of claim 4, wherein, a third comparator configured to compare the gate voltage to a leakage threshold voltage greater than the second threshold voltage, wherein the gate drive control circuit is further configured to start timing of a leakage delay period in response to an assertion of an output signal of the second comparator, and to command the gate drive circuit to charge the gate through a third pull-up resistance in response to an expiration of the leakage delay period, and to detect a leakage fault in response to a de-assertion of an output signal of the third comparator while the gate drive circuit charges the gate through the third pull-up resistance. ​ 6. The integrated circuit of claim 5, wherein, The gate drive control circuit is further configured to start timing of a leakage detection period upon termination of the leakage delay period, and to command the gate drive circuit to charge the gate through the second pull-up resistor upon termination of the leakage detection period.

7. The integrated circuit of claim 4, wherein, The gate drive control circuit is further configured to command the gate drive circuit to discharge the gate voltage through a second pull-down resistor in response to a de-assertion of the output signal of the second comparator.

8. The integrated circuit of claim 7, wherein, The gate drive control circuit is further configured to start timing of a pull-down delay period in response to a de-assertion of the output signal of the second comparator, and to command the gate drive circuit to discharge the gate through the first pull-down resistor in response to termination of the pull-down delay period.

9. The integrated circuit of claim 1, wherein, The gate drive circuit includes a plurality of first transistors coupled between the gate of the GaN power switch transistor and a power supply node, and wherein the gate drive control circuit includes a logic circuit configured to command a first number of the plurality of first transistors to turn on during an initial first portion of the on period, and to command a second number of the plurality of first transistors to turn on during a second portion of the on period, wherein the first number of the plurality of first transistors is less than the second number of the plurality of first transistors.

10. The integrated circuit of claim 9, wherein, The gate drive circuit further includes a plurality of second transistors coupled between the gate of the GaN power switch transistor and ground, and wherein the logic circuit is further configured to command a first number of the plurality of second transistors to turn on during an initial first portion of the off period, and to command a second number of the plurality of second transistors to turn on during a second portion of the off period, wherein the first number of the plurality of second transistors is greater than the second number of the plurality of second transistors.

11. The integrated circuit of claim 10, wherein, The plurality of first transistors includes a plurality of PMOS transistors, and wherein the plurality of second transistors includes a plurality of NMOS transistors.

12. The integrated circuit of claim 10, wherein, Each of the plurality of first transistors is coupled to the power supply node through a respective resistor.

13. A method of driving a gate of a GaN power switch transistor in a switching power converter, the method comprising: charging the gate through a first pull-up resistor during an initial portion of an on period of the GaN power switch transistor and while a gate voltage of the GaN power switch transistor is less than a first threshold voltage; charging the gate through a second pull-up resistor that is less than the first pull-up resistor during a second portion of the on period and while the gate voltage is greater than the first threshold voltage; discharging the gate through a first pull-down resistor during an initial portion of an off period of the GaN power switch transistor and while the gate voltage is greater than a first threshold voltage; and during a second portion of the off period, discharging the gate through a second pull-down resistor in response to the gate voltage falling below the first threshold voltage, wherein the second pull-down resistor is greater than the first pull-down resistor.

14. The method of claim 13, wherein, The method further includes: during the off period, starting a count of a pull-down delay period in response to the gate voltage falling below the first threshold voltage; and in response to expiration of the pull-down delay period, switching from discharging the gate through the second pull-down resistor to discharging the gate through the first pull-down resistor.

15. The method of claim 13, wherein, The method further includes: in response to the start of the on period, starting a count of a main on delay period; and in response to the gate voltage rising above a second threshold voltage, stopping the count of the main on delay period, the second threshold voltage being less than the first threshold voltage.

16. The method of claim 14, wherein, The method further includes: during the on period, starting a count of a leakage delay period in response to the gate voltage rising above the first threshold voltage; in response to expiration of the leakage delay period, switching from charging the gate through the second pull-up resistor to charging the gate through a third pull-up resistor to start a leakage detection period; and during the leakage detection period, detecting a leakage fault in response to the gate voltage falling below a third threshold voltage.

17. The method of claim 16, wherein, The method further includes stopping cycling of the GaN power switch transistor in response to repeated detection of the leakage fault.

18. A switching power converter, the switching power converter comprising: an inductor; a GaN power switch transistor connected to the inductor; and an integrated circuit configured to charge a gate of the GaN power switch transistor through a first pull-up resistor during an initial first portion of an on period of the GaN power switch transistor, charge the gate through a second pull-up resistor during a second portion of the on period, discharge the gate through a first pull-down resistor during an initial first portion of an off period of the GaN power switch transistor, and discharge the gate through a second pull-down resistor during a second portion of the off period.

19. The switching power converter of claim 18, wherein, the first pull-up resistor is greater than the second pull-up resistor, and wherein the second pull-down resistor is greater than the first pull-down resistor.

20. The switching power converter of claim 18, wherein, the inductor is a primary winding of a transformer.

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