Software and hardware combined LLC synchronous rectification driving optimization circuit

Abstract

The invention discloses a software and hardware combined LLC synchronous rectification driving optimization circuit which comprises an LLC resonance network, a transformer T, a synchronous rectification circuit and a control module MCU which are connected in sequence. The first synchronous rectifier tube control circuit and the second synchronous rectifier tube control circuit respectively comprise a synchronous rectifier tube driving circuit and a synchronous rectifier tube voltage stress detection circuit. The turn-off of the synchronous rectifier tube is controlled by the control module MCU, and when the synchronous rectifier tube voltage stress detection circuit of the branch detects that the drain voltage of the synchronous rectifier tube of the other branch reaches a preset value, the synchronous rectifier tube of the branch is conducted, so that the dead time of t4-t5 is controlled, the dead time of t4-t5 is reduced to the maximum extent under the condition that safety is guaranteed, and the safety is improved. The switch-on time of the synchronous rectification MOS tube is increased, the efficiency of the converter is improved, the synchronous rectification MOS tube is ensured not to be directly connected, and the reliability of a power supply is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a hardware and software combined to implement an optimized LLC synchronous rectification drive circuit. Background Technology

[0002] The LLC resonant topology is one of the most widely used topologies in DC-DC conversion of switching power supplies due to its ease of soft switching and high conversion efficiency. It is applied in fields such as communication power supplies, server power supplies, and charging pile modules. Figure 1 As shown, the LLC resonant topology combined with synchronous rectification is typically the preferred choice for applications requiring high power, high output current, or high efficiency. However, regardless of whether analog chip control or digital control is used, when the LLC resonant topology is paired with synchronous rectification, in order to improve efficiency, the LLC switching MOSFETs must minimize dead time while ensuring soft switching, and simultaneously maximize the pulse width of the synchronous rectification to ensure the MOSFET's turn-on time is as long as possible. However, under certain input and output conditions, this can lead to a common phenomenon between the upper and lower synchronous rectification MOSFETs. That is, while one synchronous rectification MOSFET is not completely turned off, another MOSFET is turned on, causing excessive voltage stress on the synchronous rectification MOSFETs and potentially resulting in power supply failure.

[0003] like Figure 2 As shown, V at time t0-t1 GS_Q1 High level, upper transistor Q1 is turned on, V GS_RS2 When the voltage level is high, the synchronous rectifier MOSFET RS2 is turned on, and the output current flows through the secondary winding N. S2 Load R O And the synchronous rectifier MOSFET RS2 is in operation. At time t1, V... GS_RS2 When the voltage drops to low, the synchronous rectifier MOSFET RS2 turns off. During the time interval t1-t2, the load current flows through the body diode D of RS2. RS2 Circulation, until time t2 V GS_Q1 When the voltage level is low, the upper transistor Q1 is turned off, and the LLC switch enters the dead time. At this time, the resonant cavity current i p Decrease, excitation current i LM As the current continues to increase, the direction of the load current remains unchanged. At time t3, V... GS_Q2 With the high level, the lower transistor Q2 is turned on, the resonant cavity current continues to decrease, the excitation current continues to increase, and the load current direction remains unchanged, still flowing from the body diode D of RS2. RS2 Circulation. At time t4, the excitation current equals the resonant cavity current. The resonant cavity current continues to decrease, and the excitation current begins to decrease. The transformer primary winding N... P When the voltage reverses, the secondary winding voltage also reverses, and the body diode D of RS2... RS2Reverse cutoff begins, at which point the voltage stress on RS2 increases until complete cutoff. When the secondary winding N... S1 After the voltage is reversed, the load current will flow through winding N. S1 Load R O RS1 body diode D RS1 Circulation. At time t5, V GS_RS1 When the voltage level changes from low to high, the first synchronous rectifier diode RS1 turns on, and the load current flows through the MOSFET, reducing losses. From the above analysis of the LLC synchronous rectification process, it can be seen that to improve the efficiency of the LLC converter, the dead time of the synchronous rectifier diode needs to be shortened, allowing the load current to flow through the MOSFET as much as possible, rather than through the body diode.

[0004] To solve the problem in the secondary winding N S1 After reversal, the load current is switched to the body diode D of RS1. RS1 In digital control, a common approach to quickly activate RS1 during operation is to extend the activation time of RS1 after Q2 is activated, i.e., control the t3-t5 time period. However, in practical applications, the t3-t4 time period will vary depending on the input voltage, output voltage, and load. For example, when the input voltage increases, V... GS_RS1 The time t4, when the excitation current and the resonant cavity current are equal, will be delayed. Since the dead time t3-t5 is fixed in digital control, the delay of t4 causes t4 to coincide with t5, and the current is still flowing through the body diode D of RS2. RS2 When RS1 is turned on during circulation, it causes a straight-through in the synchronous rectifier RS ​​tube, increasing the stress on RS1 and posing a risk of damage. The waveform is as follows. Figure 3 As shown. Therefore, in order to ensure the safety of the t4-t5 time interval, the dead time of t3-t5 must be set to be very long, or a lot of compensation must be made through judgment conditions, which makes software control more complicated, reduces reliability, and worsens efficiency. Summary of the Invention

[0005] Therefore, it is necessary to provide a hardware and software combination to achieve an optimized LLC synchronous rectification drive circuit that can improve efficiency while ensuring that the synchronous rectification MOSFET does not shoot through and has high power supply reliability.

[0006] A hardware and software integrated optimization circuit for driving an LLC synchronous rectifier is disclosed for controlling the dead time of the synchronous rectifier circuit. The circuit comprises an LLC resonant network, a transformer T, a synchronous rectifier circuit, and a control module MCU connected in sequence. The input terminal of the LLC resonant network is connected to the input power supply U. inThe output of the LLC resonant network is connected to the input of the synchronous rectifier circuit through the transformer T. The output of the synchronous rectifier circuit is connected to the load R0 through a low-pass filter circuit. The voltage of the load R0 is U0. The synchronous rectification circuit includes a first synchronous rectifier diode RS1, a first synchronous rectifier diode control circuit, a second synchronous rectifier diode RS2, and a second synchronous rectifier diode control circuit. The control module MCU has a first control signal and a second control signal. The first synchronous rectifier diode control circuit and the first control signal are used to control the on and off of the first synchronous rectifier diode RS1, and the second synchronous rectifier diode control circuit and the second control signal are used to control the on and off of the second synchronous rectifier diode RS2. By controlling the dead time of the synchronous rectification circuit, the on-time of the first synchronous rectifier diode RS1 and the second synchronous rectifier diode RS2 is increased, thereby improving the conversion efficiency of the synchronous rectification circuit.

[0007] Preferably, the LLC resonant network includes a switching circuit and an LLC resonant circuit, the switching circuit including a circuit serially connected to the input power supply U. in The first switch Q1 and the second switch Q2, with the drain of the first switch Q1 connected to the input power supply U. in The positive terminal of the first switching transistor Q1 is connected to the source of the second switching transistor Q2, and the source of the second switching transistor Q2 is connected to the input power supply U. in The negative electrode; The LLC resonant circuit includes a resonant capacitor Cr, a resonant inductor Lr, and a magnetizing inductor Lm connected in series. The LLC resonant circuit is located at the connection point A between the first switch Q1 and the second switch Q2 and the input power supply U. in Between the negative and positive electrodes.

[0008] Preferably, the transformer T includes a primary side Np, a first secondary side Ns1, and a second secondary side Ns2. The primary side Np is connected in parallel across the two ends of the magnetizing inductance Lm of the LLC resonant circuit. The same-named terminal of the first secondary side Ns1 is connected to the drain of the first synchronous rectifier RS1, and the non-same-named terminal of the second secondary side Ns2 is connected to the drain of the second synchronous rectifier RS2.

[0009] Preferably, the low-pass filter circuit includes a filter capacitor C0, which is connected in parallel with the load R0; One end of the filter capacitor C0 is connected to the midpoint between the first secondary side Ns1 and the second secondary side Ns2, and the other end of the filter capacitor C0 is connected to the source of the first synchronous rectifier RS1 and the source of the second synchronous rectifier RS2.

[0010] Preferably, the synchronous rectification circuit further includes a reference voltage circuit, which is used to output a reference voltage Vref; The first control signal is used to control the on / off state of the first synchronous rectifier diode RS1; the second control signal is used to control the on / off state of the second synchronous rectifier diode RS2.

[0011] Preferably, both the first synchronous rectifier control circuit and the second synchronous rectifier control circuit include a synchronous rectifier drive circuit and a synchronous rectifier voltage stress detection circuit, wherein, The synchronous rectifier tube voltage stress detection circuit is used to detect the stress rise voltage of the synchronous rectifier tube in the rectifier branch on the opposite side, and compare it with the reference voltage Vref. The comparison result is ANDed with the first control signal or the second control signal, and the result of the AND operation is output to the synchronous rectifier tube drive circuit. The synchronous rectifier drive circuit is used to drive the synchronous rectifier of the rectifier branch on this side to turn on or off based on the result of the AND operation between the synchronous rectifier voltage stress detection circuit and the first control signal or the second control signal.

[0012] Preferably, the first synchronous rectifier control circuit includes a first synchronous rectifier drive circuit and a first synchronous rectifier voltage stress detection circuit. The first synchronous rectifier voltage stress detection circuit and the first synchronous rectifier drive circuit are connected through a first AND gate. The input terminal of the first AND gate is connected to the output terminal of the first synchronous rectifier voltage stress detection circuit and the output terminal of the first control signal. The output terminal of the first AND gate is connected to the first synchronous rectifier drive circuit.

[0013] Preferably, the first synchronous rectifier voltage stress detection circuit includes a second comparator, a first resistor R1, a second resistor R2, and a first capacitor C1. The first resistor R1 and the second resistor R2 are connected in series between the connection point between the non-same-name terminal of the second secondary side Ns2 and the drain of the second synchronous rectifier RS2 and the working ground. The positive input terminal of the second comparator is connected to the midpoint between the first resistor R1 and the second resistor R2. The first capacitor C1 is connected in parallel across the second resistor R2. The inverting input terminal of the second comparator is connected to the reference voltage Vref. The output terminal of the second comparator is connected to the input terminal of the first AND gate.

[0014] Preferably, the second synchronous rectifier control circuit includes a second synchronous rectifier driving circuit and a second synchronous rectifier voltage stress detection circuit. The second synchronous rectifier voltage stress detection circuit and the second synchronous rectifier driving circuit are connected through a second AND gate. The input terminal of the second AND gate is connected to the output terminal of the second synchronous rectifier voltage stress detection circuit and the output terminal of the second control signal. The output terminal of the second AND gate is connected to the second synchronous rectifier driving circuit.

[0015] Preferably, the second synchronous rectifier voltage stress detection circuit includes a first comparator, a third resistor R3, a fourth resistor R4, and a second capacitor C2. The third resistor R3 and the fourth resistor R4 are connected in series between the connection point between the corresponding terminal of the first secondary side Ns1 and the drain of the first synchronous rectifier RS1 and the working ground. The positive input terminal of the first comparator is connected to the midpoint between the third resistor R3 and the fourth resistor R4. The second capacitor C2 is connected in parallel across the fourth resistor R4. The inverting input terminal of the first comparator is connected to the reference voltage Vref. The output terminal of the first comparator is connected to the input terminal of the second AND gate.

[0016] In the aforementioned hardware and software combined to implement the LLC synchronous rectification drive optimization circuit, the synchronous rectification circuit includes a first synchronous rectifier control circuit comprising a first synchronous rectifier drive circuit and a first synchronous rectifier voltage stress detection circuit, and a second synchronous rectifier control circuit comprising a second synchronous rectifier drive circuit and a second synchronous rectifier voltage stress detection circuit. The first control signal controls the first synchronous rectifier RS1 to turn off. When the first synchronous rectifier voltage stress detection circuit detects that the drain voltage of the second synchronous rectifier RS2 reaches a predetermined value, the first synchronous rectifier drive circuit drives the first synchronous rectifier RS1 to turn on. Similarly, the second control signal controls the second synchronous rectifier RS2 to turn off. When the second synchronous rectifier voltage stress detection circuit detects that the drain voltage of the first synchronous rectifier RS1 reaches a predetermined value, the second synchronous rectifier drive circuit drives the second synchronous rectifier RS2 to turn on. This controls the dead time of t4-t5, minimizing it while ensuring safety, increasing the turn-on time of the synchronous rectifier MOSFET, improving converter efficiency, ensuring the synchronous rectifier MOSFET does not shoot-through, and guaranteeing power supply reliability. The circuit structure of this invention is easy to implement, low in cost, and readily applicable. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of an LLC resonant converter circuit in the prior art.

[0018] Figure 2 This is a schematic diagram of the dead time waveform of the LLC switch MOS in an existing LLC resonant converter circuit.

[0019] Figure 3 This is a waveform diagram of the synchronous rectifier diode RS when the input voltage of the LLC resonant converter circuit in the prior art increases (the voltage stress of the synchronous rectifier diode RS is high when it is in direct pass).

[0020] Figure 4 This is a schematic diagram of the synchronous rectification circuit of the LLC synchronous rectification drive optimization circuit implemented by combining software and hardware in an embodiment of the present invention.

[0021] Figure 5 This is the conduction waveform diagram of the first synchronous rectifier tube RS1 in the synchronous rectifier circuit of the LLC synchronous rectifier drive optimization circuit implemented by the combination of software and hardware in an embodiment of the present invention. Detailed Implementation

[0022] This embodiment takes the implementation of an LLC synchronous rectification drive optimization circuit through a combination of hardware and software as an example. The invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0023] Please see Figure 4 and Figure 5 This illustration shows a hardware and software combined implementation of an LLC synchronous rectification drive optimization circuit according to an embodiment of the present invention, used to control the dead time of the synchronous rectification circuit. It includes an LLC resonant network, a transformer T, a synchronous rectification circuit, and a control module MCU connected in sequence. The input terminal of the LLC resonant network is connected to the input power supply U. in The output of the LLC resonant network is connected to the input of the synchronous rectifier circuit through the transformer T. The output of the synchronous rectifier circuit is connected to the load R0 through a low-pass filter circuit. The voltage of the load R0 is U0. The synchronous rectification circuit includes a first synchronous rectifier diode RS1, a first synchronous rectifier diode control circuit, a second synchronous rectifier diode RS2, and a second synchronous rectifier diode control circuit. The control module MCU has a first control signal and a second control signal. The first synchronous rectifier diode control circuit and the first control signal are used to control the on and off of the first synchronous rectifier diode RS1, and the second synchronous rectifier diode control circuit and the second control signal are used to control the on and off of the second synchronous rectifier diode RS2. By controlling the dead time of the synchronous rectification circuit, the on-time of the first synchronous rectifier diode RS1 and the second synchronous rectifier diode RS2 is increased, thereby improving the conversion efficiency of the synchronous rectification circuit.

[0024] Preferably, the LLC resonant network includes a switching circuit and an LLC resonant circuit, the switching circuit including a circuit serially connected to the input power supply U.in The first switch Q1 and the second switch Q2, with the drain of the first switch Q1 connected to the input power supply U. in The positive terminal of the first switching transistor Q1 is connected to the source of the second switching transistor Q2, and the source of the second switching transistor Q2 is connected to the input power supply U. in The negative electrode; The LLC resonant circuit includes a resonant capacitor Cr, a resonant inductor Lr, and a magnetizing inductor Lm connected in series. The LLC resonant circuit is located at the connection point A between the first switch Q1 and the second switch Q2 and the input power supply U. in Between the negative and positive electrodes.

[0025] Preferably, the transformer T includes a primary side Np, a first secondary side Ns1, and a second secondary side Ns2. The primary side Np is connected in parallel across the two ends of the magnetizing inductance Lm of the LLC resonant circuit. The same-named terminal of the first secondary side Ns1 is connected to the drain of the first synchronous rectifier RS1, and the non-same-named terminal of the second secondary side Ns2 is connected to the drain of the second synchronous rectifier RS2.

[0026] Preferably, the low-pass filter circuit includes a filter capacitor C0, which is connected in parallel with the load R0; One end of the filter capacitor C0 is connected to the midpoint between the first secondary side Ns1 and the second secondary side Ns2, and the other end of the filter capacitor C0 is connected to the source of the first synchronous rectifier RS1 and the source of the second synchronous rectifier RS2.

[0027] Preferably, the synchronous rectification circuit further includes a reference voltage circuit, which is used to output a reference voltage Vref.

[0028] Specifically, in this embodiment, the value of the reference voltage Vref is determined by the power supply voltage of the comparator. Typically, the comparator is powered by 3.3V, and the voltage range of the reference voltage Vref is 0~3.3V, preferably 1V.

[0029] The first control signal is used to control the on / off state of the first synchronous rectifier diode RS1; the second control signal is used to control the on / off state of the second synchronous rectifier diode RS2.

[0030] Preferably, both the first synchronous rectifier control circuit and the second synchronous rectifier control circuit include a synchronous rectifier drive circuit and a synchronous rectifier voltage stress detection circuit, wherein, The synchronous rectifier tube voltage stress detection circuit is used to detect the stress rise voltage of the synchronous rectifier tube in the rectifier branch on the opposite side, and compare it with the reference voltage Vref. The comparison result is ANDed with the first control signal or the second control signal, and the result of the AND operation is output to the synchronous rectifier tube drive circuit. The synchronous rectifier drive circuit is used to drive the synchronous rectifier of the rectifier branch on this side to turn on or off based on the result of the AND operation between the synchronous rectifier voltage stress detection circuit and the first control signal or the second control signal.

[0031] Specifically, the first control signal and the second control signal are the switching signals of the synchronous rectifier tubes of the rectifier branch on this side output by the control module MCU. The switching control signals of the first synchronous rectifier tube RS1 and the second synchronous rectifier tube RS2 are implemented by software.

[0032] When the load is relatively light, the first control signal and the second control signal output a low level, and the output result of the synchronous rectifier voltage stress detection circuit is invalid, so that the first synchronous rectifier control circuit and the second synchronous rectifier control circuit that control the first synchronous rectifier RS1 and the second synchronous rectifier RS2 to conduct do not work.

[0033] When the load is high, the first control signal and the second control signal output a high level. Based on the output result of the synchronous rectifier voltage stress detection circuit, the first synchronous rectifier RS1 or the second synchronous rectifier RS2 is turned on. However, the turn-off of the first synchronous rectifier RS1 or the second synchronous rectifier RS2 is still implemented by the first control signal and the second control signal through software, so that the turn-on of the synchronous rectifier SR closely follows the turn-off time of the other tube.

[0034] Preferably, the first synchronous rectifier control circuit includes a first synchronous rectifier drive circuit and a first synchronous rectifier voltage stress detection circuit. The first synchronous rectifier voltage stress detection circuit and the first synchronous rectifier drive circuit are connected through a first AND gate. The input terminal of the first AND gate is connected to the output terminal of the first synchronous rectifier voltage stress detection circuit and the output terminal of the first control signal. The output terminal of the first AND gate is connected to the first synchronous rectifier drive circuit.

[0035] Preferably, the first synchronous rectifier voltage stress detection circuit includes a second comparator, a first resistor R1, a second resistor R2, and a first capacitor C1. The first resistor R1 and the second resistor R2 are connected in series between the connection point between the non-same-name terminal of the second secondary side Ns2 and the drain of the second synchronous rectifier RS2 and the working ground. The positive input terminal of the second comparator is connected to the midpoint between the first resistor R1 and the second resistor R2. The first capacitor C1 is connected in parallel across the second resistor R2. The inverting input terminal of the second comparator is connected to the reference voltage Vref. The output terminal of the second comparator is connected to the input terminal of the first AND gate.

[0036] Specifically, the first resistor R1 and the second resistor R2 form a voltage divider circuit. The input terminal of the first synchronous rectifier voltage stress detection circuit is connected to the drain of the second synchronous rectifier RS2 in the synchronous rectifier circuit. The voltage Vds_RS2 of the second synchronous rectifier RS2 is connected to the second comparator after being divided by the first resistor R1 and the second resistor R2. The first capacitor C1 acts as a filter.

[0037] Specifically, the first synchronous rectifier voltage stress detection circuit is used to detect the drain voltage of the second synchronous rectifier RS2. When the drain voltage of the second synchronous rectifier RS2 is greater than a predetermined value, the first synchronous rectifier RS1 is turned on.

[0038] Specifically, the voltage divider circuit composed of the first resistor R1 and the second resistor R2 transmits the sampled value of the voltage Vds_RS2 of the second synchronous rectifier RS2 to the second comparator. By adjusting the resistance ratio of the first resistor R1 and the second resistor R2, the sampled value is adapted to the value of the reference voltage Vref.

[0039] Preferably, the second synchronous rectifier control circuit includes a second synchronous rectifier driving circuit and a second synchronous rectifier voltage stress detection circuit. The second synchronous rectifier voltage stress detection circuit and the second synchronous rectifier driving circuit are connected through a second AND gate. The input terminal of the second AND gate is connected to the output terminal of the second synchronous rectifier voltage stress detection circuit and the output terminal of the second control signal. The output terminal of the second AND gate is connected to the second synchronous rectifier driving circuit.

[0040] Preferably, the second synchronous rectifier voltage stress detection circuit includes a first comparator, a third resistor R3, a fourth resistor R4, and a second capacitor C2. The third resistor R3 and the fourth resistor R4 are connected in series between the connection point between the corresponding terminal of the first secondary side Ns1 and the drain of the first synchronous rectifier RS1 and the working ground. The positive input terminal of the first comparator is connected to the midpoint between the third resistor R3 and the fourth resistor R4. The second capacitor C2 is connected in parallel across the fourth resistor R4. The inverting input terminal of the first comparator is connected to the reference voltage Vref. The output terminal of the first comparator is connected to the input terminal of the second AND gate.

[0041] Specifically, the third resistor R3 and the fourth resistor R4 form a voltage divider circuit. The input terminal of the second synchronous rectifier voltage stress detection circuit is connected to the drain of the first synchronous rectifier RS1 in the synchronous rectifier circuit. The voltage Vds_RS1 of the first synchronous rectifier RS1 is connected to the first comparator after being divided by the third resistor R3 and the fourth resistor R4. The second capacitor C2 serves as a filter.

[0042] Specifically, the second synchronous rectifier voltage stress detection circuit is used to detect the drain voltage of the first synchronous rectifier RS1. When the drain voltage of the first synchronous rectifier RS1 is greater than a predetermined value, the second synchronous rectifier RS2 is turned on.

[0043] Specifically, the voltage divider circuit composed of the third resistor R3 and the fourth resistor R4 transmits the sampled value of the voltage Vds_RS1 of the first synchronous rectifier tube RS1 to the first comparator. By adjusting the resistance ratio of the third resistor R3 and the fourth resistor R4, the sampled value is made to match the value of the reference voltage Vref.

[0044] Specifically, in Figure 4In the synchronous rectification circuit shown, a synchronous rectifier MOSFET voltage stress detection circuit is added to the secondary full-wave rectifier circuit of the transformer T. By detecting the stress rise voltage of this synchronous rectifier MOSFET, it determines whether the load current switches to the body diode of the other synchronous rectifier MOSFET. When changes in input / output voltage and load cause time variations between t3 and t4, it ensures that the synchronous rectifier MOSFET turns on after the body diode conducts, meaning t4 precedes t5. Simultaneously, an AND gate circuit is added, introducing a digital control signal (high level under heavy load, low level under light load). The output signal of the stress detection circuit is ANDed with the digital control signal, and the output of the AND gate is sent to the synchronous rectification drive circuit to drive the MOSFET. Thus, under light load, the digital signal can turn off the synchronous rectifier MOSFET, controlling the load current to flow only through the body diode of the synchronous rectifier, ensuring reliability. This scheme can be used not only in full-wave rectifier circuits but also in full-bridge rectifier circuits.

[0045] At time t4, the excitation current equals the resonant cavity current. Then, the excitation current decreases, the secondary winding voltage reverses, and the body diode D of the second synchronous rectifier RS2... RS2 Reverse cutoff begins, V of the second synchronous rectifier tube RS2 ds_RS2 Voltage stress increases, V ds_RS2 After the voltage is divided by resistors R1 and R2, V ds_RS2_th With reference voltage V ref Comparison, when V ds_RS2 When the voltage rises to a value greater than Vref×R2 / (R1+R2), which is V ds_RS2_th Greater than V ref When the second comparator outputs a high level, its signal is ANDed with the first control signal and then enters the first synchronous rectifier drive circuit to drive the first synchronous rectifier RS1 to turn on. The waveform is as follows: Figure 5 As shown. This is achieved by using hardware to detect V. ds_RS The voltage is monitored in real time to determine whether the body diode of the synchronous rectifier MOSFET is conducting, thereby driving the MOSFET to turn on and shortening the t4-t5 time, thus improving the converter efficiency. Alternatively, the t4-t5 time can be controlled by adjusting the values ​​of the first capacitor C1 and the second capacitor C2. Similarly, the voltage V across the first synchronous rectifier RS1 can be monitored. ds_RS1 The change in voltage level controls the activation of the second synchronous rectifier diode RS2, thereby improving the converter efficiency.

[0046] Specifically, the first capacitor C1 is connected in parallel across the second resistor R2, and the second capacitor C2 is connected in parallel across the fourth resistor R4. With the reference voltage Vref and the resistance values ​​in the voltage divider circuit determined, the turn-on time of the SR synchronous rectifier can be delayed by adjusting the capacitance values ​​of the first capacitor C1 and the second capacitor C2, that is, t5 is delayed.

[0047] This invention detects the stress voltage of the synchronous rectifier tube through a synchronous rectifier tube control circuit, and combines the detection result with a gate circuit to realize the turn-on control of the synchronous rectifier tube. This is done to shorten the t4-t5 time while ensuring that the synchronous rectifier tube does not shoot through, thereby improving the converter efficiency.

[0048] In the aforementioned hardware and software combined to implement the LLC synchronous rectification drive optimization circuit, the synchronous rectification circuit includes a first synchronous rectifier control circuit comprising a first synchronous rectifier drive circuit and a first synchronous rectifier voltage stress detection circuit, and a second synchronous rectifier control circuit comprising a second synchronous rectifier drive circuit and a second synchronous rectifier voltage stress detection circuit. The first control signal controls the first synchronous rectifier RS1 to turn off. When the first synchronous rectifier voltage stress detection circuit detects that the drain voltage of the second synchronous rectifier RS2 reaches a predetermined value, the first synchronous rectifier drive circuit drives the first synchronous rectifier RS1 to turn on. Similarly, the second control signal controls the second synchronous rectifier RS2 to turn off. When the second synchronous rectifier voltage stress detection circuit detects that the drain voltage of the first synchronous rectifier RS1 reaches a predetermined value, the second synchronous rectifier drive circuit drives the second synchronous rectifier RS2 to turn on. This controls the dead time of t4-t5, minimizing it while ensuring safety, increasing the turn-on time of the synchronous rectifier MOSFET, improving converter efficiency, ensuring the synchronous rectifier MOSFET does not shoot-through, and guaranteeing power supply reliability. The circuit structure of this invention is easy to implement, low in cost, and readily applicable.

[0049] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A software and hardware combined implementation LLC synchronous rectification drive optimization circuit for controlling dead time of a synchronous rectification circuit, characterized in that, The application relates to a power supply device, which comprises an LLC resonant network, a transformer T, a synchronous rectification circuit and a control module MCU in sequence, the input end of the LLC resonant network is connected to an input power supply U in , the output end of the LLC resonant network is connected to the input end of the synchronous rectification circuit through the transformer T, the output end of the synchronous rectification circuit is connected to a load R0 through a low-pass filter circuit, and the voltage of the load R0 is U0. The synchronous rectification circuit comprises a first synchronous rectification tube RS1, a first synchronous rectification tube control circuit, a second synchronous rectification tube RS2 and a second synchronous rectification tube control circuit, the control module MCU has a first control signal and a second control signal, the first synchronous rectification tube control circuit and the first control signal are used for controlling the turn-on and turn-off of the first synchronous rectification tube RS1, the second synchronous rectification tube control circuit and the second control signal are used for controlling the turn-on and turn-off of the second synchronous rectification tube RS2; by controlling the dead time of the synchronous rectification circuit, the turn-on time of the first synchronous rectification tube RS1 and the second synchronous rectification tube RS2 is increased, so as to improve the conversion efficiency of the synchronous rectification circuit.

2. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit according to claim 1, wherein, The LLC resonance network comprises a switching circuit and an LLC resonance loop, the switching circuit comprises first and second switching tubes Q1 and Q2 connected in series to an input power supply U in , a drain electrode of the first switching tube Q1 is connected to a positive electrode of the input power supply U in , a source electrode of the first switching tube Q1 is connected to a drain electrode of the second switching tube Q2, and a source electrode of the second switching tube Q2 is connected to a negative electrode of the input power supply U in ; The LLC resonance circuit comprises a resonance capacitor Cr, a resonance inductor Lr and an excitation inductor Lm connected in series in sequence, and is arranged between the connection point A point between the first switch tube Q1 and the second switch tube Q2 and the negative electrode of the input power supply U in .

3. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 2, wherein, The transformer T comprises a primary side Np, a first secondary side Ns1 and a second secondary side Ns2, the primary side Np is connected in parallel to two ends of the excitation inductance Lm of the LLC resonant circuit, the same name end of the first secondary side Ns1 is connected to the drain of the first synchronous rectification tube RS1, and the non-same name end of the second secondary side Ns2 is connected to the drain of the second synchronous rectification tube RS2.

4. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 3, wherein, The low-pass filter circuit comprises a filter capacitor C0, and the filter capacitor C0 is connected in parallel to the load R0. One end of the filter capacitor C0 is connected to the midpoint between the first secondary side Ns1 and the second secondary side Ns2, and the other end of the filter capacitor C0 is connected to the source of the first synchronous rectification tube RS1 and the source of the second synchronous rectification tube RS2.

5. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 3, wherein, The synchronous rectification circuit further comprises a reference voltage circuit, and the reference voltage circuit is used for outputting a reference voltage Vref. The first control signal is used for controlling the turn-on and turn-off of the first synchronous rectification tube RS1. The second control signal is used for controlling the turn-on and turn-off of the second synchronous rectification tube RS2.

6. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 5, wherein, The first synchronous rectification tube control circuit and the second synchronous rectification tube control circuit each comprise a synchronous rectification tube driving circuit and a synchronous rectification tube voltage stress detection circuit, wherein, The synchronous rectification tube voltage stress detection circuit is used for detecting the stress rise voltage of the synchronous rectification tube of the opposite rectification branch, and comparing the stress rise voltage with the reference voltage Vref, and the comparison result is subjected to an AND operation with the first control signal or the second control signal, and the result after the AND operation is output to the synchronous rectification tube driving circuit; The synchronous rectification tube driving circuit is used for driving the turn-on or turn-off of the synchronous rectification tube of the local rectification branch according to the result of the AND operation of the synchronous rectification tube voltage stress detection circuit and the first control signal or the second control signal.

7. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 6, wherein, The first synchronous rectification tube control circuit comprises a first synchronous rectification tube driving circuit and a first synchronous rectification tube voltage stress detection circuit, and the first synchronous rectification tube voltage stress detection circuit and the first synchronous rectification tube driving circuit are connected through a first AND gate; the input end of the first AND gate is connected to the output end of the first synchronous rectification tube voltage stress detection circuit and the output end of the first control signal, and the output end of the first AND gate is connected to the first synchronous rectification tube driving circuit.

8. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 7, wherein, The first synchronous rectifier voltage stress detection circuit comprises a second comparator, a first resistor R1, a second resistor R2 and a first capacitor C1, the first resistor R1 and the second resistor R2 are connected in series between a connection point between a non-same end of the second secondary side Ns2 and a drain of the second synchronous rectifier RS2 and a working ground, a positive input end of the second comparator is connected to a midpoint between the first resistor R1 and the second resistor R2, and the first capacitor C1 is connected in parallel to both ends of the second resistor R2; a negative input end of the second comparator is connected to a reference voltage Vref; and an output end of the second comparator is connected to an input end of the first AND gate.

9. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 6, wherein, The second synchronous rectifier control circuit comprises a second synchronous rectifier drive circuit and a second synchronous rectifier voltage stress detection circuit, the second synchronous rectifier voltage stress detection circuit is connected with the second synchronous rectifier drive circuit through a second AND gate; an input end of the second AND gate is connected to an output end of the second synchronous rectifier voltage stress detection circuit and an output end of the second path control signal, and an output end of the second AND gate is connected to the second synchronous rectifier drive circuit.

10. The software and hardware combined implementation of LLC synchronous rectification drive optimization circuit of claim 9, wherein, The second synchronous rectifier voltage stress detection circuit comprises a first comparator, a third resistor R3, a fourth resistor R4 and a second capacitor C2, the third resistor R3 and the fourth resistor R4 are connected in series between a connection point between a same end of the first secondary side Ns1 and a drain of the first synchronous rectifier RS1 and a working ground, a positive input end of the first comparator is connected to a midpoint between the third resistor R3 and the fourth resistor R4, and the second capacitor C2 is connected in parallel to both ends of the fourth resistor R4; a negative input end of the first comparator is connected to a reference voltage Vref; and an output end of the first comparator is connected to an input end of the second AND gate.

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