Oscillator structure and electronic equipment
By designing an oscillator structure that includes an input module and a clamping module, the problem of limited input control voltage range under low power supply voltage was solved, achieving full swing and low gain sensitivity under low power supply conditions, reducing phase noise, and optimizing oscillator performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-03-10
AI Technical Summary
At low supply voltages, the input control voltage range of a voltage-controlled oscillator is limited, leading to increased gain sensitivity and consequently worsening phase noise.
Design an oscillator structure including an input module, a clamping module, and a current-controlled oscillator module. By using a first operational amplifier and appropriate resistor values, ensure that the input control voltage range supports full swing. In the clamping module, the longest path contains only three MOS transistors, reducing the gain and sensitivity requirements.
Achieving full swing of input control voltage under low supply voltage reduces phase noise, optimizes oscillator performance, and saves chip area and current consumption.
Smart Images
Figure CN121643641A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic circuit technology, and in particular relates to an oscillator structure and electronic device. Background Technology
[0002] Designing voltage-controlled oscillators (VCOs) at low supply voltages is a key challenge in current RF chip design. To obtain sufficient tuning range at low supply voltages, the product of the VCO gain sensitivity and the input control voltage range needs to be large enough.
[0003] However, due to the limitation of low power supply voltage, the range of input control voltage is limited, making it difficult to guarantee that the input voltage supports a full swing from 0 to VDD. Therefore, a higher VCO gain sensitivity design is adopted. However, excessive gain sensitivity will degrade the phase noise of the VCO. Summary of the Invention
[0004] This application provides an oscillator structure designed to address the problem that existing voltage-controlled oscillators (VCOs) suffer from high phase noise due to the limited range of input control voltage and the need for higher gain sensitivity.
[0005] The embodiments of this application are implemented as follows: An oscillator structure is provided, including an input module, a clamping module, an output module, and a current-controlled oscillation module; The input module includes a first operational amplifier, a first semiconductor device, a first resistor, and a second resistor; The non-inverting input terminal of the first operational amplifier is connected to the input voltage, the inverting input terminal of the first operational amplifier is connected to the first pin of the first semiconductor device, and the output terminal of the first operational amplifier is connected to the second pin of the first semiconductor device. The third pin of the first semiconductor device is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power supply. The first pin of the first semiconductor device is connected to analog ground via a second resistor; The clamping module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, and a ninth MOSFET; The source of the first MOSFET, the source of the second MOSFET, the element of the third MOSFET, and the element of the fourth MOSFET are all connected to the power supply. The gate and drain of the second MOSFET are simultaneously connected to the gate of the first MOSFET, and the gate and drain of the fourth MOSFET are simultaneously connected to the gate of the third MOSFET. The drain of the first MOSFET is connected to the drain and gate of the fifth MOSFET, and the source of the fifth MOSFET is connected to analog ground. The drain of the second MOSFET is connected to the drain of the sixth MOSFET, the gate of the sixth MOSFET is connected to the third pin of the first semiconductor device, and the source of the sixth MOSFET is connected to the drain of the seventh MOSFET. The gate of the seventh MOSFET is connected to the first voltage terminal, and the source of the seventh MOSFET is connected to analog ground; The drain of the third MOSFET is connected to the drain of the eighth MOSFET, and the source of the eighth MOSFET is connected to the drain of the seventh MOSFET. The drain of the fourth MOSFET is connected to the drain of the output module and the drain of the ninth MOSFET. The gate of the ninth MOSFET is connected to the gate of the fifth MOSFET. The source of the ninth MOSFET is connected to analog ground. The output module includes a third resistor and a second semiconductor device; The first end of the third resistor is connected to the power supply, the second end of the third resistor is connected to the first pin of the second semiconductor device, and the second end of the third resistor is also connected to the gate of the eighth MOS transistor. The second pin of the second semiconductor device is connected to the drain of the fourth MOSFET, and the third pin of the second semiconductor device is connected to the current-controlled oscillation module.
[0006] Furthermore, the current-controlled oscillation module includes several parallel oscillation units. Each oscillation unit includes two MOSFETs and a capacitor. The two MOSFETs are connected in series to form a series circuit. The first end of the series circuit is connected to the output module, and the second end of the series circuit is connected to digital ground. The first end of the capacitor is connected to the line between the two MOSFETs, and the second end of the capacitor is connected to digital ground. The first end of the capacitor is used to connect to an external circuit to output voltage.
[0007] Furthermore, the current-controlled oscillation module includes three or four oscillation units.
[0008] Furthermore, the oscillation unit is a single-ended inverter structure, and the two MOS transistors of the oscillation unit are a PMOS transistor and an NMOS transistor, respectively.
[0009] Furthermore, the oscillation unit is a differential pair structure, with the two MOS transistors in the oscillation unit being either two PMOS transistors or two NMOS transistors. Furthermore, the first semiconductor device and the second semiconductor device are MOSFETs or transistors.
[0010] Secondly, this application also provides an electronic device, including the oscillator structure as described above.
[0011] The beneficial effects of this application are as follows: The oscillator structure provided by this application includes an input module, a clamping module, an output module, and a current-controlled oscillation module; the input module includes a first operational amplifier, a first semiconductor device, a first resistor, and a second resistor; the non-inverting input terminal of the first operational amplifier is connected to the input voltage, the inverting input terminal of the first operational amplifier is connected to the first pin of the first semiconductor device, and the output terminal of the first operational amplifier is connected to the second pin of the first semiconductor device; the third pin of the first semiconductor device is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power supply; the first pin of the first semiconductor device is connected to analog ground through the second resistor; the clamping module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, and a ninth MOSFET; the source of the first MOSFET, the source of the second MOSFET, the element of the third MOSFET, and the element of the fourth MOSFET are all connected to the power supply, the gate and drain of the second MOSFET are simultaneously connected to the gate of the first MOSFET, and the gate and drain of the fourth MOSFET are simultaneously connected to the gate of the third MOSFET; The drain of the first MOSFET is connected to the drain and gate of the fifth MOSFET, and the source of the fifth MOSFET is connected to analog ground; the drain of the second MOSFET is connected to the drain of the sixth MOSFET, the gate of the sixth MOSFET is connected to the third pin of the first semiconductor device, and the source of the sixth MOSFET is connected to the drain of the seventh MOSFET; the gate of the seventh MOSFET is connected to the first voltage terminal, and the source of the seventh MOSFET is connected to analog ground; the drain of the third MOSFET is connected to the drain of the eighth MOSFET, and the source of the eighth MOSFET is connected to the drain of the seventh MOSFET; the drain of the fourth MOSFET is connected to the drain of the output module and the drain of the ninth MOSFET, the gate of the ninth MOSFET is connected to the gate of the fifth MOSFET, and the source of the ninth MOSFET is connected to analog ground; the output module has a third resistor and a second semiconductor device; the first end of the third resistor is connected to the power supply, the second end of the third resistor is connected to the first pin of the second semiconductor device, and the second end of the third resistor is also connected to the gate of the eighth MOSFET; the second pin of the second semiconductor device is connected to the drain of the fourth MOSFET, and the third pin of the second semiconductor device is connected to the current-controlled oscillation module. With the above settings, the input module, by using the first operational amplifier and selecting appropriate resistance values for the first, second, and third resistors, can ensure that the input control voltage range supports full swing. Moreover, since there is only one MOSFET in the path from power supply to ground in the input module, while the longest path from power supply to ground in the clamping module includes three MOSFETs, the power supply only needs to be greater than the turn-on voltage of the three MOSFETs. This allows the oscillator structure provided in this application to operate under low power supply voltage conditions. Under the premise of ensuring that the input control voltage range is full swing, it can achieve smaller gain and sensitivity requirements within a specific tuning range, thereby reducing phase noise and optimizing the overall performance of the oscillator. Attached Figure Description
[0012] Figure 1 This is a circuit structure schematic diagram of one embodiment of the oscillator structure provided in this application; Figure 2 This is a schematic diagram of the working waveform of an embodiment of the oscillator structure provided in this application.
[0013] Explanation of reference numerals in the attached figures: 100 - Input module, 200 - Output module, 300 - Clamping module, 400 - Current-controlled oscillation module, VDD - Power supply, Vctrl - Input voltage, Agnd - Analog ground, Dgnd - Digital ground; V1 - First voltage terminal, Vout - Output voltage, M1 - First MOSFET, M2 - Second MOSFET, M3 - Third MOSFET, M4 - Fourth MOSFET, M5 - Fifth MOSFET, M6 - Sixth MOSFET, M7 - Seventh MOSFET, M... 8 - Eighth MOSFET, M9 - Ninth MOSFET, M10 - Tenth MOSFET, M11 - Eleventh MOSFET, M12 - Twelfth MOSFET, M13 - Thirteenth MOSFET, M14 - Fourteenth MOSFET, M15 - Fifteenth MOSFET, A1 - First op-amp, Q1 - First semiconductor device, R1 - First resistor, R2 - Second resistor, R3 - Third resistor, Q2 - Second semiconductor device, C1 - First capacitor, C2 - Second capacitor, C3 - Third capacitor. Detailed Implementation
[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.
[0015] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0016] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0017] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0018] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0019] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference values and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0020] The oscillator structure provided in this application includes an input module, a clamping module, an output module, and a current-controlled oscillation module. The input module includes a first operational amplifier (op-amp), a first semiconductor device, a first resistor, and a second resistor. The non-inverting input of the first op-amp is connected to the input voltage, the inverting input of the first op-amp is connected to the first pin of the first semiconductor device, and the output of the first op-amp is connected to the second pin of the first semiconductor device. The third pin of the first semiconductor device is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power supply. The first pin of the first semiconductor device is connected to analog ground through the second resistor. The clamping module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, and a ninth MOSFET. The sources of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET are all connected to the power supply. The gate and drain of the second MOSFET are simultaneously connected to the gate of the first MOSFET, and the gate and drain of the fourth MOSFET are simultaneously connected to the gate of the third MOSFET. The first MOSFET... The drain of the S-MOSFET is connected to the drain and gate of the fifth MOSFET, and the source of the fifth MOSFET is connected to analog ground; the drain of the second MOSFET is connected to the drain of the sixth MOSFET, the gate of the sixth MOSFET is connected to the third pin of the first semiconductor device, and the source of the sixth MOSFET is connected to the drain of the seventh MOSFET; the gate of the seventh MOSFET is connected to the first voltage terminal, and the source of the seventh MOSFET is connected to analog ground; the drain of the third MOSFET is connected to the drain of the eighth MOSFET, and the source of the eighth MOSFET is connected to the drain of the seventh MOSFET; the drain of the fourth MOSFET is connected to the drain of the output module and the drain of the ninth MOSFET, the gate of the ninth MOSFET is connected to the gate of the fifth MOSFET, and the source of the ninth MOSFET is connected to analog ground; the output module has a third resistor and a second semiconductor device; the first end of the third resistor is connected to the power supply, the second end of the third resistor is connected to the first pin of the second semiconductor device, and the second end of the third resistor is also connected to the gate of the eighth MOSFET; the second pin of the second semiconductor device is connected to the drain of the fourth MOSFET, and the third pin of the second semiconductor device is connected to the current-controlled oscillation module. With the above settings, the input module, by using the first operational amplifier and selecting appropriate resistance values for the first, second, and third resistors, can ensure that the input control voltage range supports full swing. Moreover, since there is only one MOSFET in the path from power supply to ground in the input module, while the longest path from power supply to ground in the clamping module includes three MOSFETs, the power supply only needs to be greater than the turn-on voltage of the three MOSFETs. This allows the oscillator structure provided in this application to operate under low power supply voltage conditions. Under the premise of ensuring that the input control voltage range is full swing, it can achieve smaller gain and sensitivity requirements within a specific tuning range, thereby reducing phase noise and optimizing the overall performance of the oscillator.
[0021] like Figures 1 to 2 As shown, one embodiment of this application provides an oscillator structure, including an input module 100, a clamping module 300, an output module 200, and a current-controlled oscillation module 400. The input module 100 includes a first operational amplifier A1, a first semiconductor device Q1, a first resistor R1, and a second resistor R2. The non-inverting input terminal of the first operational amplifier A1 is connected to the input voltage Vctrl, the inverting input terminal of the first operational amplifier A1 is connected to the first pin of the first semiconductor device Q1, and the output terminal of the first operational amplifier AQ is connected to the second pin of the first semiconductor device Q1. The third pin of the first semiconductor device Q1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the power supply VDD. The first pin of the first semiconductor device Q1 is connected to analog ground Agnd via the second resistor R2; The clamping module 300 includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, and a ninth MOSFET M9; The source of the first MOSFET M1, the source of the second MOSFET M2, the components of the third MOSFET M3 and the components of the fourth MOSFET M4 are all connected to the power supply VDD. The gate and drain of the second MOSFET M2 are simultaneously connected to the gate of the first MOSFET M1, and the gate and drain of the fourth MOSFET M4 are simultaneously connected to the gate of the third MOSFET M3. The drain of the first MOSFET M1 is connected to the drain and gate of the fifth MOSFET M5, and the source of the fifth MOSFET M5 is connected to analog ground Agnd. The drain of the second MOSFET M2 is connected to the drain of the sixth MOSFET M6, the gate of the sixth MOSFET M6 is connected to the third pin of the first semiconductor device Q1, and the source of the sixth MOSFET M6 is connected to the drain of the seventh MOSFET M7. The gate of the seventh MOSFET M7 is connected to the first voltage terminal V1, and the source of the seventh MOSFET M7 is connected to the analog ground Agnd. The drain of the third MOSFET M3 is connected to the drain of the eighth MOSFET M8, and the source of the eighth MOSFET M8 is connected to the drain of the seventh MOSFET M7. The drain of the fourth MOSFET M4 is connected to the drain of the output module 200 and the ninth MOSFET M9. The gate of the ninth MOSFET M9 is connected to the gate of the fifth MOSFET M5. The source of the ninth MOSFET M9 is connected to analog ground Agnd. The output module includes a third resistor R3 and a second semiconductor device Q2; The first end of the third resistor R3 is connected to the power supply VDD, the second end of the third resistor R3 is connected to the first pin of the second semiconductor device Q2, and the second end of the third resistor R3 is also connected to the gate of the eighth MOSFET M8. The second pin of the second semiconductor device Q2 is connected to the drain of the fourth MOS transistor M4, and the third pin of the second semiconductor device Q2 is connected to the current-controlled oscillation module 400.
[0022] In implementation, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3 and the fourth MOSFET M4 are PMOS transistors, while the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8 and the ninth MOSFET M9 are NMOS transistors.
[0023] The power supply VDD is used to provide the operating voltage, and the analog ground Agnd is the zero potential reference point of the analog circuit. In some microcomputer control systems, the analog ground Agnd needs to be strictly separated from the digital ground Dgnd. Even if there are two ground terminals on the same chip, they should be handled separately and finally connected through a single point to avoid digital loop interference with analog signals.
[0024] A semiconductor device is an electronic device whose conductivity lies between that of a good conductor and an insulator. It utilizes the special electrical properties of semiconductor materials to perform specific functions and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion.
[0025] Optionally, the first semiconductor device Q1 can be a MOSFET or a transistor, without limitation. For example, if the first semiconductor device Q1 is a MOSFET, its first, second, and third pins are the source, gate, and drain of the MOSFET, respectively. Similarly, if the first semiconductor device Q1 is a transistor, its first, second, and third pins are the emitter, base, and collector of the transistor, respectively, without further elaboration.
[0026] In implementation, the second semiconductor device Q2 can refer to the first semiconductor device Q1 described above, without further details.
[0027] For example, the first semiconductor device Q1 can be a self-biased NMOS transistor, and the second semiconductor device Q2 can be a self-biased PMOS transistor.
[0028] With the above settings, the input module 100, by using the first operational amplifier A1 and selecting appropriate resistance values for the first resistor R1, the second resistor R2, and the third resistor R3, can ensure that the input control voltage range supports full swing. Moreover, since there is only one MOSFET in the path from the power supply VDD to ground (analog ground Agnd) in the input module 100, while the longest path from the power supply VDD to ground in the clamping module 300 includes three MOSFETs, the power supply VDD only needs to be greater than the turn-on voltage of the three MOSFETs. This allows the oscillator structure provided in this application to operate under low power supply voltage conditions. Under the premise of ensuring that the input control voltage range is full swing, it can achieve smaller gain sensitivity requirements within a specific tuning range, thereby reducing phase noise and optimizing the overall performance of the oscillator.
[0029] Furthermore, the current-controlled oscillation module 400 includes several parallel oscillation units. Each oscillation unit includes two MOSFETs and a capacitor. The two MOSFETs form a series circuit. The first end of the series circuit is connected to the output module 200. Specifically, the first end of the series circuit is connected to the third pin of the second semiconductor device Q2. The second end of the series circuit is connected to the digital ground Dgnd. The line between the two MOSFETs in the same series circuit is connected to the first end of the capacitor. The second end of the capacitor is connected to the digital ground Dgnd. The first end of the capacitor is used to connect to an external circuit (not shown) to output voltage Vout. The lines between the two MOSFETs in adjacent series circuits are connected.
[0030] In implementation, each oscillation unit includes two MOSFETs, which are alternately turned on and off by a control signal to form a periodic switching action. For example, for the same oscillation unit, when the first MOSFET is on, the second MOSFET is off; similarly, when the first MOSFET is off, the second MOSFET is on, thereby generating an oscillation signal.
[0031] Optionally, the current-controlled oscillation module 400 includes three or four oscillation units.
[0032] For example, taking the current-controlled oscillation module 400 as an example, which includes three oscillation units, the first oscillation unit includes the tenth MOSFET M10 and the eleventh MOSFET M11, the second oscillation unit includes the twelfth MOSFET M12 and the thirteenth MOSFET M13, and the third oscillation unit includes the fourteenth MOSFET M14 and the fifteenth MOSFET M15.
[0033] Among them, the source of the tenth MOSFET M10 is connected to the third pin of the second semiconductor device Q2, the gate of the tenth MOSFET M10 is connected to the gate of the eleventh MOSFET M11, the drain of the tenth MOSFET M10 is connected to the drain of the eleventh MOSFET M11, the source of the eleventh MOSFET M11 is connected to digital ground Dgnd, and the drain of the tenth MOSFET M10 is also connected to the gate of the twelfth MOSFET M12.
[0034] The source of the twelfth MOSFET M12 is connected to the third pin of the second semiconductor device Q2. The gate of the twelfth MOSFET M12 is connected to the gate of the thirteenth MOSFET M13 and the drain of the tenth MOSFET M10. The drain of the twelfth MOSFET M12 is connected to the drain of the thirteenth MOSFET M13. The source of the thirteenth MOSFET M13 is connected to digital ground Dgnd.
[0035] The source of the fourteenth MOSFET M14 is connected to the third pin of the second semiconductor device Q2. The gate of the fourteenth MOSFET M14 is connected to the gate of the fifteenth MOSFET M15 and the drain of the twelfth MOSFET M12. The drain of the fourteenth MOSFET M14 is connected to the drain of the fifteenth MOSFET M15. The source of the fifteenth MOSFET M15 is connected to digital ground Dgnd. The drain of the fourteenth MOSFET M14 is also connected to the gate of the tenth MOSFET M10. The drain of the fourteenth MOSFET M14 is used to output the voltage Vout to the external circuit.
[0036] Each oscillation unit also includes a capacitor, with the first end of the capacitor connected to the line between the two MOS transistors and the second end of the capacitor connected to digital ground Dgnd.
[0037] For example, taking the current-controlled oscillation module 400 described above, which includes three oscillation units, the first oscillation unit includes a tenth MOSFET M10, an eleventh MOSFET M11, and a first capacitor C1; the second oscillation unit includes a twelfth MOSFET M12, a thirteenth MOSFET M13, and a second capacitor C2; and the third oscillation unit includes a fourteenth MOSFET M14, a fifteenth MOSFET M15, and a third capacitor C3. The tenth MOSFET M10, eleventh MOSFET M11, twelfth MOSFET M12, thirteenth MOSFET M13, fourteenth MOSFET M14, and fifteenth MOSFET M15 are described in the above embodiment and will not be repeated. The first terminal of the first capacitor C1 is connected to the drain of the tenth MOSFET M10, and the second terminal of the first capacitor C1 is connected to the digital ground Dgnd. The first terminal of the second capacitor C2 is connected to the drain of the twelfth MOSFET M12, and the second terminal of the second capacitor C2 is connected to the digital ground Dgnd. The first terminal of the third capacitor C3 is connected to the drain of the fourteenth MOSFET M14, and the second terminal of the third capacitor C3 is connected to the digital ground Dgnd. The first terminal of the third capacitor C3 is also connected to the gate of the tenth MOSFET M10, and the first terminal of the third capacitor C3 is used to output the voltage Vout to the external circuit.
[0038] The specific implementation process of this embodiment is as follows: The resistance values of the second resistor R2 and the first resistor R1 are in a ratio of N:1.
[0039] The input voltage Vctrl passes through the circuit composed of the first operational amplifier A1 and the first semiconductor device Q1. At node VA, the voltage VA = Vctrl. Since the range of Vctrl is 0~VDD, the voltage range of VA is 0~VDD.
[0040] The current flowing through the second resistor R2 can be expressed as VA / R2, and its current range is 0~VDD / R2.
[0041] The current flowing through the first resistor R1 is equal to the current flowing through the second resistor R2, and its current range is 0~VDD / R2.
[0042] The voltage at node VB is VB=VDD-R1*VA / R2=VDD-Vctrl*R1 / R2=VDD-Vctrl / N, and its voltage range is VDD~VDD(1-1 / N).
[0043] Due to the clamping module 300 composed of the first MOSFET M1 to the ninth MOSFET M9, the gate voltages of the sixth MOSFET M6 and the eighth MOSFET M8 are equal, so VB=VC. That is, the voltage at node VC is VC=VB=VDD-Vctrl / N, and its voltage range is VDD~VDD(1-1 / N).
[0044] The current flowing through the third resistor R3 can be expressed as (VDD-VC) / R3, that is, the current flowing through R3 is Vctrl / N / R3, and its current range is 0~VDD / N / R3.
[0045] The current-controlled oscillation module 400, composed of the tenth MOSFET M10 to the fifteenth MOSFET M15 and the first capacitor C1 to the third capacitor C3, is a current-value-based oscillation module. The switching threshold of the tenth MOSFET M10 to the fifteenth MOSFET M15 is denoted as Vswing, and the capacitance of the first capacitor C1 to the third capacitor C3 is denoted as C. The oscillation frequency Vout of the current-controlled oscillation module 400 is proportional to the current flowing through the third resistor R3. Its oscillation frequency _Freq can be expressed as: Freq=K / 6*I3 / (C*Vswing)=K / 6*Vctrl / (N*R3)*1 / (C*Vswing)① In formula ①, K is a constant, and the oscillation frequency range of Vout is 0~K / 6*VDD / (N*R3)*1 / (C*Vswing) The operating waveforms of the input voltage Vctrl, VA, second resistor R2, VB, VC, third resistor R3, and output voltage Vout in the oscillator are as follows: Figure 2 As shown.
[0046] In the oscillator structure provided in this application, the power supply VDD only needs to be greater than the threshold voltage Vthp of one PMOS and the source-drain voltage Vdsn of two NMOS transistors. For example, the power supply VDD only needs to be greater than the threshold voltage Vthp of the second MOS transistor M2, the source-drain voltage Vdsn of the sixth MOS transistor M6, and the source-drain voltage Vdsn of the seventh MOS transistor M7. In this case, the second MOS transistor M2, the sixth MOS transistor M6, and the seventh MOS transistor M7 form one circuit. Alternatively, the power supply VDD only needs to be greater than the threshold voltage Vthp of the third MOS transistor M3, the source-drain voltage Vdsn of the eighth MOS transistor M8, and the source-drain voltage Vdsn of the seventh MOS transistor M7. In this case, the third MOS transistor M3, the eighth MOS transistor M8, and the seventh MOS transistor M7 form one circuit. Therefore, this embodiment can operate under low power supply VDD voltage conditions. At the same time, based on the use of the first operational amplifier A1 and the selection of circuit parameters, the range of the input control power supply VDD can be guaranteed to be full swing. This allows for smaller gain and sensitivity requirements within a specific tuning range, thereby reducing phase noise and optimizing the overall system performance. Moreover, by not using on-chip inductors, valuable chip area is saved, while current consumption is reduced.
[0047] As one possible implementation, taking the current-controlled oscillation module 400 comprising four oscillation units as an example, the first oscillation unit includes a tenth MOSFET M10, an eleventh MOSFET M11, and a first capacitor C1; the second oscillation unit includes a twelfth MOSFET M12, a thirteenth MOSFET M13, and a second capacitor C2; the third oscillation unit includes a fourteenth MOSFET M14, a fifteenth MOSFET M15, and a third capacitor C3; and the fourth oscillation unit includes a sixteenth MOSFET (not shown), a seventeenth MOSFET (not shown), and a fourth capacitor (not shown). It is understood that the tenth MOSFET M10, eleventh MOSFET M11, twelfth MOSFET M12, thirteenth MOSFET M13, fourteenth MOSFET M14, fifteenth MOSFET M15, first capacitor C1, second capacitor C2, and third capacitor C3 refer to the above embodiment and will not be described again. The connection structure of the sixteenth MOSFET (not shown in the figure), the seventeenth MOSFET (not shown in the figure), and the fourth capacitor (not shown in the figure) can be compared with the structure of the other three oscillation units, for example, referring to the connection structure of the tenth MOSFET M10, the eleventh MOSFET M11, and the first capacitor C1, which will not be elaborated further.
[0048] It should be noted that the circuit structure of the clamping module 300 described above can also adopt other structural methods, as long as VB=VC, there is no limitation.
[0049] Optionally, the oscillation unit can adopt a single-ended inverter structure, with one PMOS transistor and one NMOS transistor in the two MOS transistors of the oscillation unit. For example, the tenth MOS transistor M10 is a PMOS transistor and the eleventh MOS transistor M11 is an NMOS transistor, or the twelfth MOS transistor M12 is a PMOS transistor and the thirteenth MOS transistor M13 is an NMOS transistor, and so on, without further details.
[0050] Optionally, the oscillation unit can also adopt a differential pair structure, with the two MOS transistors of the oscillation unit being either two PMOS transistors or two NMOS transistors. For example, the tenth MOS transistor M10 is a PMOS transistor, and the eleventh MOS transistor M11 is also a PMOS transistor. Alternatively, the tenth MOS transistor M10 is an NMOS transistor, the eleventh MOS transistor M11 is also an NMOS transistor, and so on, without further elaboration.
[0051] Secondly, this application also provides an electronic device, including the oscillator structure as described above.
[0052] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the structure and implementation principle of the electronic device described above can be referred to the corresponding structure and implementation principle in the foregoing embodiments, and will not be repeated here.
[0053] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. An oscillator structure, characterized by The input terminal module, the clamp voltage module, the output terminal module and the current control oscillation module are included. The input terminal module includes a first operational amplifier, a first semiconductor device, a first resistor and a second resistor. The non-inverting input terminal of the first operational amplifier is connected with an input voltage, the inverting input terminal of the first operational amplifier is connected with the first pin of the first semiconductor device, and the output terminal of the first operational amplifier is connected with the second pin of the first semiconductor device. The third pin of the first semiconductor device is connected with the first end of the first resistor, and the second end of the first resistor is connected with a power supply. The first pin of the first semiconductor device is connected with an analog ground through the second resistor. The clamp voltage module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a ninth MOS tube. The source of the first MOS tube, the source of the second MOS tube, the element of the third MOS tube and the element of the fourth MOS tube are all connected with the power supply, the gate and the drain of the second MOS tube are simultaneously connected with the gate of the first MOS tube, and the gate and the drain of the fourth MOS tube are simultaneously connected with the gate of the third MOS tube. The drain of the first MOS tube is connected with the drain and the gate of the fifth MOS tube, and the source of the fifth MOS tube is connected with the analog ground. The drain of the second MOS tube is connected with the drain of the sixth MOS tube, the gate of the sixth MOS tube is connected with the third pin of the first semiconductor device, and the source of the sixth MOS tube is connected with the drain of the seventh MOS tube. The gate of the seventh MOS tube is connected with a first voltage terminal, and the source of the seventh MOS tube is connected with the analog ground. The drain of the third MOS tube is connected with the drain of the eighth MOS tube, and the source of the eighth MOS tube is connected with the drain of the seventh MOS tube. The drain of the fourth MOS tube is connected with the output terminal module and the drain of the ninth MOS tube, the gate of the ninth MOS tube is connected with the gate of the fifth MOS tube, and the source of the ninth MOS tube is connected with the analog ground. The output terminal module includes a third resistor and a second semiconductor device. The first end of the third resistor is connected with the power supply, the second end of the third resistor is connected with the first pin of the second semiconductor device, and the second end of the third resistor is also connected with the gate of the eighth MOS tube. The second pin of the second semiconductor device is connected with the drain of the fourth MOS tube, and the third pin of the second semiconductor device is connected with the current control oscillation module.
2. The oscillator structure of claim 1, wherein, The current control oscillation module comprises several parallel oscillation units, each of which comprises two MOS transistors and a capacitor, the two MOS transistors are connected in series to form a series body, the first end of the series body is connected with the output terminal module, the second end of the series body is connected with a digital ground, the first end of the capacitor is connected with a line between the two MOS transistors, the second end of the capacitor is connected with the digital ground, and the first end of the capacitor is used for being connected with an external circuit to output a voltage.
3. The oscillator structure of claim 2, wherein, The current control oscillation module comprises three or four oscillation units.
4. The oscillator structure of any of claims 2 to 3, wherein, The oscillation unit is a single-ended inverter structure, and the two MOS transistors of the oscillation unit are a PMOS transistor and an NMOS transistor respectively.
5. The oscillator structure of any of claims 2 to 3, wherein, The oscillation unit is a differential pair structure, and the two MOS transistors of the oscillation unit are two PMOS transistors or two NMOS transistors.
6. The oscillator structure of claim 1, wherein, The first semiconductor device and the second semiconductor device are MOS transistors or triodes.
7. An electronic device, comprising: An oscillator structure as claimed in any one of claims 1 to 6.