Single-stage quadruplicated frequency circuit

Abstract

The invention relates to the technical field of radio frequency integrated circuits, and discloses a single-stage quadruplicated frequency circuit, which comprises an input matching network, a quadruplicated frequency unit, a harmonic suppression network, a grid bias circuit and an output matching network, the input matching network is connected with the quadruplicated frequency unit, and the input matching network matches the input impedance of the quadruplicated frequency unit to a preset ohm; the quadruplicated frequency unit at least comprises a transistor, and the transistor generates harmonic signals corresponding to input signals; the grid bias circuit is connected with the grid of the transistor, and the grid bias circuit provides grid voltage for the transistor; the harmonic suppression network is connected with the quadruplicated frequency unit; and the output matching network is connected with the harmonic suppression network, and outputs a quadruplicated frequency signal corresponding to the input signal. In this way, multiple times of harmonic suppression is at least achieved, and the quality of output signals of the single-stage quadruplicated frequency circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and in particular to a single-stage quadruple frequency multiplier circuit. Background Technology

[0002] In recent years, with the rapid development of mobile communication, the Internet of Things (IoT), and wireless network technologies, higher requirements have been placed on radio frequency (RF) circuit design. For faster transmission rates, the research and application of the millimeter-wave band are of great significance. In RF communication systems, the stability and purity of the frequency source have a significant impact on the overall system performance. Currently, there are two ways to generate a local oscillator (LO) signal: one is to generate the LO signal directly through oscillation, and the other is to generate the signal using a frequency-doubled low-frequency source. In the millimeter-wave band, directly generating the LO signal is very difficult, as it is hard to guarantee phase noise and bandwidth. Low-frequency source design is relatively mature, so using a frequency-doubled low-frequency source can yield a high-purity LO signal. For frequency multipliers, important indicators include conversion gain and the degree of suppression of different harmonics.

[0003] Currently, there are many types of frequency multiplier designs, classified as doublers and quadruplers, balanced and unbalanced frequency multipliers, injection-locked frequency multipliers, and harmonic filtering frequency multipliers, among others. Among these, single-stage unbalanced frequency multipliers are simple to design, have moderate bandwidth, and achieve high harmonic suppression after filtering, resulting in considerable research achievements. However, for single-stage quadruplers, typical filtering structures exhibit low suppression of the third harmonic and some loss of the fourth harmonic, leading to poor output signal quality. Summary of the Invention

[0004] The purpose of this invention is to provide a single-stage quadruple frequency multiplier circuit to improve the output signal quality of the single-stage quadruple frequency multiplier circuit.

[0005] To achieve the above objectives, the present invention provides a single-stage quadruple frequency multiplier circuit, comprising: an input matching network, a quadruple frequency multiplier unit, a harmonic suppression network, a gate bias circuit, and an output matching network;

[0006] The input matching network is connected to the fourth harmonic unit, and the input matching network matches the input impedance of the fourth harmonic unit to a preset ohm.

[0007] The fourth harmonic unit includes at least a transistor, which generates harmonic signals corresponding to the input signal.

[0008] The gate bias circuit is connected to the gate of the transistor, and the gate bias circuit provides a gate voltage to the transistor.

[0009] The harmonic suppression network is connected to the fourth harmonic unit; the output matching network is connected to the harmonic suppression network, and the output matching network outputs the fourth harmonic signal corresponding to the input signal.

[0010] Compared with existing technologies, the present invention provides a single-stage fourth harmonic circuit. The input matching network matches the input impedance of the fourth harmonic unit to a preset ohm. The fourth harmonic unit includes at least a transistor that generates harmonic signals corresponding to the input signal. A band-stop filter module in the harmonic suppression network provides drain voltage to the transistor and suppresses the second and third harmonic signals. A first microstrip line suppresses the fundamental, third, and fifth harmonic signals. A high-pass filter module suppresses the fundamental, second, and third harmonic signals. A gate bias circuit is connected to the gate of the transistor and provides a gate voltage. The output matching network is connected to the harmonic suppression network. The output matching network outputs the fourth harmonic signal corresponding to the input signal. By designing multiple levels of suppression, multiple suppressions of the third harmonic are achieved, reducing the fourth harmonic loss caused by suppressing the third harmonic in traditional structures, as well as the suppression of other harmonics, thus improving the quality of the output signal of the single-stage fourth harmonic circuit. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figure 1 A schematic diagram of the circuit structure of a single-stage quadruple frequency multiplier circuit provided in an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of a circuit structure for another connection method of the band-stop filter module in a single-stage quadruple frequency multiplier circuit provided in an embodiment of the present invention;

[0014] Figure 3 The diagram shows the harmonic suppression result obtained after simulation using a band-stop filter module in a single-stage quadruple harmonic suppression network, as provided in an embodiment of the present invention.

[0015] Figure 4(a) shows the fundamental frequency suppression result obtained by simulation using a single-stage quadruple frequency circuit according to an embodiment of the present invention.

[0016] Figure 4(b) shows the second harmonic suppression result obtained by simulation using a single-stage quadruple frequency circuit according to an embodiment of the present invention.

[0017] Figure 4(c) shows the third harmonic suppression result obtained by simulation using a single-stage quadruple frequency circuit according to an embodiment of the present invention.

[0018] Figure 4(d) shows the fifth harmonic suppression result obtained by simulation using a single-stage quadruple frequency circuit according to an embodiment of the present invention.

[0019] Figure label:

[0020] 10 - Input matching network; 20 - Quadruple frequency unit; 30 - Harmonic suppression network; 40 - Gate bias circuit; 50 - Output matching network; 31 - Band-stop filter module; 32 - High-pass filter module. Detailed Implementation

[0021] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0022] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0023] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0024] like Figure 1 As shown, this embodiment of the invention provides a single-stage quadruple frequency multiplier circuit, which may include: an input matching network 10, a quadruple frequency multiplier unit 20, a harmonic suppression network 30, a gate bias circuit 40, and an output matching network 50.

[0025] The input matching network 10 is connected to the quadruple frequency unit 20, and the input matching network 10 matches the input impedance of the quadruple frequency unit 20 to a preset ohm.

[0026] The quadruple frequency unit 20 includes at least a transistor, which generates harmonic signals corresponding to the input signal;

[0027] The gate bias circuit 40 is connected to the gate of the transistor, and the gate bias circuit 40 provides the gate voltage Vg to the transistor.

[0028] Harmonic suppression network 30 is connected to the fourth harmonic unit 20; output matching network 50 is connected to harmonic suppression network 30, and output matching network 50 outputs the fourth harmonic signal corresponding to the input signal.

[0029] Specifically, each harmonic signal includes at least the fundamental wave, the second harmonic signal, the third harmonic signal, and the fifth harmonic signal;

[0030] The harmonic suppression network 30 includes a band-stop filter module 31, a first microstrip line L1, and a high-pass filter module 32;

[0031] The band-stop filter module 31 is connected to the drain of the transistor. The band-stop filter module 31 provides the drain voltage of the transistor and suppresses the second and third harmonic signals. The first microstrip line suppresses the fundamental, third, and fifth harmonic signals. The high-pass filter module 32 suppresses the fundamental, second, and third harmonic signals.

[0032] As can be seen from the above, the input matching network matches the input impedance of the fourth harmonic unit to a preset ohm. The fourth harmonic unit includes at least a transistor in the transistor that generates each harmonic signal corresponding to the input signal. The band-stop filter module in the harmonic suppression network provides the drain voltage of the transistor and suppresses the second and third harmonic signals. The first microstrip line suppresses the fundamental, third, and fifth harmonic signals. The high-pass filter module suppresses the fundamental, second, and third harmonic signals. The gate bias circuit is connected to the gate of the transistor and provides the gate voltage to the transistor. The output matching network is connected to the harmonic suppression network. The output matching network outputs the fourth harmonic signal corresponding to the input signal. In this way, by designing multiple levels of suppression methods, the third harmonic is suppressed, as well as other harmonics, thereby improving the quality of the output signal of the single-stage fourth harmonic circuit.

[0033] Optionally, such as Figure 1 As shown, the band-stop filter module 31 includes a second microstrip line L2, a third microstrip line L3, a fourth microstrip line L4, a fifth microstrip line L5, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a first resistor R1.

[0034] The first end of the second microstrip line L2 and the first end of the third microstrip line L3 are both connected to the drain voltage Vd; the first end of the fourth microstrip line L4 is connected to the second end of the third microstrip line L3, the second end of the fourth microstrip line L4 is connected to the first end of the fifth microstrip line L5, and the second end of the fifth microstrip line L5 is grounded.

[0035] The first terminal of the first capacitor C1 is connected to the first terminal of the fourth microstrip line L4, and the second terminal of the first capacitor C1 is grounded.

[0036] The first terminal of the second capacitor C2 is connected to the second terminal of the fourth microstrip line L4, and the second terminal of the second capacitor C2 is grounded.

[0037] The second end of the second microstrip line L2 and the first end of the first resistor R1 are both connected to the drain power supply.

[0038] The third capacitor C3 is connected to the second terminal of the first resistor, and the second terminal of the third capacitor C3 is grounded.

[0039] It should be noted that in the band-stop filter module, the first capacitor C1, the second capacitor C2, the third microstrip line L3, the fourth microstrip line L4, and the fifth microstrip line L5 constitute the core filter network, which can effectively suppress the second and third harmonic signals. The fifth microstrip line L5, the third capacitor C3, and the first resistor R1 in the band-stop filter module constitute the drain voltage supply circuit, providing the bias drain voltage for the transistor.

[0040] Optionally, such as Figure 2 As shown, the band-stop filter module includes a third microstrip line L3, a fourth microstrip line L4, a fifth microstrip line L5, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a first resistor R1.

[0041] The first terminal of the first resistor R1 and the first terminal of the fifth microstrip line L5 are both connected to the drain bias voltage Vd; the first terminal of the fourth microstrip line L4 is connected to the second terminal of the fifth microstrip line L5, the second terminal of the fourth microstrip line L4 is connected to the first terminal of the third microstrip line L3, and the second terminal of the third microstrip line L3 is connected to the drain of the transistor.

[0042] The first terminal of the first capacitor C1 is connected to the second terminal of the fourth microstrip line L4, and the second terminal of the first capacitor C1 is grounded.

[0043] The first terminal of the second capacitor C2 is connected to the first terminal of the fourth microstrip line L4, and the second terminal of the second capacitor C2 is grounded.

[0044] The first terminal of the third capacitor C3 is connected to the second terminal of the first resistor R1, and the second terminal of the third capacitor C3 is grounded.

[0045] As can be seen from the above, compared to Figure 1 The band-stop filter module in the middle, Figure 2 The band-stop filter module in the circuit has a different connection method, which reduces the circuit area occupied by the second microstrip line L2, and thus reduces the layout area of ​​the single-stage quadruple frequency multiplier circuit.

[0046] Optionally, such as Figure 1 As shown, the high-pass filter module 32 includes a sixth microstrip line L6, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6.

[0047] The first terminal of the fourth capacitor C4 is connected to the drain; the first terminal of the fifth capacitor C5 and the first terminal of the sixth microstrip line L6 are both connected to the second terminal of the fourth capacitor C4.

[0048] The first terminal of the sixth capacitor C6 is connected to the second terminal of the sixth microstrip line L6, and the second terminal of the sixth capacitor C6 is grounded; the second terminal of the fifth capacitor C5 is connected to the output matching network 50.

[0049] Optionally, the first end of the first microstrip line L1 is connected to the drain, and the second end of the first microstrip line L1 is open-circuited; the length of the first microstrip line L1 is one-quarter of the fundamental wavelength.

[0050] Optionally, such as Figure 1 As shown, the quadruple frequency unit 20 also includes a seventh microstrip line L7; the first end of the seventh microstrip line L7 is connected to the source of the transistor, and the second end of the seventh microstrip line L7 is grounded.

[0051] Optionally, such as Figure 1 As shown, the input matching network 10 includes a seventh capacitor C7, an eighth microstrip line L8, and a ninth microstrip line L9; the first terminal of the seventh capacitor C7 is connected to the input signal; the first terminals of the eighth microstrip line L8 and the ninth microstrip line L9 are both connected to the second terminal of the seventh capacitor C7; the second terminal of the ninth microstrip line L9 is connected to the gate.

[0052] Optionally, such as Figure 1 As shown, the gate bias circuit 40 includes a third resistor R3, an eighth capacitor C8, and an eighth microstrip line L8.

[0053] The first terminal of the third resistor R3 is connected to the gate voltage Vg; the first terminal of the eighth capacitor C8 and the second terminal of the eighth microstrip line L8 are both connected to the second terminal of the third resistor R3; the second terminal of the eighth capacitor C8 is grounded.

[0054] Optionally, such as Figure 1 As shown, the output matching network 50 includes a tenth microstrip line L10 and a ninth capacitor C9; the ninth capacitor C9 is a DC blocking capacitor.

[0055] The first terminal of the tenth microstrip line L10 and the first terminal of the ninth capacitor C9 are both connected to the second terminal of the fifth capacitor C5.

[0056] The working principle of a single-stage quadruple frequency multiplier circuit is explained below:

[0057] After the circuit starts up, the input signal is input to the gate of the transistor, generating a current i1 at the drain of the transistor. A Taylor expansion of this current yields:

[0058] i1 = a0 + a1v i +a2v i2 +a3v i 3 +a4v i 4 +a5v i 5 (1)

[0059] Where a0 is the DC current in the circuit, a1 is the amplitude of the first harmonic signal, a2 is the amplitude of the second harmonic signal, a3 is the amplitude of the third harmonic signal, a4 is the amplitude of the fourth harmonic signal, and a5 is the amplitude of the fifth harmonic signal; v i This is the input gate voltage.

[0060] The signal wave propagates in the transmission line, i.e., the first microstrip line L1, and the total voltage on the transmission line is the sum of the incident wave and the reflected wave:

[0061] V(l)=V0 + e -jβl +V0 - e jβl (2)

[0062] The total current is:

[0063]

[0064] Where V(l) is the total voltage, l is the transmission line coordinate, and β is the propagation constant; V0 + It is the forward transmission voltage at the origin of the coordinate system, V0 - It is the reverse transmission voltage at the origin of the coordinate system; V0 + e -jβl The incident wave is generated from a source where l < 0; Z0 is the characteristic impedance; V0 - e jβl It takes the form of a reflected wave. If there is a load at l=0, then

[0065]

[0066] Among them, Z L The load impedance at point 1 = 0;

[0067] From the above formula, we can obtain:

[0068]

[0069] The voltage reflection coefficient Γ is:

[0070]

[0071] Therefore, the total voltage on the transmission line can be expressed as:

[0072] V(l)=V0 + (e-jβl +Γe jβl (7)

[0073] The total current on the transmission line can be expressed as:

[0074]

[0075] When the transmission line termination is open, Z L If Γ = ∞, then Γ = 1, and the total voltage is:

[0076] V(l)=V0 + (e -jβl +Γe jβl ) = 2V0 + cos(βl), if the line length is one-quarter of the fundamental wavelength, then That is, for a signal with wavelength λ, this open path is short-circuited, so the signal can pass through the signal path. An open path for a specific wavelength filters out signals of that wavelength.

[0077] Based on the above principle analysis, the first microstrip line L1 is set as an open-circuit microstrip line, and the length of the first microstrip line L1 is determined as follows: The fundamental wavelength, and the length of the first microstrip line L1 is also the third harmonic wavelength. The wavelength, and also the length of the first microstrip line L1, are fifth harmonics. wavelength.

[0078] As can be seen from the above, for the third and fifth harmonics, the first microstrip line L1 is also equivalent to a short circuit, so it also has a filtering effect on the third and fifth harmonics.

[0079] It should be noted that in the millimeter-wave band, the inductance value of the inductor changes significantly due to parasitic effects, which can easily lead to errors in both simulation and testing. Therefore, existing technologies often use microstrip lines to replace all inductors to reduce errors. However, existing technologies use a large number of open-circuit microstrip lines for filtering. For example, in existing technologies, a microstrip line that only filters the second harmonic requires a length of 1600µm in the Ka-band, resulting in a large area after folding in the circuit layout. In contrast, the high-pass filter in this embodiment only requires a small capacitor and a 300µm line, which can greatly reduce the circuit layout area and facilitate integration. At the same time, the LC network in the band-stop filter module uses... Figure 2 The connection method used for drain bias circuits does not occupy more area, further saving circuit area.

[0080] As can be seen from the above, the high-pass filter module composed of the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, and the sixth microstrip line L6 suppresses low-order harmonics.

[0081] The filter network consisting of the first capacitor C1, the second capacitor C2, the third microstrip line L3, the fourth microstrip line L4, and the fifth microstrip line L5 introduces two troughs in the transfer function, which can suppress the second and third harmonics. The principle is that its network impedance has two zeros in frequencies greater than 0.

[0082] To address the insufficient suppression of the third harmonic by the traditional quadruple frequency harmonic structure in existing technologies, this invention employs a band-stop filter module, a first microstrip line, and a high-pass filter module to jointly suppress the third harmonic. After passing through the harmonic suppression network, the harmonic components other than the fourth harmonic are fully matched. Finally, the signal output to the output terminal OUT through the output matching network is a quadruple frequency harmonic signal. This not only provides better suppression and reduces the loss of the fourth harmonic, but also reduces the circuit area.

[0083] It is understood that the bandstop network in the embodiments of the present invention has high tunability. By adjusting the length of the microstrip line and the size of the capacitor, the suppression band can be adjusted, and harmonics at the edge of the bandwidth can be suppressed, thereby increasing the bandwidth.

[0084] The following simulation was performed using the single-stage quadruple frequency multiplier circuit designed above. The simulation conditions were as follows: the circuit was built on a simulation platform using 0.25μm GaAsp HEMT technology and simulated using the HB simulation tool. The bias voltage VG was 0.45V, VD was 5V, the input signal frequency was 8.65GHz, and the operating temperature was 25℃.

[0085] Add ports (input and output ports) to the input port IN and the output port OUT respectively, and then perform HB (harmonic balance) simulation.

[0086] S-parameter simulations were performed separately on the band-stop filter section of the harmonic suppression network in the embodiment of this invention, with the two-port impedance set to 50Ω. The effect on harmonic suppression is shown in the appendix. Figure 3 The vertical axis represents the absolute value of the transfer function, i.e., the degree of harmonic suppression. It can be seen that the network can suppress the second and third harmonics by more than 10dB. Furthermore, the peak value and the suppression frequency band can be adjusted by adjusting the microstrip line length and the capacitance.

[0087] The suppression levels of different harmonics in the embodiments of the present invention are shown in Figure 4. Figure 4(a) shows that the fundamental frequency suppression ratio is greater than 35dBc in the input 8.3GHz to 9GHz frequency band. Figure 4(b) shows that the second harmonic suppression ratio is greater than 42dBc in the input 8.3GHz to 9GHz frequency band. Figure 4(c) shows that the third harmonic suppression ratio is greater than 25dBc in the input 8.3GHz to 9GHz frequency band. Figure 4(d) shows that the fifth harmonic suppression ratio is greater than 25dBc in the input 8.3GHz to 9GHz frequency band.

[0088] Theoretical analysis and simulation results show that the single-stage quadruple frequency circuit of one embodiment of the present invention enhances the harmonic suppression effect, has a high harmonic suppression degree at the frequency center point, and can effectively enhance harmonic suppression through a new band-stop filter, and can be applied to Ka-band wireless communication local oscillator systems.

[0089] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0090] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A single-stage quadrupler circuit, characterized by comprising: The application relates to a quadrupling circuit. The input matching network is connected with the quadrupling unit, the input matching network matches the input impedance of the quadrupling unit to a preset ohm; The quadrupling unit at least comprises a transistor, the transistor generates each harmonic signal corresponding to an input signal; The gate bias circuit is connected with the gate of the transistor, and the gate bias circuit provides a gate voltage for the transistor; The harmonic suppression network is connected with the quadrupling unit, and the output matching network is connected with the harmonic suppression network, and the output matching network outputs a quadrupling signal corresponding to the input signal. The each harmonic signal at least comprises a fundamental wave, a second harmonic signal, a third harmonic signal and a fifth harmonic signal; 2. The single-stage quadrupler circuit of claim 1, wherein, The harmonic suppression network comprises a band-stop filtering module, a first microstrip line and a high-pass filtering module; The band-stop filtering module is connected with the drain of the transistor, the band-stop filtering module provides a drain voltage for the transistor and suppresses the second harmonic signal and the third harmonic signal; the first microstrip line suppresses the fundamental wave, the third harmonic signal and the fifth harmonic signal; and the high-pass filtering module suppresses the fundamental wave, the second harmonic signal and the third harmonic signal. The band-stop filtering module comprises a second microstrip line, a third microstrip line, a fourth microstrip line, a fifth microstrip line, a first capacitor, a second capacitor, a third capacitor and a first resistor; 3. The single-stage quadrupler circuit of claim 2, wherein, The first end of the second microstrip line and the first end of the third microstrip line are connected with the drain voltage; the first end of the fourth microstrip line is connected with the second end of the third microstrip line, the second end of the fourth microstrip line is connected with the first end of the fifth microstrip line, and the second end of the fifth microstrip line is grounded; The first end of the first capacitor is connected with the first end of the fourth microstrip line, and the second end of the first capacitor is grounded; The first end of the second capacitor is connected with the second end of the fourth microstrip line, and the second end of the second capacitor is grounded; The second end of the second microstrip line and the first end of the first resistor are connected with the drain voltage source; The third capacitor is connected with the second end of the first resistor, and the second end of the third capacitor is grounded. The band-stop filtering module comprises the third microstrip line, the fourth microstrip line, the fifth microstrip line, the first capacitor, the second capacitor, the third capacitor and the first resistor; 4. The single-stage quadrupler circuit of claim 3, wherein, The first end of the first resistor and the first end of the fifth microstrip line are connected with the drain bias voltage; the first end of the fourth microstrip line is connected with the second end of the fifth microstrip line, the second end of the fourth microstrip line is connected with the first end of the third microstrip line, and the second end of the third microstrip line is connected with the drain of the transistor; The first end of the first capacitor is connected with the second end of the fourth microstrip line, and the second end of the first capacitor is grounded; The first end of the second capacitor is connected with the first end of the fourth microstrip line, and the second end of the second capacitor is grounded; The first end of the third capacitor is connected with the second end of the first resistor, and the second end of the third capacitor is grounded. ​ 5. The single-stage quadrupler circuit of claim 2, wherein, The high-pass filter module comprises a sixth microstrip line, a fourth capacitor, a fifth capacitor and a sixth capacitor; The first end of the fourth capacitor is connected with the drain; the first end of the fifth capacitor and the first end of the sixth microstrip line are both connected with the second end of the fourth capacitor; The first end of the sixth capacitor is connected with the second end of the sixth microstrip line, and the second end of the sixth capacitor is grounded; the second end of the fifth capacitor is connected with the output matching network.

6. The single-stage quadrupler circuit of claim 2, wherein, The first end of the first microstrip line is connected with the drain; the line length of the first microstrip line is one quarter of the fundamental wavelength.

7. The single-stage quadrupler circuit of claim 1, wherein, The four times frequency unit further comprises a seventh microstrip line; the first end of the seventh microstrip line is connected with the source of the transistor, and the second end of the seventh microstrip line is grounded.

8. The single-stage quadrupler circuit of claim 1, wherein, The input matching network comprises a seventh capacitor, an eighth microstrip line and a ninth microstrip line; the first end of the seventh capacitor is connected with the input signal; The first end of the eighth microstrip line and the first end of the ninth microstrip line are both connected with the second end of the seventh capacitor; the second end of the ninth microstrip line is connected with the gate.

9. The single-stage quadrupler circuit of claim 8, wherein, The gate bias circuit comprises a third resistor, an eighth capacitor and the eighth microstrip line; The first end of the third resistor is connected with the gate voltage; the first end of the eighth capacitor and the second end of the eighth microstrip line are both connected with the second end of the third resistor; the second end of the eighth capacitor is grounded.

10. The single-stage quadrupler circuit of claim 5, wherein, The output matching network comprises a tenth microstrip line and a ninth capacitor; The first end of the tenth microstrip line and the first end of the ninth capacitor are both connected with the second end of the fifth capacitor.

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