All-digital clock recovery method and system under Baud rate sampling rate
By combining highly nonlinear timing phase error detection with finite-domain fast convolution filtering, the problems of low power consumption, low jitter, and high precision in all-digital clock recovery under baud rate sampling are solved, achieving low-complexity clock recovery and supporting high-speed fiber optic communication systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-03-10
AI Technical Summary
Existing technologies struggle to achieve low-power, low-cost, low-jitter, and high-precision fully digital clock recovery at baud rate sampling. Traditional solutions suffer from bandwidth limitations, high computational complexity, and insufficient accuracy in timing phase error detection.
A collaborative design of highly nonlinear timing phase error detection and finite-domain fast convolution filtering is adopted. By performing block processing, finite-domain transformation and filtering operations on the input signal, the timing phase error is calculated and the tap coefficient vector is updated to generate phase control information to achieve clock recovery.
It achieves high bandwidth and phase modulation performance with extremely low computational complexity, significantly reduces timing jitter, provides a low-power all-digital clock recovery solution, and supports high-speed fiber optic communication systems.
Smart Images
Figure CN121643752A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of optical fiber communication and digital signal processing technology, and particularly relates to a fully digital clock recovery method and system under baud rate sampling rate. Background Technology
[0002] Coherent detection technology, due to its high transmission rate, high sensitivity, and ability to effectively compensate for channel impairments when combined with digital signal processing (DSP) technology, has become a key technology for long-distance optical fiber communication systems. With the explosive growth of data center capacity, coherent detection-based technologies are gradually extending to metropolitan area networks and even short-distance interconnect networks for data centers. However, its further widespread application is mainly limited by power consumption and cost. In typical coherent optical modules, the analog-to-digital converter (ADC) and DSP core are the main sources of power consumption. The power consumption of the ADC is directly proportional to the sampling rate, while the computational complexity of the DSP algorithm directly determines the hardware resources and power consumption of the application-specific integrated circuit (ASIC). Therefore, achieving baud rate sampling and reducing the computational complexity of the DSP algorithm is one of the key paths to reduce the overall power consumption and cost of high-speed optical fiber communication systems.
[0003] At the coherent receiver, the clock recovery (CR) module is the core component for synchronizing the clocks of the transmitter and receiver, ensuring that sampling occurs at the optimal time. Currently, all-digital feedback clock recovery architectures are widely used due to their simplicity and stability. However, traditional all-digital schemes operate at twice the sampling rate, and their core components—the digital interpolation filter (DIF) and the timing phase error detector (TPED)—face the risk of failure under baud rate sampling conditions.
[0004] Specifically, traditional linear or piecewise parabolic interpolation filters cause severe bandwidth limitation during baud rate sampling, leading to system performance degradation. While using sinc function interpolation filters can improve bandwidth, their computational complexity is extremely high, making them impractical. To address this, existing technologies propose using a hybrid analog-digital architecture to circumvent the use of digital interpolation filters, but this architecture introduces problems such as large feedback delays and high hardware complexity. On the other hand, the clock component of traditional power-type Gardner timing phase error detectors disappears under baud rate sampling, making it impossible to accurately estimate timing phase errors. Some existing timing phase error detectors suitable for baud rate sampling, such as sign-based Mueller and Müller detectors or sign-and-absolute-value detectors, while functional, exhibit poor timing jitter performance.
[0005] In summary, existing technologies struggle to simultaneously achieve low power consumption, low cost, low jitter, and high precision in fully digital clock recovery at baud rate sampling. Therefore, a new technical solution is urgently needed to address these challenges. Summary of the Invention
[0006] This invention proposes a fully digital clock recovery method and system at baud rate sampling rate to solve the problems existing in the prior art.
[0007] To achieve the above objectives, the present invention provides a fully digital clock recovery method at a baud rate sampling rate, comprising the following steps:
[0008] The input baud rate sampled signal sequence is divided into blocks to form overlapping data blocks;
[0009] Perform a finite-field forward transform on the overlapping data blocks to obtain the transformed data blocks;
[0010] Perform a finite field filtering operation on the transformed data block and the currently used tap coefficient vector;
[0011] The result of the finite field filtering operation is subjected to an inverse finite field transform to obtain the processed time-domain data block.
[0012] The processed time-domain data block is then processed to generate a clock-recovered output signal.
[0013] Calculate the timing phase error based on the output signal after the clock is restored;
[0014] The timing phase error is filtered to generate phase control information;
[0015] Based on the phase control information, determine and update the currently used tap coefficient vector.
[0016] Optionally, the calculation of the timing phase error includes:
[0017] Perform conjugation and modulus operations on the output signal;
[0018] Perform complex sign function operations on the output signal;
[0019] The timing phase error is obtained by combining the results of taking the conjugate, taking the modulus, and performing complex sign function operations.
[0020] Optionally, determining and updating the currently used tap coefficient vector includes:
[0021] Using the phase control information as an index, the corresponding tap coefficient vector is read from a pre-stored lookup table to update the currently used tap coefficient vector.
[0022] Optionally, the output processing of the processed time-domain data block includes: discarding some sampling points at both ends of the time-domain data block, and using the remaining sampling points as the output signal after clock recovery.
[0023] Optionally, the forward finite field transform and the inverse finite field transform are the Fermat number transform and the inverse Fermat number transform, respectively.
[0024] Optionally, the calculation expression for the tap coefficient vector is:
[0025] ;
[0026] ;
[0027] ;
[0028] In the formula, Represents the intermediate frequency domain coefficient vector. This represents the interpolation decimal interval after quantization. represent bit width size, Represents the frequency index vector. The symbol represents the sampling period, and exp(·) represents performing an exponential function operation on the operands within the parentheses. Representing the intermediate time-domain coefficient vector, IFFT(·) indicates performing an inverse Fourier transform on the operands within the parentheses, and Q(A, B) indicates performing a quantization operation on operand A within the parentheses according to the bit width B. The value represents the quantization bit width of h, FNT(·) indicates that the operands within the parentheses are subjected to Fermat number transformation, and j represents the imaginary unit.
[0029] Optionally, the generation of phase control information includes:
[0030] The timing phase error is filtered using a loop filter;
[0031] Based on the filtered results, phase control information is generated by a numerically controlled oscillator.
[0032] Optionally, the step of dividing the input baud rate sampling signal sequence into blocks to form overlapping data blocks specifically includes:
[0033] The sampling points of the input signal sequence are adjusted according to the base point index indicated by the phase control information;
[0034] The adjusted signal sequence is divided into blocks so that adjacent data blocks have overlapping sampling points.
[0035] This invention also provides a fully digital clock recovery system at a baud rate sampling rate for implementing the method, comprising a main processing module and a coefficient control module:
[0036] The main path processing module includes:
[0037] The block unit is configured to divide the input baud rate sampled signal sequence into blocks to form overlapping data blocks;
[0038] A finite-field forward transform unit is configured to perform a finite-field forward transform on the overlapping data blocks to obtain the transformed data blocks.
[0039] A finite field filtering unit is configured to perform finite field filtering operations on the transformed data block and the currently used tap coefficient vector.
[0040] The finite-domain inverse transform unit is configured to perform a finite-domain inverse transform on the result of the finite-domain filtering operation to obtain the processed time-domain data block.
[0041] An output processing unit is configured to perform output processing on the processed time-domain data block to generate a clock-recovered output signal;
[0042] The coefficient control module includes:
[0043] A timing error detection unit is configured to calculate the timing phase error based on the output signal after the clock is recovered.
[0044] A filter control unit is configured to filter the timing phase error and generate phase control information.
[0045] The coefficient update unit is configured to determine and update the currently used tap coefficient vector based on the phase control information, and provide it to the finite field filtering unit.
[0046] Optionally, the finite field forward transform unit and the finite field inverse transform unit are respectively a Fermat number transformer and an inverse Fermat number transformer; the coefficient update unit includes a lookup table storing tap coefficient vectors.
[0047] Compared with the prior art, the present invention has the following advantages and technical effects:
[0048] This invention successfully achieves fully digital clock recovery at baud rate sampling through a collaborative design of highly nonlinear timing phase error detection and finite-domain fast convolutional filtering, completely eliminating the reliance on high-power, high-latency hybrid analog-to-digital architectures. The proposed scheme achieves bandwidth and phase modulation performance comparable to high-complexity sinc interpolation filters with extremely low computational complexity. Simultaneously, high-precision timing error detection effectively enhances the strength of clock components, significantly reducing timing jitter. Ultimately, this invention comprehensively achieves high-precision, low-jitter, low-complexity, and low-latency clock recovery, providing key technical support for high-speed, low-power optical fiber communication systems. Attached Figure Description
[0049] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0050] Figure 1 This is a system structure diagram of an embodiment of the present invention;
[0051] Figure 2 The clock component spectrum of the power-type Gardner timing error detector (TPED) in this embodiment of the invention is shown in (a) and (b) is shown in the spectrum under double sampling.
[0052] Figure 3 The following is a comparison of the clock component spectra of different timing error detectors (TPEDs) under baud rate sampling in embodiments of the present invention, wherein (a) represents the spectrum of MM-signed-TPED, (b) represents the spectrum of ABS-signed-TPED, and (c) represents the spectrum of the highly nonlinear TPED of the present invention.
[0053] Figure 4 The clock performance comparison diagrams of the embodiments of the present invention are shown, where (a) represents the clock component-local frequency offset diagram and (b) represents the clock jitter-local frequency offset diagram.
[0054] Figure 5 The following is a performance comparison chart of the clock recovery method proposed in the embodiments of the present invention, wherein (a) represents a comparison chart of the amplitude-frequency response of the proposed FF-DIF and the sinc function DIF, (b) represents a comparison chart of the BER-OSNR curves of clock recovery systems based on different DIFs, (c) represents a comparison chart of the computational complexity of clock recovery systems based on different DIFs, and (d) represents a convergence curve. Detailed Implementation
[0055] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0056] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.
[0057] Example 1
[0058] This embodiment provides a method for recovering a fully digital clock at a baud rate sampling rate, including the following steps:
[0059] The input baud rate sampled signal sequence is divided into blocks to form overlapping data blocks;
[0060] Perform a finite-field forward transform on the overlapping data blocks to obtain the transformed data blocks;
[0061] Perform a finite field filtering operation on the transformed data block and the currently used tap coefficient vector;
[0062] The result of the finite field filtering operation is subjected to an inverse finite field transform to obtain the processed time-domain data block.
[0063] The processed time-domain data block is then processed to generate a clock-recovered output signal.
[0064] Calculate the timing phase error based on the output signal after the clock is restored;
[0065] The timing phase error is filtered to generate phase control information;
[0066] Based on the phase control information, determine and update the currently used tap coefficient vector.
[0067] Furthermore, calculating the timing phase error includes: performing conjugation and modulus operations on the output signal; performing complex sign function operations on the output signal; and combining the results of the conjugation, modulus, and complex sign function operations to obtain the timing phase error.
[0068] Furthermore, determining and updating the currently used tap coefficient vector includes: using phase control information as an index, reading the corresponding tap coefficient vector from a pre-stored lookup table to update the currently used tap coefficient vector.
[0069] Furthermore, the output processing of the processed time-domain data block includes: discarding some sampling points at both ends of the time-domain data block, and using the remaining sampling points as the output signal after clock recovery.
[0070] The algorithm will be explained in detail below:
[0071] In this embodiment, the method is based on highly nonlinear TPED and finite field DIF (FF-DIF): firstly, the former is used to improve the detection accuracy of TPE under baud rate sampling and reduce clock jitter; then, the latter is used to adjust the sampling clock phase, and with the help of fast convolution operation in the finite field, the same bandwidth and clock phase adjustment performance as the traditional large tap sinc function interpolation filter is achieved with low computational complexity.
[0072] The described fully digital clock recovery method and system at a baud rate sampling rate comprises two parts: a main path and a bypass (feedback path). Considering polarization multiplexed signals, each polarization signal in the main path includes two overlapping block operations, two Fermat number transforms (FNTs), two point-by-point real number multiplications, two inverse Fermat number transforms (IFNTs), and two drop-point operations. The bypass path includes one highly nonlinear TPED operation, one loop filter (LF) operation, one numerically controlled oscillator (NCO) operation, and one lookup table (LUT) operation.
[0073] The formula for calculating highly nonlinear TPED is as follows:
[0074] (1)
[0075] Where a represents the input complex signal sequence in the time domain, and k represents the sequence index. Represents the length of the input signal sequence, (·) * Re represents taking the conjugate of the operands within the parentheses, |·| represents taking the modulus of the operands within the parentheses, and Re(·) represents taking the real part of the operands within the parentheses. csign(c) = sign[Re(c)] + j·sign[Im(c)] represents the complex sign function, indicating that the sign operation is performed on the real and imaginary parts of the complex number c.
[0076] Tap coefficient vector of N-point FF-DIF participating in point-by-point multiplication The generation method is as follows:
[0077] (2)
[0078] (3)
[0079] (4)
[0080] in Represents the intermediate frequency domain coefficient vector. This represents the interpolation decimal interval after quantization. represent bit width size, Represents the frequency index vector. The period represents the sampling symbol, and exp(·) represents performing an exponential function operation on the operands within the parentheses. Representing the intermediate time-domain coefficient vector, IFFT(·) indicates performing an inverse Fourier transform on the operands within the parentheses, and Q(A,B) indicates performing a quantization operation on the operand A within the parentheses according to the bit width B, where A and B are used as references. `h` represents the quantization bit width. `j` represents the imaginary unit. `FNT(·)` indicates performing an FNT operation on the operands within the parentheses, where the modulus of the transformation is set to 0. (where p is an odd number and b is a power of 2). The FNT only includes shift and addition operations, eliminating multiplication operations, resulting in very low computational complexity. Due to the properties of the FNT, the maximum transformation lengths supported by one-dimensional and two-dimensional FNTs are 4b and 8b, respectively. 2 Quantitative Each value within the range corresponds to a set of values. Therefore, it can constitute a For indexing, with The output LUT has a dimension size of . The LUT is generated offline and will not participate in the actual communication process, meaning that formula (2-4) will not introduce additional DSP computational complexity.
[0081] This embodiment also provides a fully digital clock recovery system under baud rate sampling rate, including a main processing module and a coefficient control module:
[0082] The main path processing module includes:
[0083] The block unit is configured to divide the input baud rate sampled signal sequence into blocks to form overlapping data blocks;
[0084] A finite-field forward transform unit is configured to perform a finite-field forward transform on the overlapping data blocks to obtain the transformed data blocks.
[0085] A finite field filtering unit is configured to perform finite field filtering operations on the transformed data block and the currently used tap coefficient vector.
[0086] The finite-domain inverse transform unit is configured to perform a finite-domain inverse transform on the result of the finite-domain filtering operation to obtain the processed time-domain data block.
[0087] An output processing unit is configured to perform output processing on the processed time-domain data block to generate a clock-recovered output signal;
[0088] The coefficient control module includes:
[0089] A timing error detection unit is configured to calculate the timing phase error based on the output signal after the clock is recovered.
[0090] A filter control unit is configured to filter the timing phase error and generate phase control information.
[0091] The coefficient update unit is configured to determine and update the currently used tap coefficient vector based on the phase control information, and provide it to the finite field filtering unit.
[0092] The following explanation uses specific components as examples:
[0093] like Figure 1 As shown, only a single X-polarized signal is displayed; the Y-polarized signal is the same. The main processing module includes two FNT operators 1, two point-by-point real multiplier operators 2, two IFNT operators 3, and two drop-point modules 4. The coefficient control module includes a high nonlinear TPED operator 5, an LF operator 6, an NCO operator 7, and a LUT lookup module 8.
[0094] The specific operation process of this system is as follows:
[0095] The I-channel and Q-channel data streams of the input baud rate sampled X-polarized signal are first indexed by the base point of the NCO output. Control, when It will output one sampling point in advance. The output is delayed by one sampling point. The data stream is directly output. After determining the base point index, the data stream is divided into two data blocks of length N. Each data block overlaps with the data blocks of the two adjacent clock cycles by Md sampling points. The two output data blocks are transformed to the finite domain by FNT and then multiplied by the real coefficient vector of FF-DIF. The result of the multiplication is returned to the time domain by IFNT and then discarded by Md / 2 sampling points on both sides. The remaining N-Md sampling points of the XI and XQ channels are used as two time-domain outputs of the CR module, and also synthesized into N-Md complex numbers for calculating TPE. The obtained TPE is filtered for phase noise by LF and then calculated by NCO. and . Using the LUT as an index, a corresponding set of N-point vectors is found, which is used for setting the FF-DIF tap coefficients of both XI and XQ paths.
[0096] exist Figure 2 Images (a) and (b) show the clock component spectra of a power-mode Gardner TPED at double sampling and baud rate sampling, respectively. The transmitted signal is a 120 GBaud dual-polarized Nyquist signal with a roll-off factor of [missing information]. Local oscillator frequency deviation The horizontal axis represents the frequency normalized to the signal baud rate, and the vertical axis is normalized to the value at the center zero frequency position. It can be seen that the power-type Gardner's TPED has a high clock component (≈32 dB) at double sampling, but at baud rate sampling, the clock component of the power-type Gardner's TPED disappears, and TPE estimation fails.
[0097] Figure 3Images (a)-(c) show the clock component spectra of MM-signed-TPED, ABS-signed-TPED, and the nonlinear TPED improved by this method at baud rate sampling, respectively. The transmitted signal is a 120 GBaud dual-polarized Nyquist signal with a roll-off factor of [missing information]. Local oscillator frequency deviation The horizontal axis represents the frequency normalized to the signal baud rate, and the vertical axis is normalized to the value at the center zero frequency position. It can be seen that since these TPEDs are proposed for baud rate sampling, the clock component has not disappeared. However, due to the more robust nonlinear computation employed in the proposed high-nonlinear TPED, it exhibits a higher clock component compared to the other two proposed TPEDs.
[0098] Figure 4 Figures (a) and (b) show the clock components and clock jitter of MM-signed-TPED, ABS-signed-TPED, and the proposed high-nonlinearity TPED at different local oscillator frequency offsets under baud rate sampling conditions. It can be seen that the proposed high-nonlinearity TPED exhibits higher clock components and lower clock jitter compared to MM-signed-TPED and ABS-signed-TPED under local oscillator frequency offsets within 2 GHz. Therefore, the proposed method possesses higher TPE detection accuracy and lower clock jitter performance.
[0099] Figure 5 In the diagram, (a) represents the amplitude-frequency response of the sinc function DIF and the proposed FF-DIF when TPE=0.5. It can be seen that the proposed FF-DIF has bandwidth performance very close to that of the sinc function DIF.
[0100] Figure 5 In Figure (b), the curves showing the change in BER relative to OSNR are obtained by using the sinc function DIF for temporal convolution and the proposed FF-DIF for fast convolution. The curves showing the change in bit error rate (BER) relative to optical signal-to-noise ratio (OSNR) are obtained by using the sinc function DIF for temporal convolution and the proposed FF-DIF for fast convolution, where the sampling clock error (SCO) is set to 100 ppm and the bit width of the input signal quantization is 6. The TPED used in all cases is the proposed high nonlinear TPED. The number of taps and the bit width after quantization in the sinc function DIF are 131 and 10, respectively. In the proposed FF-DIF, Using two-dimensional FNT / IFNT, , Overlapping drop size . Figure 5In the figure, (d) represents the convergence curves of the CR method based on sinc function DIF and the proposed FF-DIF method when OSNR=26 dB. It can be seen that the proposed method has the same clock phase modulation performance as the method based on sinc function DIF.
[0101] Figure 5 In the figure, (c) represents a comparison of the computational complexity of the CR method based on the sinc function DIF and the CR method based on the proposed FF-DIF, where the parameter configurations used are different from those of the proposed FF-DIF method. Figure 5 The same as (b) in the above, since the resource consumption of multiplication operation is much greater than that of addition operation, the computational complexity is calculated according to the formula CC≈kw0w1R. Where k represents the scaling factor, w0 and w1 represent the bit width of the two multipliers involved in the multiplication operation, and R represents the number of real multiplications required to output a polarization symbol. For the CR method based on sinc function DIF, R=2Nt (Nt is the number of taps of sinc function DIF). For the proposed CR method based on FF-DIF, R=2τN / (N-Md), where τ equals 1 (2) for one-dimensional (two-dimensional) FNT. Figure 5 In section (c), the computational complexity is normalized based on the maximum value. It can be seen that the proposed method simplifies the computational complexity by approximately 88.8% compared to the method based on the sinc function DIF.
[0102] In summary, this invention eliminates the dependence of baud rate sampling clock recovery methods on mixed analog-digital architectures, effectively reduces feedback delay, and improves the tracking speed and accuracy of clock recovery, making it a promising candidate for application in fiber optic communication systems.
[0103] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method of all-digital clock recovery at baud sampling rate, characterized in that, The method comprises the following steps: performing block processing on an input baud rate sample signal sequence to form overlapping data blocks; performing finite field forward transformation on the overlapping data blocks to obtain transformed data blocks; performing finite field filtering operation on the transformed data blocks and a currently used tap coefficient vector; performing finite field inverse transformation on the result of the finite field filtering operation to obtain processed time domain data blocks; performing output processing on the processed time domain data blocks to generate an output signal after clock recovery; calculating a timing phase error according to the output signal after clock recovery; performing filtering processing on the timing phase error to generate phase control information; determining and updating the currently used tap coefficient vector according to the phase control information.
2. The method of claim 1, wherein, The calculation of the timing phase error comprises: performing conjugate taking and modulus value operation on the output signal; performing complex sign function operation on the output signal; performing combination calculation according to the results of the conjugate taking, modulus value and complex sign function operation to obtain the timing phase error.
3. The method of claim 1, wherein, The determination and update of the currently used tap coefficient vector comprises: reading a corresponding tap coefficient vector from a pre-stored lookup table with the phase control information as an index to update the currently used tap coefficient vector.
4. The method of claim 1, wherein, The output processing on the processed time domain data blocks comprises: discarding the sampling points at both ends of the time domain data blocks and taking the remaining sampling points as the output signal after clock recovery.
5. The method of claim 1, wherein, The finite field forward transformation and the finite field inverse transformation are Fermat number transformation and inverse Fermat number transformation respectively.
6. The method of claim 1, wherein, The calculation expression of the tap coefficient vector is: ； ； ； wherein, represents an intermediate frequency-domain coefficient vector, represents a quantized interpolation fractional interval, represents a bit width size of h, represents a frequency index vector, represents a sampling symbol period, exp(·) represents an exponential function operation on an operand in the parentheses, represents an intermediate time-domain coefficient vector, IFFT(·) represents an inverse Fourier transform operation on an operand in the parentheses, Q(A, B) represents a quantization operation on an operand A according to a bit width B, represents a quantization bit width size of h, FNT(·) represents a Fermat number transform operation on an operand in the parentheses, and j represents an imaginary unit.
7. The method of claim 1, wherein, The generation of the phase control information comprises: filtering the timing phase error using a loop filter; generating the phase control information through a digital controlled oscillator according to the filtered result.
8. The method of claim 1, wherein, The block processing on the input baud rate sample signal sequence to form overlapping data blocks specifically comprises: adjusting the sampling points of the input signal sequence according to a base point index indicated by the phase control information; performing block processing on the adjusted signal sequence so that the adjacent data blocks have overlapping sampling points.
9. A fully digital clock recovery system at a baud rate sampling rate for implementing the method of any one of claims 1 to 8, characterized in that, The method comprises a main path processing module and a coefficient control module. The main path processing module comprises: a block unit configured to perform block processing on an input baud rate sample signal sequence to form overlapping data blocks; a finite field forward transformation unit configured to perform finite field forward transformation on the overlapping data blocks to obtain transformed data blocks; a finite field filtering unit configured to perform finite field filtering operation on the transformed data blocks and a currently used tap coefficient vector; a finite field inverse transformation unit configured to perform finite field inverse transformation on the result of the finite field filtering operation to obtain processed time domain data blocks; an output processing unit configured to perform output processing on the processed time domain data blocks to generate an output signal after clock recovery. The coefficient control module comprises: a timing error detection unit configured to calculate a timing phase error according to the output signal after clock recovery; a filter control unit configured to filter the timing phase error to generate phase control information; a coefficient update unit configured to determine and update the current used tap coefficient vector according to the phase control information and provide the finite field filter unit.
10. The system of claim 9, wherein, The finite field forward transform unit and the finite field inverse transform unit are Fermat number transformer and inverse Fermat number transformer respectively; and the coefficient update unit includes a look-up table storing tap coefficient vector.