Digital transmitter, communication device and radio frequency signal generation method

Abstract

The embodiment of the invention discloses a digital transmitter. The digital transmitter comprises a digital front-end circuit and a radio frequency circuit, the digital front-end circuit is used for receiving the fundamental frequency signal and generating a phase signal, a first amplitude signal and a second amplitude signal aiming at the fundamental frequency signal, and the second amplitude signal is orthogonal to the first amplitude signal; the radio frequency circuit is used for generating a first local oscillator signal and a second local oscillator signal aiming at the phase signal, mixing the first local oscillator signal with the first amplitude signal to generate a first radio frequency signal, mixing the second local oscillator signal with the second amplitude signal to generate a second radio frequency signal, and superposing the first radio frequency signal and the second radio frequency signal to generate a second radio frequency signal; and generating a target radio frequency signal, the first local oscillator signal and the second local oscillator signal being orthogonal. According to the digital transmitter provided by the embodiment of the invention, the hardware cost and the operation power consumption can be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of radio frequency technology, and in particular to a digital transmitter, a communication device, and a radio frequency signal generation method. BACKGROUND

[0002] As an important component in a communication device, a transmitter converts a radio frequency signal capable of being transmitted through an antenna by modulating and up-converting a baseband signal. Compared with a traditional quadrature transmitter, a digital transmitter (DTX) has obvious energy efficiency advantages and becomes a mainstream direction in short-range communication such as wifi, Bluetooth, Internet of Things, and the like, which has high integration and low cost.

[0003] In an existing digital transmitter, a received baseband signal is usually converted into a polar coordinate signal including an amplitude modulation signal and a phase modulation signal. However, the amplitude modulation signal usually carries rich high-order harmonic energy. After the amplitude modulation signal is mixed with a local oscillator signal, the high-order harmonic energy is mixed into a frequency range near the local oscillator signal to become aliasing noise, which causes the transmitter spectrum to deteriorate and interfere with adjacent channels. In the prior art, in order to improve the communication quality of the digital transmitter, a complex noise elimination algorithm is usually used in the digital transmitter to eliminate the aliasing noise. The complex noise elimination algorithm increases the chip area and power consumption of the digital transmitter, thereby increasing the cost of the digital transmitter. SUMMARY

[0004] The digital transmitter, the communication device, and the radio frequency signal generation method provided by the embodiments of the present application can reduce the cost of the digital transmitter. To achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, the embodiments of the present application provide a digital transmitter, which includes a digital front-end circuit and a radio frequency circuit. The digital front-end circuit is configured to receive a baseband signal and generate a phase signal, a first amplitude signal, and a second amplitude signal corresponding to the baseband signal, wherein the second amplitude signal is orthogonal to the first amplitude signal. The radio frequency circuit is configured to generate a first local oscillator signal and a second local oscillator signal corresponding to the phase signal, mix the first local oscillator signal with the first amplitude signal to generate a first radio frequency signal, mix the second local oscillator signal with the second amplitude signal to generate a second radio frequency signal, and superimpose the first radio frequency signal and the second radio frequency signal to generate a target radio frequency signal, wherein the first local oscillator signal and the second local oscillator signal are orthogonal.

[0006] In the embodiment of the present application, the digital front-end circuit can first convert the baseband signal into a polar coordinate signal including a phase signal and a first amplitude signal, and then perform a first-order differential operation on the first amplitude signal to generate a second amplitude signal. Since the first amplitude signal is obtained by converting the baseband signal into a polar coordinate signal, the first amplitude signal usually includes high-order harmonic energy (i.e., includes a noise signal generated by the high-order harmonic energy), which leads to an error between the first amplitude signal and an ideal signal, and the error is positively correlated with the change amount of the first amplitude signal, that is, when the error increases positively, the change amount of the first amplitude signal is a positive value, and when the error increases reversely, the change amount of the first amplitude signal is a negative value.

[0007] The digital transmitter provided by the embodiment of the present application sets the digital front-end circuit and the radio frequency circuit, generates the first amplitude signal and the second amplitude signal which are orthogonal to each other by using the digital front-end circuit, simulates the error signal by using the second amplitude signal, then separately modulates the first amplitude signal and the second amplitude signal to generate the first radio frequency signal and the second radio frequency signal, and then superimposes the first radio frequency signal and the second radio frequency signal, compensates the first radio frequency signal by using the second radio frequency signal to eliminate the aliasing noise in the radio frequency signal to be transmitted. Therefore, compared with the prior art, the digital transmitter provided by the embodiment of the present application can generate the second amplitude signal (for example, by performing a differential operation on the first amplitude signal) without setting a complex correction algorithm, so that the hardware cost of the digital transmitter can be reduced. In addition, compared with the prior art, the digital front-end circuit of the digital transmitter provided by the embodiment of the present application does not need to control the zero-crossing time of the rising edge and the falling edge of the local oscillator signal, the amplitude signal generated by the digital front-end circuit is decoupled from the local oscillator signal generated by the radio frequency circuit, and the clock frequency of the digital front-end circuit can be the same as the clock frequency of the radio frequency circuit, so that the power consumption of the digital front-end circuit can be reduced. Therefore, the digital transmitter provided by the embodiment of the present application can reduce the high hardware cost and the operating power consumption.

[0008] Based on the first aspect, in a possible implementation manner, the radio frequency circuit can include a frequency synthesizer, a first radio frequency digital-to-analog converter, a second radio frequency digital-to-analog converter, and an adder; the first radio frequency digital-to-analog converter is coupled between a first output end of the frequency synthesizer and a first input end of the adder; the second radio frequency digital-to-analog converter is coupled between a second output end of the frequency synthesizer and a second input end of the adder; the frequency synthesizer, the first radio frequency digital-to-analog converter, and the second radio frequency digital-to-analog converter are coupled with the digital front-end circuit.

[0009] The frequency synthesizer receives the phase signal from the digital front-end circuit, generates a first local oscillator signal and a second local oscillator signal for the phase signal; the first radio frequency digital-to-analog converter receives a first amplitude signal from the digital front-end circuit, and is used for mixing the first local oscillator signal and the first amplitude signal to generate a first radio frequency signal; the second radio frequency digital-to-analog converter receives a second amplitude signal from the digital front-end circuit, and is used for mixing the second local oscillator signal and the second amplitude signal to generate a second radio frequency signal; and the adder is used for superimposing the first radio frequency signal and the second radio frequency signal to generate a target radio frequency signal.

[0010] Based on the first aspect, the structure of the frequency synthesizer can be implemented in multiple ways.

[0011] In a first way, the frequency synthesizer includes a phase-locked loop and a frequency divider, an input end of the frequency divider is coupled to an output end of the phase-locked loop; a first output end of the frequency divider is coupled to an input end of the first radio frequency digital-to-analog converter, and a second output end of the frequency divider is coupled to an input end of the second radio frequency digital-to-analog converter. In this implementation way, the input end of the phase-locked loop can be coupled to the digital front-end circuit to receive the phase signal from the digital front-end circuit, and then modulate the phase signal to generate an initial local oscillator signal, and transmit the initial local oscillator signal to the frequency divider; the frequency divider can perform frequency division processing on the initial local oscillator signal to generate the first local oscillator signal and the second local oscillator signal. The frequency division ratio of the frequency divider may, for example, be 1 / 2, so that the clock frequency of the initial local oscillator signal can be twice the frequency of the first local oscillator signal (or the second local oscillator signal).

[0012] In a second way, in addition to the phase-locked loop and the frequency divider, the frequency synthesizer can also include a digital time converter. The digital time converter is coupled between the phase-locked loop and the frequency divider. Based on this structure, the output end of the phase-locked loop is coupled to a first input end of the digital time converter, a second input end of the digital time converter is coupled to the digital front-end circuit, an output end of the digital time converter is coupled to an input end of the frequency divider, a first output end of the frequency divider is coupled to an input end of the first radio frequency digital-to-analog converter, and a second output end of the frequency divider is coupled to an input end of the second radio frequency digital-to-analog converter. In this way, the phase-locked loop is used to output a clock signal with a fixed frequency, which may, for example, be twice the frequency of the first local oscillator signal (or the second local oscillator signal). The digital time converter receives the phase signal from the digital front-end circuit, and then modulates the phase signal based on the clock signal input by the phase-locked loop to generate an initial local oscillator signal, and transmits the initial local oscillator signal to the frequency divider; the frequency divider can perform frequency division processing on the initial local oscillator signal to generate the first local oscillator signal and the second local oscillator signal. The frequency division ratio of the frequency divider may, for example, be 1 / 2.

[0013] In method three, the frequency synthesizer may include a phase-locked loop (PLL) and a polyphase filter. The PLL is coupled between the digital front-end circuit and the input of the polyphase filter. The first output of the polyphase filter is coupled to the input of a first RF digital-to-analog converter (DAC), and the second output of the polyphase filter is coupled to the input of a second RF DAC. In this implementation, the input of the PLL can be coupled to the digital front-end circuit to receive a phase signal, which is then modulated to generate an initial local oscillator (LOO) signal. This LOO signal is then transmitted to the polyphase filter. The polyphase filter can perform orthogonal processing on the LOO signal while maintaining its frequency, generating a first LOO signal and a second LOO signal that are orthogonal to each other. The frequency of the initial LOO signal is the same as the frequency of the first LO signal (or the second LO signal).

[0014] The digital front-end circuit provided in this application embodiment can be implemented in various ways. In one possible implementation, the digital front-end circuit can be a processor or processor chip that processes the baseband signal by executing a software program to generate the aforementioned phase signal, first amplitude signal, and second amplitude signal. In another possible implementation, the digital front-end circuit may include a coordinate rotation computer and an orthogonal amplitude compensation circuit; the coordinate rotation computer performs polar coordinate processing on the baseband signal to generate the first amplitude signal and the phase signal, wherein the baseband signal is an orthogonal signal and the phase signal is a polar coordinate signal; the orthogonal amplitude compensation circuit differentially processes the first amplitude signal to generate the second amplitude signal.

[0015] Secondly, embodiments of this application provide a communication device, which includes a baseband processor and a digital transmitter as described in any of the first aspects; the baseband processor is coupled to the digital transmitter, and the baseband processor is used to transmit baseband signals to the digital transmitter.

[0016] Based on the second aspect, in one possible implementation, the baseband processor includes a modem; the modem is coupled to the input of a digital front-end circuit, the modem being used to generate a baseband signal and transmit the baseband signal to the digital front-end circuit.

[0017] Based on the second aspect, in one possible implementation, the communication device also includes an antenna coupled to a digital transmitter, which is used to transmit target radio frequency signals through the antenna.

[0018] Thirdly, embodiments of this application provide a radio frequency (RF) signal generation method applied to a digital transmitter. The RF signal generation method includes: a digital front-end circuit in the digital transmitter receiving a baseband signal, processing the baseband signal to generate a phase signal, a first amplitude signal, and a second amplitude signal, and transmitting the phase signal, the first amplitude signal, and the second amplitude signal to an RF circuit. The first amplitude signal is a polarization signal obtained by polarization processing of the baseband signal, and the second amplitude signal is used to indicate the change in the first amplitude signal within a preset period, and the second amplitude signal and the first amplitude signal are orthogonal signals. The RF circuit in the digital transmitter generates a first local oscillator signal and a second local oscillator signal based on the phase signal, mixes the first local oscillator signal with the first amplitude signal to generate a first RF signal, mixes the second local oscillator signal with the second amplitude signal to generate a second RF signal, and superimposes the first RF signal and the second RF signal to generate a target RF signal, wherein the first local oscillator signal and the second local oscillator signal are orthogonal signals.

[0019] It should be understood that the second and third aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a digital transmitter structure in the prior art provided in the embodiments of this application;

[0021] Figure 2 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0022] Figure 3 This is a flowchart illustrating the operation of the digital transmitter provided in the embodiments of this application;

[0023] Figure 4A These are waveform diagrams of the amplitude signal and the ideal signal provided in the embodiments of this application;

[0024] Figure 4B This is a waveform diagram of the error signal and amplitude signal provided in the embodiments of this application;

[0025] Figure 5 This is a schematic diagram of a phased array provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of a digital transmitter provided in the application embodiment;

[0027] Figure 7 This is yet another structural schematic diagram of the digital transmitter provided in the embodiments of this application;

[0028] Figure 8 This is yet another structural schematic diagram of the digital transmitter provided in the embodiments of this application;

[0029] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0031] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0032] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0033] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0034] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0035] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0036] refer to Figure 1 , Figure 1 This is a schematic diagram of a digital transmitter structure in the prior art provided in the embodiments of this application. For example... Figure 1As shown, existing transmitter architectures typically include a Coordinate Rotation Digital Computer (CORDIC), a zero-crossing pre-distortion (ZCPD) module, a frequency synthesizer, and a radio frequency digital-to-analog converter (RFDAC). The digital transmitter is connected to a baseband processor. A pair of differential signals, I and Q, transmitted by the baseband processor are processed by the CORDIC to generate phase and amplitude signals corresponding to the digital transmitter. Typically, the signals generated by the CORDIC carry a significant amount of high-order harmonic energy (e.g., first and second harmonics). The zero-crossing pre-distortion module runs a correction algorithm to calculate aliasing noise in the signals generated by the CORDIC. Based on the aliasing noise, it determines the zero-crossing times of the rising and falling edges of the local oscillator signal, using the local oscillator signal to inversely compensate for the aliasing noise. Based on the determined times, a phase signal is generated and provided to the frequency synthesizer. Therefore, the frequency synthesizer generates a local oscillator signal based on the phase signal provided by the zero-crossing pre-distortion module and provides it to the RF digital-to-analog converter. Finally, the RF digital-to-analog converter mixes the local oscillator signal with the amplitude signal provided by the zero-crossing pre-distortion module to generate the RF signal to be transmitted.

[0037] like Figure 1 In the digital transmitter structure shown, the correction algorithm run by the zero-crossing pre-distortion module requires calculating the integral energy of the error signal, resulting in high algorithm complexity. Furthermore, the correction algorithm needs to adjust the zero-crossing times of the rising and falling edges of the local oscillator signal, and the clock frequency of the correction algorithm is much higher than the local oscillator signal frequency (e.g., twice the local oscillator signal frequency). In the prior art, the correction algorithm run by the zero-crossing pre-distortion module is quite complex. This overly complex algorithm increases the chip area occupied by the zero-crossing pre-distortion module, thus increasing its hardware overhead. Additionally, because the clock frequency of the correction algorithm is much higher than the local oscillator signal frequency, the zero-crossing pre-distortion module has high power consumption. In summary, it can be seen that the existing digital transmitter technology suffers from high hardware cost and high operating power consumption.

[0038] The digital transmitter provided in this application embodiment, by setting up a digital front-end circuit and a radio frequency (RF) circuit, generates a first amplitude signal and a second amplitude signal that are orthogonal to each other using the digital front-end circuit. The second amplitude signal is used to simulate an error signal. Then, the first and second amplitude signals are modulated separately to generate a first RF signal and a second RF signal. The first and second RF signals are then superimposed, and the second RF signal is used to compensate for the first RF signal, thereby eliminating aliasing noise in the RF signal to be transmitted. Therefore, compared with the prior art, the digital transmitter provided in this application embodiment can generate the second amplitude signal without setting a complex correction algorithm (e.g., by differential operation on the first amplitude signal), thus reducing the hardware overhead of the digital transmitter. Furthermore, compared with the prior art, the digital transmitter provided in this application embodiment, since the digital front-end circuit does not need to control the zero-crossing time of the rising and falling edges of the local oscillator signal, the amplitude signal generated by the digital front-end circuit is decoupled from the local oscillator signal generated by the RF circuit. The clock frequency of the digital front-end circuit and the clock frequency of the RF circuit can be the same, thereby reducing the power consumption of the digital front-end circuit. Therefore, the digital transmitter provided in this application embodiment can reduce high hardware costs and operating power consumption. The following describes... Figures 2 to 8 The embodiments shown herein provide a detailed description of the digital transmitter provided in this application.

[0039] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the communication device 100 provided in this application embodiment. The communication device 100 provided in this application embodiment can be applied to cellular network communication (e.g., 4G or 5G) scenarios, and also to short-range communication (e.g., WIFI or Bluetooth) scenarios, such as... Figure 2 The communication device 100 shown can be used in electronic devices. This electronic device can be, for example, a terminal device, including but not limited to: mobile phones, PCs, tablets, laptops, wearable devices (such as smartwatches, AR devices, VR devices), and terminal devices in smart homes (such as, but not limited to, smart lights, smart speakers, smart air conditioners, or smart refrigerators); the electronic device can also be a switch or router, etc. Figure 2As shown, the communication device 100 includes a baseband processor 11, a transceiver 10, and an antenna 12. The transceiver 10 may include a digital transmitter T and a digital receiver R. The baseband processor 11 is coupled to the digital transmitter T and digital receiver R in the transceiver 10, and the digital transmitter T and digital receiver R are also coupled to the antenna 12. The baseband processor 11 and the transceiver 10 may be electronic devices, or modules, chips, chipsets, circuit boards or components carrying chips or chipsets disposed within electronic devices. The chip or chipset or the circuit board carrying the chip or chipset can operate under necessary software driving. Subsequent embodiments are described using the communication device 100 as an example of the electronic device itself, but are not intended to limit the solution. The one or more processors may be integrated into one or more chips, which may be considered as a chipset. When the one or more processors are integrated into the same chip, the chip is also called a system-on-a-chip (SOC). In one possible implementation, the baseband processor 101 and the transceiver 10 may be integrated on the same chip, i.e., integrated on a SOC. In other implementations, the baseband processor 101 can be integrated on one chip, and the radio frequency transmitter 102 can be integrated on another chip.

[0040] The baseband processor 11 can be a standalone component or integrated into other digital logic devices, including but not limited to CPUs (Central Processing Units) or DSPs (Digital Signal Processors). Furthermore, the baseband processor 101 can also be other programmable logic devices, transistor logic devices, or discrete hardware components. The communication device 100 may also include one or more other components, such as a memory. The memory can be integrated on the same chip as the baseband processor 101 and the transceiver 10. The memory can be used to support the communication device 100 in executing stored program code and data. The baseband processor 11 processes the information to be transmitted, generating a baseband signal to be sent to the digital transmitter T in the transceiver 10. It should be noted that the information to be transmitted here can also be called useful information, that is, the information that the transmitting device hopes the signal receiving end will receive. This information can be, for example, information obtained from an information source, which may include, but is not limited to, other user equipment or server equipment; or, for example, information generated based on user operations on the electronic device. In one possible implementation, the baseband processor 11 may also include a modem for modulating the signal transmitted by the signal source, generating a baseband signal, and providing the baseband signal to the digital transmitter T.

[0041] The digital transmitter T may include a digital front-end circuit 01 and an radio frequency (RF) circuit 02. The digital front-end circuit 01 may be a digital logic device, including but not limited to a DSP or CPU. Furthermore, the digital front-end circuit 01 may also be a programmable logic device, a transistor logic device, or a discrete hardware component. In one possible implementation, when the baseband processor 11 and the transceiver 10 are integrated into the same chip, the digital front-end circuit 01 may share the same hardware as the baseband processor 11, but execute different signal processing logic. The digital transmitter T can generate RF signals by running software, hardware, or a combination of both. The RF signal generation method is described in reference [reference needed]. Figure 3 , Figure 3This paper illustrates a workflow of a radio frequency (RF) signal generation method provided in an embodiment of this application. The RF signal generation method includes the following steps: Step 301, the digital front-end circuit 01 processes the baseband signal sent by the baseband processor 11 to generate a phase signal phi, an amplitude signal amp_I, and an amplitude signal amp_Q, respectively, and then transmits the phase signal phi, amplitude signal amp_I, and amplitude signal amp_Q to the RF circuit 02. In this embodiment, the amplitude signal amp_Q is used to indicate the amount of change of the amplitude signal amp_I within a preset period. This preset period can be, for example, one period or two periods; this embodiment does not specifically limit this. For example, the amount of change of the amplitude signal amp_Q within the preset period can be the difference between the amplitude signal amp_I1 of the current period and the amplitude signal amp_I2 of the previous period, or the difference between the amplitude signal amp_I1 of the current period and the amplitude signal amp_I3 two periods ahead of the current period. The length of the preset period can be set according to the needs of the scenario; this embodiment does not specifically limit this. Furthermore, the amplitude signals amp_I and amp_Q are orthogonal signals, meaning that the phases of amp_I and amp_Q differ by 90 degrees, or by 1 / 4 period. In one possible implementation, the digital front-end circuit 01 can first convert the baseband signal into a polar coordinate signal including the phase signal phi and the amplitude signal amp_I, and then perform a differential operation on the amplitude signal amp_I to generate the amplitude signal amp_Q. In step 302, the RF circuit 02 can generate local oscillator signals LO1 and LO2 based on the phase signal phi, and mix the local oscillator signal LO1 with the amplitude signal amp_I to generate the RF signal F1. In step 303, the RF circuit 02 can also mix the local oscillator signal LO2 with the amplitude signal amp_I2 to generate the RF signal F2. Local oscillator signals LO1 and LO2 are orthogonal signals. The phase of local oscillator signal LO1 is the same as the amplitude signal amp_I, and the phase of local oscillator signal LO2 is the same as the amplitude signal amp_Q. In step 304, the radio frequency circuit 02 superimposes radio frequency signals F1 and F2 to generate the target radio frequency signal (i.e., the radio frequency signal to be transmitted), thus enabling the radio frequency circuit 02 to transmit the target radio frequency signal through antenna 12.

[0042] The receiver R can be a digital receiver or a quadrature receiver. This application embodiment does not specifically limit the receiver R; it is set based on the needs of the scenario. The receiver R receives signals from the antenna 12, amplifies the received RF signal, performs down-conversion processing, and then generates a baseband signal after filtering and analog-to-digital conversion, which is then provided to the baseband processor 11. Therefore, the receiver R can selectively include necessary components such as amplifiers, mixers, filters, local oscillators, or analog-to-digital converters.

[0043] Antenna 12 may include one or more. In one possible implementation, antenna 12 may be an antenna array, and digital transmitter T may be coupled to one or more antennas in antenna 12. Digital transmitter T may also modulate the target radio frequency signal onto one or more antennas for transmission. Receiver R may also be coupled to one or more antennas in antenna 12 to receive radio frequency signals from one or more antennas. Furthermore, in one possible implementation, digital transmitter T and receiver R may be coupled to the same antenna or to different antennas. This application embodiment does not impose specific limitations and the configuration is based on the needs of the scenario.

[0044] based on Figure 2 Please refer to the communication device 100 shown below. Figure 4A and Figure 4B , Figure 4A This is a waveform diagram of the amplitude signal amp_I and the ideal signal provided in the embodiments of this application; Figure 4B This is a waveform diagram of the error signal and amplitude signal amp_Q provided in the embodiments of this application. Figure 4A In the diagram, the solid line represents the waveform of the amplitude signal amp_I, and the dashed line represents the waveform of the ideal signal; Figure 4B In the diagram, the square wave signal represents the waveform of the amplitude signal amp_Q, and the triangular wave signal represents the waveform of the error signal. Figure 4A and Figure 4B In the graph, the horizontal axis represents normalized time (in nanoseconds), and the vertical axis represents amplitude. From... Figure 4A As can be seen, in the square wave waveform of the amplitude signal amp_I, the width of the square wave within the same period (e.g., the width of the square wave in the positive half-cycle or the negative half-cycle) is a fixed value (i.e., the same size); however, in the square wave signal of an ideal signal, the width of the square wave within the same period is not a fixed value (i.e., different sizes), but has a variable. For example, taking... Figure 4ATaking a period T1 as an example, in period T1, the square wave width of the amplitude signal amp_I in the forward period T11 is 290, while the square wave width of the ideal signal in the reverse period T11 increases from 290 to 299; in the reverse period T12, the square wave width of the amplitude signal amp_I is -285, while the square wave width of the ideal signal in the reverse period T12 decreases from -290 to -299. That is, there is an error between the amplitude signal amp_I and the ideal signal, and this error is caused by higher-order harmonic signal disturbances. Figure 4B In this context, the triangular wave signal is the error signal waveform between the amplitude signal amp_I and the ideal signal. Within the same period, the sum of the amplitude signal amp_I and the error signal is the ideal signal. Figure 4B In this context, the amplitude signal amp_Q is the difference between two adjacent periods of the amplitude signal amp_I. For example, the difference between the amplitude signal amp_I in period T21 and the amplitude signal in period T11 is... Figure 4B The high-level signal of the medium-amplitude signal amp_Q; the difference between the amplitude signal amp_I in period T22 and the signal in period T12 is... Figure 4B The low-level signal of the medium-amplitude signal amp_Q. From Figure 4B As can be seen, the direction of change of the amplitude signal amp_Q is consistent with the direction of change of the error signal. Figure 4B Taking period T1 as an example, in period T11, the amplitude signal amp_Q changes from low to high, and the error signal increases from -9 to 0, both showing a positive change. In period T12, the amplitude signal amp_Q changes from high to low, and the error signal changes from 0 to -9, both showing a negative change. That is to say, the change in amplitude signal amp_I (i.e., amplitude signal amp_Q) is positively correlated with the higher-order noise signal. When the higher-order noise signal increases positively, the change in amplitude signal amp_I (i.e., amplitude signal amp_Q) is positive; when the higher-order noise signal increases negatively, the change in amplitude signal amp_I (i.e., amplitude signal amp_Q) is negative. Therefore, the amplitude signal amp_Q can simulate the direction of change of the error signal. Furthermore, based on the magnitude of the error signal, the amplitude of amplitude signal amp_Q can be adjusted to modulate amplitude signal amp_Q and compensate for the error signal.

[0045] pass Figures 2 to 4B It can be seen that in existing technologies, through methods such as Figure 2The zero-crossing pre-distortion module shown uses a correction algorithm to compensate for the local oscillator signal. This typically requires calculating the integral energy of the error signal and determining the zero-crossing times of the rising and falling edges of the local oscillator signal, resulting in high algorithm complexity and a high clock frequency for the zero-crossing pre-distortion module. In contrast, the digital transmitter T provided in this embodiment uses digital front-end circuit 01 to generate amplitude signals amp_I and amp_Q. Amplitude signal amp_Q indicates the change in amplitude signal amp_I within a preset period. Since amplitude signal amp_Q can simulate the direction of error signal change, it is used to modulate an RF signal to compensate for the RF signal modulated by amplitude signal amp_I. This reduces the deviation between the actual and ideal signals caused by higher-order harmonic disturbances, thereby improving the accuracy of the transmitted signal. Since amplitude signal amp_Q can be calculated by the signal difference of amplitude signal amp_I within a preset period, it can be obtained using a simple algorithm. Therefore, compared with the prior art, the digital transmitter T provided in this application embodiment can generate the amplitude signal amp_Q without setting a complex correction algorithm, thereby reducing the hardware overhead of the digital transmitter. Furthermore, compared with the prior art, the digital transmitter T provided in this application embodiment, since the digital front-end circuit 01 does not need to control the zero-crossing time of the rising and falling edges of the local oscillator signal, the amplitude signal generated by the digital front-end circuit 01 is decoupled from the local oscillator signal generated by the radio frequency circuit 02. The clock frequency of the digital front-end circuit 01 and the clock frequency of the radio frequency circuit 02 can be the same, thereby reducing the power consumption of the digital front-end circuit 01. Thus, the digital transmitter T provided in this application embodiment can reduce high hardware costs and low operating power consumption.

[0046] based on Figure 2 The digital transmitter T shown in this embodiment is, in one possible implementation of this application, applicable to a phased array. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the phased array 200 provided in an embodiment of this application. The phased array 200 can be applied to... Figure 2 In the transceiver 10 shown. For example... Figure 5 As shown, the phased array 200 includes a digital front-end circuit 01, an RF circuit 02, a cross circuit 03, and multiple transmission channels. Each transmission channel may include a phase shifting circuit (e.g., a phase shifter) and a power amplifier circuit (e.g., a power amplifier). The phase shifting circuit and the power amplifier circuit in each transmission channel are coupled. Figure 5The diagram schematically illustrates four transmission channels, corresponding to four phase-shifting circuits 041, 042, 043, and 04N, and four power amplifier circuits 051, 052, 053, and 05N. It is understood that the number of phase-shifting and power amplifier circuits is illustrative and based on the needs of the scenario, and is not intended to limit the solution; for example, it may include more or fewer phase-shifting and power amplifier circuits. Figure 2 Similar to the digital transmitter T shown, the digital front-end circuit 01 is coupled to the radio frequency circuit 02, which in turn is coupled to the power divider circuit 03. The power divider circuit 03 includes multiple output terminals, which can be coupled one-to-one with multiple phase-shifting circuits. Additionally, the antenna 12 in the phased array 200 can include multiple sets of antennas, and each of the multiple power amplifier circuits is coupled one-to-one with each set of antennas in the antenna 12. Figure 5 The diagram schematically illustrates the coupling between power amplifier circuit 051 and antenna 12 (coupling 1), power amplifier circuit 052 and antenna 12 (coupling 2), power amplifier circuit 053 and antenna 12 (coupling 3), and power amplifier circuit 05N and antenna 12 (coupling N). When a phased array needs to point in a specific direction to achieve a specific beam, the signal from the radio frequency circuit can be phase-shifted using phase-shifting circuits in the phased array, thus obtaining a radiation pattern in that specific direction. When a phased array needs to dynamically cover multiple directions, it can achieve this through phase scanning. Since phased array systems require a large scanning angle, there are certain requirements for the phase-shifting accuracy and range of each phase-shifting circuit. For ease of system control, the phased array can optionally employ digital phase shifter technology. Each branch needs to adjust its phase within a phase-shifting range implemented by n bits by changing the digital control bits to achieve phase scanning. For example... Figure 5 In the phased array 200 shown, the digital front-end circuit 01 processes the baseband signal sent by the baseband processor 11, generating a phase signal phi, an amplitude signal amp_I, and an amplitude signal amp_Q, respectively. Then, the phase signal phi, the amplitude signal amp_I, and the amplitude signal amp_Q are transmitted to the radio frequency circuit 02, respectively. The radio frequency circuit 02 performs the following operations: Figure 1 The RF circuit 02 shown generates a target RF signal through similar steps and provides it to the power divider circuit 03. After the power divider circuit 03 performs power division processing on the target RF signal, it provides it to the phase shifting circuit in the corresponding transmission channel. The phase shifting circuit performs phase shift processing on the received signal and provides it to the power amplifier circuit. The power amplifier circuit amplifies the power of the received signal. Finally, the target RF signal generated by the RF circuit 02 is transmitted through multiple antennas in the antenna 12.

[0047] based on Figure 2 The communication device 100 shown and Figure 6The phased array 200 shown below is followed by a more detailed description of the structure of the digital transmitter T provided in the embodiments of this application. Please refer to... Figure 6 , Figure 6 This is a schematic diagram of the structure of a digital transmitter T provided in an embodiment of this application. For example... Figure 6 As shown, the digital front-end circuit 01 in the digital transmitter T may include a coordinate rotation digital computer (CORDIC) COR and a quadrature amplitude compensation circuit (QAC); the radio frequency circuit 02 includes a phase-locked loop (PLL), a frequency divider F, a radio frequency digital to analog converter (RFDAC) DAC1, a radio frequency digital to analog converter DAC2, and an adder A.

[0048] The input of the coordinate rotation computer (COR) is coupled to the baseband processor 11. The COR includes multiple outputs, one of which is coupled to the radio frequency (RF) circuit 02, and another output is coupled to the quadrature amplitude compensation circuit QAC. The COR receives a baseband signal from the baseband processor 11, which may include signal I and signal Q. Signal I and signal Q can be a pair of quadrature signals. The COR converts the received signals I and Q into polar coordinate signals represented by amplitude and phase, including a phase signal phi and an amplitude signal amp_I. The COR then transmits the phase signal phi to the RF circuit 02 and the amplitude signal amp_I to the quadrature amplitude compensation circuit QAC. The input of the quadrature amplitude compensation circuit QAC is coupled to one output of the COR, one output of the QAC is coupled to one input of the RF digital-to-analog converter DAC1, and the other output of the QAC is coupled to one input of the RF digital-to-analog converter DAC2. The quadrature amplitude compensation circuit QAC processes the amplitude signal amp_I to generate the amplitude signal amp_Q. The amplitude signal amp_Q indicates the change in amplitude signal amp_I between two adjacent periods. amp_Q can be obtained by differentiating the amplitude signals amp_I1 and amp_I2 between two adjacent periods. Furthermore, the amplitude signals amp_Q and amp_I are orthogonal. In one possible implementation, both amplitude signals amp_Q and amp_I are square wave signals. The quadrature amplitude compensation circuit QAC provides amplitude signal amp_I to RF digital-to-analog converter DAC1, and the quadrature amplitude compensation circuit QAC provides amplitude signal amp_Q to RF digital-to-analog converter DAC2. The coordinate rotation computer COR can be a processor or a programmable logic device; the quadrature amplitude compensation circuit QAC can also be a processor or a programmable logic device.

[0049] The input of the phase-locked loop (PLL) is coupled to one digital input of the coordinate rotating computer (COR), and the output of the PLL is coupled to the input of the frequency divider F. The PLL generates a local oscillator (LO) signal based on the phase signal phi provided by the COR, and then transmits the LO signal to the frequency divider F. The structure of the PLL provided in this embodiment can include, but is not limited to, charge pump PLLs, sampling PLLs, binary phase-detection PLLs, undersampled PLLs, or fully digital PLLs, etc., and this embodiment does not impose specific limitations. Furthermore, the phase modulation method of the PLL includes, but is not limited to, two-point modulation or single-point modulation. The frequency divider F includes two outputs, one of which is coupled to the radio frequency digital-to-analog converter (DAC1), and the other output is coupled to the radio frequency digital-to-analog converter (DAC2). The frequency divider F can be a two-way divider. The frequency divider F divides the LO signal by two to generate LO1 and LO2, where LO1 and LO2 are orthogonal signals. The output of RF digital-to-analog converter DAC1 is coupled to one of the inputs of adder A, and the output of RF digital-to-analog converter DAC2 is coupled to the other input of adder A. RF digital-to-analog converter DAC1 mixes the local oscillator signal LO1 sent by frequency divider F and the amplitude signal amp_I sent by quadrature amplitude module QAC to generate RF signal F1, and then sends RF signal F1 to adder A. RF digital-to-analog converter DAC2 mixes the local oscillator signal LO2 sent by frequency divider F and the amplitude signal amp_Q sent by quadrature amplitude module QAC to generate RF signal F2, and then sends RF signal F2 to adder A. In this embodiment, the structures of RF digital-to-analog converters DAC1 and DAC2 may include, but are not limited to: switched-capacitor RFDAC, current-mode RFDAC, or voltage-mode RFDAC. In other words, RF digital-to-analog converters DAC1 and DAC2 can perform frequency mixing modulation on voltage signals, current signals, and other types of signals. Adder A superimposes RF signals F1 and F2 to generate the target RF signal, which is then transmitted through antenna 12. In this embodiment, the superposition of RF signals F1 and F2 by adder A can include, but is not limited to, current signal superposition, voltage signal superposition, or superposition based on transformers or transmission lines, wherein the signal superposition method is determined based on the signal type modulated by RF digital-to-analog converters DAC1 and DAC2.

[0050] like Figure 6The digital transmitter T shown uses an orthogonal amplitude compensation circuit QAC to process the polarization amplitude signal, generating two orthogonal amplitude signals amp_I and amp_Q. Both amp_I and amp_Q are square wave signals. Amplitude signal amp_Q indicates the change in amplitude signal amp_I between two adjacent periods. The digital transmitter T also uses a frequency divider F and two RF digital-to-analog converters to modulate amplitude signals amp_I and amp_Q respectively. The modulated signals are then superimposed to compensate for amplitude signal amp_I using amplitude signal amp_Q. Figure 6 As can be seen from the digital transmitter T shown, the embodiments of this application can achieve compensation for aliasing noise energy through a relatively simple algorithm and fewer components. Compared with the prior art, it can reduce hardware costs and operating power consumption.

[0051] above Figure 6 In the digital transmitter T shown, the output of the coordinate rotation computer (COR) is coupled to the input of a phase-locked loop (PLL), transmitting a phase signal phi to the PLL, which then generates a local oscillator signal LO. In one possible implementation, the PLL can be used solely to generate the clock signal, with phase modulation achieved via a time-to-digital converter (DTC). (Reference) Figure 7 , Figure 7 This is another structural schematic diagram of the digital transmitter T provided in the embodiments of this application. Figure 7 The circuit structure of the digital front-end circuit 01 in the digital transmitter T shown is similar to... Figure 6 The digital front-end circuit shown is the same as 01; please refer to the following for details. Figure 6 The relevant descriptions will not be repeated here. (And...) Figure 6 The radio frequency circuit 02 shown is the same as that shown. Figure 7 The RF circuit 02 shown includes a phase-locked loop (PLL), a frequency divider F, an RF digital-to-analog converter (DAC1), an RF digital-to-analog converter (DAC2), and an adder A; and Figure 6 When the RF circuit 02 shown is different, Figure 7The RF circuit 02 shown also includes a time-to-digital converter (DTC), which is coupled between a phase-locked loop (PLL) and a frequency divider F. One output of the coordinate rotating computer (COR) is also coupled to the DTC. The PLL generates a clock signal at twice the frequency of the local oscillator signal and provides this clock signal to the DTC. The DTC can be implemented using a time delay or a phase difference. This embodiment does not specifically limit the implementation of the DTC; it is set according to the needs of the scenario. The DTC performs phase modulation based on the clock signal output from the PLL and the phase signal phi transmitted by the COR, generating a local oscillator signal LO which is provided to the frequency divider F. The connection relationships and functions between the frequency divider F, the RF digital-to-analog converters DAC1 and DAC2, and the adder A are described below. Figure 6 The frequency divider F, RF digital-to-analog converter DAC1, RF digital-to-analog converter DAC2, and adder A shown are the same; please refer to the following for details. Figure 6 The relevant descriptions will not be repeated here.

[0052] above Figure 6 and Figure 7 The digital transmitter T shown illustrates the use of a frequency divider F to divide the local oscillator signal LO. In one possible implementation, frequency division of the local oscillator signal LO can also be achieved using a polyphase filter (PPF). (See reference...) Figure 8 , Figure 8 This is another structural schematic diagram of the digital transmitter T provided in the embodiments of this application. Figure 8 The circuit structure of the digital front-end circuit 01 in the digital transmitter T shown is similar to... Figure 6 The digital front-end circuit shown is the same as 01; please refer to the following for details. Figure 6 The relevant descriptions will not be repeated here. Figure 8In the RF circuit 02 shown, the frequency divider F is no longer used; instead, a polyphase filter PPF is used. The input of the polyphase filter PPF is coupled to a phase-locked loop (PLL), one output of the polyphase filter PPF is coupled to an RF digital-to-analog converter (DAC1), and the other output is coupled to an RF DAC2. In this implementation, the PPL modulates the phase signal phi transmitted by the coordinate rotation computer (COR) to generate a local oscillator signal LO, which is then transmitted to the polyphase filter PPF. The polyphase filter PPF maintains the frequency of the local oscillator signal LO and converts it into two orthogonal local oscillator signals LO1 and LO2, which are provided to the RF DAC1 and DAC2, respectively. The frequency of the local oscillator signal LO generated by the PPL is the same as the frequencies of local oscillator signals LO1 and LO2. The connection relationships and functions between the RF DAC1, RF DAC2, and adder A are described below. Figure 6 The RF digital-to-analog converters DAC1 and DAC2 shown are identical to adder A; please refer to the following for details. Figure 6 The relevant descriptions will not be repeated here.

[0053] It should be noted that the above Figures 6 to 8 In the digital transmitter T shown, the description focuses on the digital front-end circuit 01, which includes a coordinate rotation computer (COR) and a quadrature amplitude compensation circuit (QAC). In other possible implementations, the digital front-end circuit 01 of the digital transmitter T can be a processor or an integrated chip, used to execute the algorithm functions performed by the coordinate rotation computer (COR) and the quadrature amplitude compensation circuit (QAC); the radio frequency circuit 02 of the digital transmitter T can be... Figures 6 to 8 The circuit shown in any embodiment.

[0054] exist Figure 2 The communication device 100 shown Figure 5 The phased array 200 shown, and Figures 6 to 8 Based on the structure of the digital transmitter T shown, this application also provides an electronic device 300, please refer to... Figure 9 The electronic device 300 may include a communication device 301, a memory 302, and a processor 303. The communication device here can be... Figure 2The communication device 100 shown is illustrated. It should be understood that the electronic device 300 here can specifically be a smartphone, computer, smartwatch, or other terminal device. Taking a smartphone as an example, the terminal device may specifically include a processor 303, a memory 302, a communication circuit, an antenna, and input / output devices. The processor 303 is mainly used to process communication protocols and communication data, control the entire smartphone, execute software programs, and process data from the software programs, such as supporting the smartphone to achieve various communication functions (e.g., making calls, sending messages, or instant messaging). The memory 302 is mainly used to store software programs and data. The communication circuit is mainly used for the conversion between baseband signals and radio frequency signals, and for processing radio frequency signals; the communication circuit includes the aforementioned phased array. The communication circuit is mainly used to transmit and receive radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are mainly used to receive user input data and output data to the user.

[0055] When the smartphone is powered on, the processor 303 can read the software program from the memory 302, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 303 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit then performs RF processing on the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the smartphone, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 303. The processor 303 converts the baseband signal back into data and processes the data.

[0056] Those skilled in the art will understand that, for ease of explanation, Figure 9 Only one memory 302 and one processor 303 are shown. In actual terminal devices, multiple processors 303 and multiple memories 302 may exist. The memory 302 may also be referred to as a storage medium or storage device, etc. It should be noted that the type of memory 302 is not limited in the embodiments of this application.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A digital transmitter, characterized by The digital front-end circuit and the radio frequency circuit are included. The digital front-end circuit is configured to receive a baseband signal, and generate a phase signal, a first amplitude signal and a second amplitude signal corresponding to the baseband signal, wherein the second amplitude signal is orthogonal to the first amplitude signal. The radio frequency circuit is configured to generate a first local oscillator signal and a second local oscillator signal corresponding to the phase signal, mix the first local oscillator signal with the first amplitude signal to generate a first radio frequency signal, mix the second local oscillator signal with the second amplitude signal to generate a second radio frequency signal, and superimpose the first radio frequency signal and the second radio frequency signal to generate a target radio frequency signal, wherein the first local oscillator signal and the second local oscillator signal are orthogonal.

2. The digital transmitter of claim 1, wherein, The radio frequency circuit includes a frequency synthesizer, a first radio frequency digital-to-analog converter, a second radio frequency digital-to-analog converter and an adder. The first radio frequency digital-to-analog converter is coupled between a first output terminal of the frequency synthesizer and a first input terminal of the adder. The second radio frequency digital-to-analog converter is coupled between a second output terminal of the frequency synthesizer and a second input terminal of the adder. The frequency synthesizer, the first radio frequency digital-to-analog converter and the second radio frequency digital-to-analog converter are coupled with the digital front-end circuit. The frequency synthesizer is configured to generate the first local oscillator signal and the second local oscillator signal. The first radio frequency digital-to-analog converter is configured to mix the first local oscillator signal with the first amplitude signal to generate the first radio frequency signal. The second radio frequency digital-to-analog converter is configured to mix the second local oscillator signal with the second amplitude signal to generate the second radio frequency signal.

3. The digital transmitter of claim 2, wherein, The frequency synthesizer includes a phase-locked loop and a frequency divider. An input terminal of the frequency divider is coupled with an output terminal of the phase-locked loop. A first output terminal of the frequency divider is coupled with an input terminal of the first radio frequency digital-to-analog converter, and a second output terminal of the frequency divider is coupled with an input terminal of the second radio frequency digital-to-analog converter.

4. The digital transmitter of claim 3, wherein, The frequency synthesizer further includes a digital time converter. The digital time converter is coupled between the phase-locked loop and the frequency divider.

5. The digital transmitter of claim 2, wherein, The frequency synthesizer includes a phase-locked loop and a polyphase filter. The phase-locked loop is coupled between the digital front-end circuit and an input terminal of the polyphase filter. A first output terminal of the polyphase filter is coupled with an input terminal of the first radio frequency digital-to-analog converter, and a second output terminal of the polyphase filter is coupled with an input terminal of the second radio frequency digital-to-analog converter.

6. A digital transmitter as claimed in any one of claims 1 to 5, characterized in that The digital processing circuit includes a coordinate rotation digital computer and a quadrature amplitude compensation circuit. The coordinate rotation digital computer is configured to perform polar coordinate processing on the baseband signal to generate the first amplitude signal and the phase signal, wherein the baseband signal is a quadrature signal, and the phase signal is a polar coordinate signal. The quadrature amplitude compensation circuit is configured to perform differential processing on the first amplitude signal to generate the second amplitude signal.

7. A communication device, characterized by The baseband processor is coupled with the digital transmitter, and is configured to transmit a baseband signal to the digital transmitter.

8. The communication device of claim 7, wherein, The baseband processor comprises a modem; The modem is coupled with an input end of the digital processing circuit, and the modem is configured to generate a base frequency signal and transmit the base frequency signal to the digital processing circuit.

9. The communication device according to claim 7 or 8, characterized by The communication device further comprises an antenna coupled with the digital transmitter, and the digital transmitter is configured to transmit the target radio frequency signal through the antenna.

10. A method for generating a radio frequency signal, applied to a digital transmitter, characterized in that, Comprise: The digital processing circuit in the digital transmitter receives a base frequency signal, and generates a phase signal, a first amplitude signal and a second amplitude signal corresponding to the base frequency signal, wherein the second amplitude signal is orthogonal to the first amplitude signal; The radio frequency circuit in the digital transmitter generates a first local oscillator signal and a second local oscillator signal corresponding to the phase signal, mixes the first local oscillator signal with the first amplitude signal to generate a first radio frequency signal, mixes the second local oscillator signal with the second amplitude signal to generate a second radio frequency signal, and superimposes the first radio frequency signal and the second radio frequency signal to generate a target radio frequency signal, wherein the first local oscillator signal and the second local oscillator signal are orthogonal.

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