Network test transmission optimization method and test system

Abstract

The application provides a network test transmission optimization method and a test system, and belongs to the technical field of network testing.The network test transmission optimization method of the application transmits only the 4-layer header and load description information, compared with transmitting complete data packets, the data transmission amount of the PCIe bus is greatly reduced, and the bandwidth occupation of the PCIe bus is significantly reduced;the FPGA intelligent network card locally completes load generation, assembly and detection, does not need to rely on the CPU processing of the mainboard, reduces the data interaction delay, and improves the concurrent test capability of the test instrument.

Description

Technical Field

[0001] This invention relates to the field of network testing technology, and in particular to a network testing transmission optimization method and testing system. Background Technology

[0002] With the rapid development of cloud computing, big data, and 5G communication technologies, data center network bandwidth is evolving rapidly from 10Gbps to 25Gbps, 100Gbps, 200Gbps, and even 400Gbps. Network testing instruments play a crucial role in verifying the performance and stability of these high-speed network devices, such as switches, routers, firewalls, and load balancers.

[0003] In actual Layer 4-7 network testing, there are two typical scenarios: The first is that there are no requirements for the specific content of the load above Layer 4 (i.e., above the transport layer, including the application layer, presentation layer, etc.), only that the data packet format compliance and transmission performance testing requirements need to be met; The second is that the content of the load above Layer 4 is limited, that is, the load set is fixed and can be enumerated in advance, so there is no need to transmit the complete load data every time.

[0004] In existing technologies, regardless of whether Layer 4 or higher payloads are required, complete data packets (including headers below Layer 4 and payloads above Layer 4) are transmitted via the PCIe (Peripheral Component Interconnect Express) bus. When port speeds reach the 400G level, the transmission of payloads above Layer 4 consumes a significant amount of PCIe bandwidth, leading to PCIe bus saturation. This limits the port speed improvement and concurrent testing capabilities of test instruments, failing to meet the testing requirements in high-bandwidth scenarios. Therefore, there is an urgent need for a PCIe transmission optimization solution for the above two scenarios, which can reduce the amount of data transmitted on the PCIe bus without affecting test accuracy, thus overcoming performance bottlenecks. Summary of the Invention

[0005] This invention provides a network test transmission optimization method and test system to solve the defect of large bus data volume during testing in the prior art, and to achieve the effect of reducing the data transmission volume of PCIe bus.

[0006] This invention provides a network test transmission optimization method, which is applied to a test system including an instrument motherboard and a field-programmable gate array (FPGA) smart network card. The instrument motherboard and the FPGA smart network card are connected via a PCIe bus through peripheral components. The method includes a sending process and a receiving process.

[0007] The transmission process includes: the instrument motherboard generating a header below layer 4 and load description information corresponding to the load above layer 4 in the data packet according to the test requirements; the instrument motherboard sending the header below layer 4 and the load description information to the FPGA smart network card through the PCIe bus; the FPGA smart network card receiving the header below layer 4 and the load description information, and obtaining the corresponding load content above layer 4 according to the load description information; the FPGA smart network card assembling the header below layer 4 and the obtained load content above layer 4 into a complete data packet, and sending it to the network under test through a physical port;

[0008] The receiving process includes: the FPGA smart network card receives data packets from the network under test through a physical port, and parses them to obtain headers below layer 4 and loads above layer 4; the FPGA smart network card performs feature detection on the loads above layer 4 and obtains corresponding load description information; the FPGA smart network card sends the headers below layer 4 and the obtained load description information to the instrument motherboard through the PCIe bus; the instrument motherboard completes test data statistics based on the received headers below layer 4 and load description information.

[0009] According to a network test transmission optimization method provided by the present invention, when the test scenario is that there are no requirements for the load content of layers 4 and above, the load description information is the load length information;

[0010] The step of obtaining the corresponding load content at layer 4 or above based on the load description information specifically includes:

[0011] The FPGA smart network card generates random data that meets the length requirement locally as load data based on the load length information, and inserts a target pseudo-random binary sequence as an identifier at a preset position in the load data.

[0012] According to a network test transmission optimization method provided by the present invention, the FPGA smart network card performs feature detection on the load of layers 4 and above, specifically including:

[0013] The FPGA smart network card detects whether the target pseudo-random binary sequence exists in the payload of the received data packets at layers 4 or above;

[0014] If the target pseudo-random binary sequence is detected, it is determined that the data packet does not need to transmit payload content. The payload length is extracted as the payload description information and sent to the instrument motherboard via the PCIe bus.

[0015] According to a network test transmission optimization method provided by the present invention, when the test scenario involves a load of limited content at layer 4 or higher, the load description information is a load ID;

[0016] Before executing the sending process, the method further includes a pre-configuration process, which includes:

[0017] The instrument motherboard generates a mapping table for all preset load contents of layers 4 and above and their corresponding load IDs and verification values.

[0018] The mapping table is loaded into the local memory of the FPGA smart network card via the PCIe bus.

[0019] According to a network test transmission optimization method provided by the present invention, the step of obtaining the corresponding Layer 4 or higher load content based on the load description information specifically includes:

[0020] The FPGA smart network card queries the mapping table in the local memory based on the received load ID and reads the corresponding load content of layers 4 and above.

[0021] According to a network test transmission optimization method provided by the present invention, in the receiving process, the FPGA smart network card performs feature detection on the load of layers 4 and above, specifically including:

[0022] The FPGA smart network card calculates the verification value of the received load of layers 4 and above, and queries the mapping table in the local memory according to the calculated verification value;

[0023] If the query matches successfully, the corresponding load ID is obtained as the load description information and sent to the instrument motherboard via the PCIe bus; if the query fails to match, the complete data packet is written to the memory of the instrument motherboard via the PCIe bus.

[0024] According to a network test transmission optimization method provided by the present invention, the checksum is calculated using the MD5 algorithm, and the mapping table contains the correspondence between the load ID, the load content, and the MD5 value.

[0025] According to the network test transmission optimization method provided by the present invention, the target pseudo-random binary sequence is a pseudo-random sequence PRBS-31, and the preset position is the 16th to 48th bytes after the load start position of layer 4 or above.

[0026] The present invention also provides a testing system, comprising:

[0027] The instrument motherboard is equipped with upper-level driver software, which is used to generate or process the header and payload description information of data packets below level 4, and to perform data interaction through the PCIe bus.

[0028] The FPGA smart network card is connected to the instrument motherboard via the PCIe bus and is equipped with local memory and a logic processing unit.

[0029] The testing system is configured to perform any of the network test transmission optimization methods described above.

[0030] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement any of the network test transmission optimization methods described above.

[0031] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the network test transmission optimization methods described above.

[0032] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements any of the network test transmission optimization methods described above.

[0033] The network test transmission optimization method and test system provided by this invention significantly reduce the data transmission volume of the PCIe bus by transmitting only the header and load description information of layer 4 and below, compared with transmitting the complete data packet, thus significantly reducing the bandwidth occupation of the PCIe bus. The FPGA smart network card completes the load generation, assembly and detection locally without relying on the motherboard CPU, reducing data interaction latency and improving the concurrent testing capability of the test instrument. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of the testing system provided by the present invention;

[0036] Figure 2 This is a flowchart illustrating the network testing transmission optimization method provided by the present invention;

[0037] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0039] The following is combined with Figure 1 Figure 3 illustrates the network test transmission optimization method and test system of the present invention.

[0040] As shown in Figure 1, this embodiment of the invention provides a test system, which physically consists of two main parts: an instrument motherboard and an FPGA (Field Programmable Gate Array) smart network card. The two communicate with each other via a PCIe bus.

[0041] An instrument motherboard refers to a computing platform equipped with a high-performance general-purpose processor, such as an x86 architecture CPU, supporting PCIe 4.0 / 5.0 bus (x16 lanes), and running upper-layer driver software. The instrument motherboard can run an operating system (such as Linux) and upper-layer driver software. In this invention, the instrument motherboard is no longer responsible for handling all data, but has transformed into a control core. The instrument motherboard is used to maintain the protocol stack state machine, generate headers below layer 4 (L2-L4 headers), and generate and manage load description information.

[0042] The instrumentation motherboard's software stack includes user-mode test applications and kernel-mode or DPDK (Data Plane Development Kit) drivers. The upper-layer driver software manages the PCIe descriptor ring, enabling efficient interaction with the FPGA.

[0043] FPGA smart network cards refer to network interface cards that integrate high-performance FPGA chips, such as those using Xilinx FPGA chips, integrating 16GB DDR4 local RAM and a hardware MD5 check module.

[0044] The core logic processing unit of the FPGA chip contains firmware that implements the logic of this invention. Local memory is typically onboard DDR4 SDRAM or HBM. Physical ports support QSFP-DD or OSFP package interfaces, providing 100G / 400G physical connections. The FPGA can internally implement a PCIe Endpoint controller, DMA engine, packet parser, packet assembler, PRBS generation / verification module, MD5 hardware acceleration module, etc.

[0045] The PCIe bus serves as the physical channel connecting the motherboard and the network card. In this embodiment, a PCIe 4.0 x16 or PCIe 5.0 x16 interface can be used to provide the highest possible base bandwidth.

[0046] The Layer 4 and below headers (L2-L4 headers) refer to the control information portion of network data packets, typically including the Ethernet frame header (MAC address, VLAN), IP header (source / destination IP, TTL, protocol number), and TCP / UDP header (source / destination port, sequence number, ACK number, flags). This part is usually of fixed length and relatively short, approximately 54-100 bytes.

[0047] Layer 4 and above payload (L4+Payload) refers to the data portion following the TCP / UDP header, i.e., application layer data such as HTTP messages and FTP data blocks. In 400G tests, this portion often accounts for more than 90% of the bandwidth.

[0048] The load description information is not the actual load data; it can be a short index or instruction used to instruct the FPGA network interface card (NIC) on how to generate or reconstruct the load. The load description information can be a length value or a unique ID index.

[0049] like Figure 2 As shown, the network test transmission optimization method of this invention can be applied to the test system of the foregoing embodiments, that is, the test system can execute the network test transmission optimization method in the following embodiments. This method mainly includes a sending process and a receiving process.

[0050] The transmission process includes: the instrument motherboard generates a header below layer 4 and a load description information corresponding to the load above layer 4 based on the test requirements; the instrument motherboard sends the header below layer 4 and the load description information to the FPGA smart network card via the PCIe bus; the FPGA smart network card receives the header below layer 4 and the load description information, and obtains the corresponding load content above layer 4 based on the load description information; the FPGA smart network card assembles the header below layer 4 and the obtained load content above layer 4 into a complete data packet, and sends it to the network under test through the physical port.

[0051] The receiving process includes: the FPGA smart network card receives data packets from the network under test through the physical port, and parses them to obtain the header below layer 4 and the load above layer 4; the FPGA smart network card performs feature detection on the load above layer 4 and obtains the corresponding load description information; the FPGA smart network card sends the header below layer 4 and the obtained load description information to the instrument motherboard through the PCIe bus; the instrument motherboard completes the test data statistics based on the received header below layer 4 and load description information.

[0052] In some embodiments, the sending process is as follows.

[0053] The upper-layer driver software on the instrument motherboard constructs the header of the data packets based on the current test flow configuration. Simultaneously, it generates a brief load description based on the test scenario.

[0054] The instrument motherboard writes only the header and load description information into the descriptor ring accessible by the FPGA smart network card via the PCIe bus.

[0055] Compared to transmitting a complete packet, only a smaller number of bytes need to be transmitted, significantly reducing PCIe bandwidth usage. For example, PCIe bandwidth that could previously only run at 20Gbps can now theoretically drive 400Gbps of physical traffic.

[0056] After the internal transmission engine of the FPGA smart network interface card (NIC) reads the descriptor, it extracts the header. Simultaneously, it parses the payload description information. If the description information specifies a length, the FPGA NIC activates its internal random number generator to generate data of the specified length.

[0057] If the description information is a load ID, the FPGA smart network card can start the DDR4 read controller to retrieve pre-stored data blocks from the onboard memory based on the load ID.

[0058] The packet assembly logic inside the FPGA smart network card splices the header and the payload generated locally by the FPGA smart network card, recalculates the IP checksum and TCP / UDP checksum, and finally adds a frame check sequence before sending it to the optical port through the physical MAC layer.

[0059] In some embodiments, the receiving process is as follows.

[0060] The FPGA smart network interface card (NIC) receives 400G line-speed traffic from the physical port. The parsing logic quickly separates the header and payload. The FPGA smart NIC does not directly upload data; instead, it performs feature detection on the payload.

[0061] The FPGA smart network card internally checks in parallel whether the payload contains a specific PRBS (Pseudo Random Binary Sequence) signature, or calculates the MD5 hash value of the payload.

[0062] If the feature match is successful, it indicates that it is a test message. The FPGA smart network card can discard heavy load data and only extract the load description information representing the load, such as load length or load ID.

[0063] The FPGA smart network card writes only the "header + load description information" to the motherboard memory via PCIe's DMA (Direct Memory Access). After receiving the simplified packet, the upper-layer software uses the header to count packet loss, out-of-order packets, and latency, and uses the load description information to verify the correctness of the data content, thus completing the test loop.

[0064] According to the network test transmission optimization method provided in the embodiments of the present invention, by transmitting only the header and load description information of layer 4 and below, the data transmission volume of the PCIe bus is greatly reduced compared with transmitting the complete data packet, which significantly reduces the bandwidth occupation of the PCIe bus; the FPGA smart network card completes the load generation, assembly and detection locally without relying on the motherboard CPU for processing, reducing data interaction latency and improving the concurrent testing capability of the test instrument.

[0065] In random load tests without content requirements, such as RFC2544 benchmark tests and TCP throughput tests, where specific application layer content is not a concern, the load description information can be the load length information.

[0066] In some embodiments, the corresponding load content of layers 4 and above is obtained according to the load description information. Specifically, the FPGA smart network card generates random data that meets the length requirements as load data locally according to the load length information, and inserts a target pseudo-random binary sequence as an identifier at a preset position of the load data.

[0067] An FPGA smart network interface card can integrate a linear feedback shift register module. Upon receiving a length command, the linear feedback shift register module operates at full speed, generating 64 or 128 bytes of pseudo-random numbers per clock cycle until the specified length is filled.

[0068] In some embodiments, the target pseudo-random binary sequence is a PRBS-31 sequence, with the preset position being the 16th to 48th bytes after the load start position of layer 4 or above.

[0069] To help the receiving end recognize that this is a test packet rather than background traffic or an abnormal packet, it can be marked.

[0070] For example, the marker could be a PRBS-31 sequence, which has an extremely long period and is very difficult to conflict with natural data. The insertion position can be selected from bytes 16 to 48 after the start position. Avoiding the first 16 bytes is to prevent position offset caused by extensions in certain protocol headers; selecting a length of 32 bytes is to ensure robustness of detection.

[0071] Specifically, in the multiplexer logic of the FPGA smart network card during packet assembly, when the counter reaches 16, the data source can be forcibly switched to a fixed PRBS generator output for 32 bytes, and then switched back to the random number generator.

[0072] In some embodiments, the FPGA smart network card performs feature detection on loads of layers 4 and above, specifically including: the FPGA smart network card detects whether there is a target pseudo-random binary sequence in the load of layers 4 and above of the received data packet; if a target pseudo-random binary sequence is detected, it is determined that the data packet does not need to transmit load content, the load length is extracted as load description information, and sent to the instrument motherboard through the PCIe bus.

[0073] The receiver engine of an FPGA smart network interface card can include a sliding window detector or a fixed-position comparator. When the 16th byte of the data packet is parsed, the comparator starts and compares the received bit stream bit by bit with the locally stored PRBS-31 sequence.

[0074] If all 32 bytes match, the FPGA smart network interface card (NIC) can perform a truncation operation, discarding the payload content, retaining only the header, and filling the PCIe descriptor with the parsed actual length value for transmission back. If there is no match, it indicates that it may be a protocol control packet or non-test data; in this case, the FPGA smart network interface card can perform a pass-through operation, uploading the complete packet.

[0075] In this implementation, the PRBS identification mechanism achieves both 100% data compression and ensures that the receiving end can verify the legitimacy of the data, i.e., it is not garbled text, but a tagged test stream, thus resolving the contradiction between bandwidth and accuracy.

[0076] In some embodiments, in fixed-load testing scenarios with limited content, such as HTTP / HTTPS new connection testing, web page playback, and virus attack signature database playback, the load content in these scenarios must be specific and cannot be random, but the content set is limited.

[0077] When the test scenario involves a load of 4 layers or more with limited content, the load description information can be the load ID.

[0078] Before executing the transmission process, the method also includes a pre-configuration process, which includes: the instrument motherboard generating a mapping table of all preset load contents of layers 4 and above and their corresponding load IDs and check values; and loading the mapping table into the local memory of the FPGA smart network card through the PCIe bus.

[0079] During the initialization phase before testing, a cache warm-up can be performed. The upper-layer software scans all test data, such as the bodies of 100 different HTTP GET request messages, and assigns an ID (0-99) to each content. It calculates the MD5 value (128 bits) for each content and constructs a mapping table structure. The actual content data and mapping table can be moved to the FPGA's onboard DDR4 memory via PCIe. This single transfer allows for multiple uses, eliminating the need to repeatedly transfer static data during testing.

[0080] The corresponding load content at or above layer 4 is obtained based on the load description information. Specifically, the FPGA smart network card queries the mapping table in the local memory based on the received load ID and reads the corresponding load content at or above layer 4.

[0081] When the FPGA smart network card receives the instruction "send ID=5", its internal memory controller calculates the physical address offset in DDR4 based on ID=5. The FPGA smart network card initiates a local DMA read, reads the corresponding HTTP packet body from DDR4, appends the read data to the IP / TCP header, and then sends it.

[0082] In some embodiments, during the receiving process, the FPGA smart network card performs feature detection on loads of layers 4 and above. Specifically, this includes: the FPGA smart network card calculates the check value of the received loads of layers 4 and above, and queries the mapping table in the local memory based on the calculated check value; if the query is successful, the corresponding load ID is obtained as load description information and sent to the instrument motherboard via the PCIe bus; if the query fails, the complete data packet is written to the memory of the instrument motherboard via the PCIe bus.

[0083] The checksum is calculated using the MD5 algorithm, and the mapping table contains the correspondence between the load ID, load content, and MD5 value.

[0084] Unlike CPUs, FPGA smart network interface cards (NICs) cannot perform sequential MD5 calculations internally. In this embodiment, the FPGA smart NIC can employ a pipelined MD5 calculation engine. When data packets flow in at a rate of 400Gbps, the data can be divided into 512-bit blocks, which are fed into the MD5 pipeline each clock cycle. Regardless of packet length, the 128-bit MD5 digest value can be calculated within a few clock cycles after the data stream ends.

[0085] FPGA smart network interface cards (NICs) not only store "ID-content" but can also store "MD5-ID" hash lookup tables or content-addressable memory logic. After calculating the MD5 value of the received packet, a fast match is performed in the FPGA smart network interface card's local storage.

[0086] A successful match indicates that the received packet content is correct and belongs to the preset set. At this point, the FPGA smart network card does not need to upload data or MD5, only the ID. After receiving the ID, the instrument mainboard can confirm that a correct HTTP request has been received.

[0087] A failed match indicates that the packet may be out of order, tampered with, or not a test packet. In this case, to facilitate troubleshooting, the FPGA smart network card uploads the complete data packet to the instrument motherboard via PCIe for analysis.

[0088] In this implementation, verification matching ensures the rigor of the test and the integrity of the content. Meanwhile, the ID return mechanism maintains extremely low PCIe bandwidth usage.

[0089] Understandably, in scenarios where there are no requirements for the content of the load above Layer 4, a specific PRBS sequence is used to ensure the compliance of the load format. In scenarios where the content of the load above Layer 4 is limited, MD5 checksum is used to ensure the correctness of the load transmission. This does not affect the core indicators of Layer 4-7 network testing, such as throughput, latency, and packet loss rate.

[0090] Furthermore, the solutions of this invention have strong compatibility. They can be based on existing FPGA smart network cards and PCIe bus architectures without modifying the hardware interface. Only the FPGA firmware and upper-layer driver software need to be upgraded. It can be adapted to mainstream 4-7 layer network test instruments with low upgrade costs.

[0091] Figure 3 illustrates a schematic diagram of the physical structure of an electronic device. As shown in Figure 3, the electronic device may include: a processor 310, a communication interface 320, a memory 330, and a communication bus 340, wherein the processor 310, the communication interface 320, and the memory 330 communicate with each other through the communication bus 340. The processor 310 can call logic instructions in the memory 330 to execute a network test transmission optimization method, which includes a sending process and a receiving process. The sending process includes: the instrument motherboard generates a header below layer 4 and a load description information corresponding to the load above layer 4 in the data packet according to the test requirements; the instrument motherboard sends the header below layer 4 and the load description information to the FPGA smart network card through the PCIe bus; the FPGA smart network card receives the header below layer 4 and the load description information, and obtains the corresponding load content above layer 4 according to the load description information; the FPGA smart network card assembles the header below layer 4 and the obtained load content above layer 4 into a complete data packet, and sends it to the network under test through the physical port. The receiving process includes: the FPGA smart network card receives the data packet from the network under test through the physical port, and parses it to obtain the header below layer 4 and the load above layer 4; the FPGA smart network card performs feature detection on the load above layer 4 and obtains the corresponding load description information; the FPGA smart network card sends the header below layer 4 and the obtained load description information to the instrument motherboard through the PCIe bus; the instrument motherboard completes test data statistics based on the received header below layer 4 and the load description information.

[0092] Furthermore, the logical instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0093] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the network test transmission optimization method provided by the above methods. This method includes: a sending process and a receiving process; the sending process includes: the instrument motherboard generating a header below layer 4 and load description information corresponding to the load above layer 4 of the data packet according to the test requirements; the instrument motherboard sending the header below layer 4 and the load description information to the FPGA smart network card through the PCIe bus; the FPGA smart network card receiving the header below layer 4 and the load description information, and... The FPGA smart network card obtains the corresponding load content at layer 4 and above based on the load description information; it assembles the header below layer 4 and the obtained load content at layer 4 and above into a complete data packet and sends it to the network under test through the physical port; the receiving process includes: the FPGA smart network card receives data packets from the network under test through the physical port and parses them to obtain the header below layer 4 and the load at layer 4 and above; the FPGA smart network card performs feature detection on the load at layer 4 and above and obtains the corresponding load description information; the FPGA smart network card sends the header below layer 4 and the obtained load description information to the instrument motherboard through the PCIe bus; the instrument motherboard completes the test data statistics based on the received header below layer 4 and the load description information.

[0094] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, this computer program implements the network test transmission optimization method provided by the methods described above. This method includes: a sending process and a receiving process; the sending process includes: the instrument motherboard generating a header below layer 4 and load description information corresponding to the load above layer 4 of a data packet according to test requirements; the instrument motherboard sending the header below layer 4 and the load description information to the FPGA smart network card via the PCIe bus; the FPGA smart network card receiving the header below layer 4 and the load description information, and obtaining the corresponding layer 4 and above load description information based on the load description information. The process involves the following steps: The FPGA smart network card assembles the header (below Layer 4) and the acquired load (above Layer 4) into a complete data packet and sends it to the network under test via a physical port. The receiving process includes: The FPGA smart network card receives data packets from the network under test via a physical port and parses them to obtain the header (below Layer 4) and the load (above Layer 4); The FPGA smart network card performs feature detection on the load (above Layer 4) and obtains the corresponding load description information; The FPGA smart network card sends the header (below Layer 4) and the acquired load description information to the instrument motherboard via the PCIe bus; The instrument motherboard completes test data statistics based on the received header (below Layer 4) and load description information.

[0095] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for optimizing network test transmission, characterized in that, The method is applied to a test system including an instrument motherboard and a field-programmable gate array (FPGA) smart network card, wherein the instrument motherboard and the FPGA smart network card are connected via a PCIe bus for rapid interconnection through peripheral components. The method includes a sending process and a receiving process; The transmission process includes: the instrument motherboard generating a header below layer 4 and load description information corresponding to the load above layer 4 in the data packet according to the test requirements; the instrument motherboard sending the header below layer 4 and the load description information to the FPGA smart network card through the PCIe bus; the FPGA smart network card receiving the header below layer 4 and the load description information, and obtaining the corresponding load content above layer 4 according to the load description information; the FPGA smart network card assembling the header below layer 4 and the obtained load content above layer 4 into a complete data packet, and sending it to the network under test through a physical port; The receiving process includes: the FPGA smart network card receives data packets from the network under test through a physical port, and parses them to obtain headers below layer 4 and loads above layer 4; the FPGA smart network card performs feature detection on the loads above layer 4 and obtains corresponding load description information; the FPGA smart network card sends the headers below layer 4 and the obtained load description information to the instrument motherboard through the PCIe bus; the instrument motherboard completes test data statistics based on the received headers below layer 4 and load description information.

2. The network test transmission optimization method according to claim 1, characterized in that, When the test scenario involves a load of 4 layers or more with no specific requirements, the load description information is the load length information. The step of obtaining the corresponding load content at layer 4 or above based on the load description information specifically includes: The FPGA smart network card generates random data that meets the length requirement locally as load data based on the load length information, and inserts a target pseudo-random binary sequence as an identifier at a preset position in the load data.

3. The network test transmission optimization method according to claim 2, characterized in that, The FPGA smart network interface card performs feature detection on the load at layers 4 and above, specifically including: The FPGA smart network card detects whether the target pseudo-random binary sequence exists in the payload of the received data packets at layers 4 or above; If the target pseudo-random binary sequence is detected, it is determined that the data packet does not need to transmit payload content. The payload length is extracted as the payload description information and sent to the instrument motherboard via the PCIe bus.

4. The network test transmission optimization method according to claim 1, characterized in that, When the test scenario involves a load of 4 layers or more with limited content, the load description information is the load ID; Before executing the sending process, the method further includes a pre-configuration process, which includes: The instrument motherboard generates a mapping table for all preset load contents of layers 4 and above and their corresponding load IDs and verification values. The mapping table is loaded into the local memory of the FPGA smart network card via the PCIe bus.

5. The network test transmission optimization method according to claim 4, characterized in that, The step of obtaining the corresponding load content at layer 4 or above based on the load description information specifically includes: The FPGA smart network card queries the mapping table in the local memory based on the received load ID and reads the corresponding load content of layers 4 and above.

6. The network test transmission optimization method according to claim 4, characterized in that, In the receiving process, the FPGA smart network card performs feature detection on the load at layers 4 and above, specifically including: The FPGA smart network card calculates the verification value of the received load of layers 4 and above, and queries the mapping table in the local memory according to the calculated verification value; If the query matches successfully, the corresponding load ID is obtained as the load description information and sent to the instrument motherboard via the PCIe bus; if the query fails to match, the complete data packet is written to the memory of the instrument motherboard via the PCIe bus.

7. The network test transmission optimization method according to claim 6, characterized in that, The verification value is calculated using the MD5 algorithm, and the mapping table contains the correspondence between the load ID, load content, and MD5 value.

8. The network test transmission optimization method according to claim 2, characterized in that, The target pseudo-random binary sequence is a pseudo-random sequence PRBS-31, and the preset position is the 16th to 48th bytes after the load start position of layer 4 or above.

9. A testing system, characterized in that, include: The instrument motherboard is equipped with upper-level driver software, which is used to generate or process the header and payload description information of data packets below level 4, and to perform data interaction through the PCIe bus. The FPGA smart network card is connected to the instrument motherboard via the PCIe bus and is equipped with local memory and a logic processing unit. The testing system is configured to perform the network test transmission optimization method as described in any one of claims 1 to 8.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the network test transmission optimization method as described in any one of claims 1 to 8.

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