Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a first wiring portion including a first insulating layer and a first conductor layer provided on one surface of the first insulating layer; a second wiring portion including a second insulating layer and a second conductor layer provided on one surface of the second insulating layer, the one surface of the second insulating layer facing the one surface of the first insulating layer; an adhesive portion disposed between the first wiring portion and the second wiring portion to connect the first wiring portion and the second wiring portion, and including an adhesive layer and a conductive filler dispersed within the adhesive layer; and a first insulating film disposed on a portion of the first conductor layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0121374, filed on September 6, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0185920, filed on December 13, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] Recently, due to the development of artificial intelligence (AI) technology, packages including memory chips (such as high-bandwidth memory (HBM)), processor chips (such as central processing units (CPUs) and graphics processing units (GPUs)) and logic chips (such as application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs)) can be used to process exponentially growing data.

[0004] Studies have been conducted to reduce defects occurring during chip mounting and to improve the yield of printed circuit boards used in such packages. As the number of substrate layers increases, the defect rate of each layer may accumulate, which may reduce the overall yield, and the yield reduction may be more pronounced in substrates requiring fine circuitry. Summary of the Invention

[0005] The present disclosure provides a printed circuit board whose reliability can be improved by bonding multiple wiring portions together.

[0006] According to this disclosure, a printed circuit board includes: a first wiring portion including a first insulating layer and a first conductor layer disposed on one surface of the first insulating layer; a second wiring portion including a second insulating layer and a second conductor layer disposed on one surface of the second insulating layer, the one surface of the second insulating layer facing the one surface of the first insulating layer; an adhesive portion disposed between the first wiring portion and the second wiring portion to connect the first wiring portion and the second wiring portion, and the adhesive portion including an adhesive layer and a conductive filler dispersed within the adhesive layer; and a first insulating film disposed on a portion of the first conductor layer.

[0007] The first insulating film may include at least one of Al2O3, ZnO, TiO2 and SiO2.

[0008] The first insulating film may be an atomic layer deposition layer.

[0009] The thickness of the first insulating film can be from 5 nm to 15 nm.

[0010] The first insulating film may also be disposed on one of the surfaces of the first insulating layer.

[0011] The first insulating film may expose a portion of one surface of the first insulating layer.

[0012] The first insulating film can contact the conductive filler.

[0013] The first insulating film may be coated on the portion of the first conductor layer.

[0014] The first insulating film may be the surface oxide layer of the first conductor layer.

[0015] The area of ​​the first conductor layer on which the first insulating film is disposed may be thicker than the area of ​​the first conductor layer on which the first insulating film is not disposed.

[0016] The adhesive portion can contact the surface of the first conductor layer where the first insulating film is not disposed, as well as the side surface of the first insulating film.

[0017] The area of ​​the first conductor layer on which the first insulating film is not disposed may have a step difference relative to the area of ​​the first conductor layer on which the first insulating film is disposed.

[0018] The area of ​​the first conductor layer on which the first insulating film is not disposed may have a groove shape relative to the area of ​​the first conductor layer on which the first insulating film is disposed.

[0019] The adhesive portion may be disposed in the region of the first conductor layer having the groove shape.

[0020] The pitch of the first conductor layer may be smaller than the pitch of the second conductor layer.

[0021] The second wiring portion may further include a second insulating film disposed on a portion of the second conductor layer.

[0022] The first exposed area of ​​the first conductor layer exposed by the first insulating film and the second exposed area of ​​the second conductor layer exposed by the second insulating film can be connected to each other through the conductive filler.

[0023] The first insulating film is not provided on the side surface of the first insulating layer, and the second insulating film is not provided on the side surface of the second insulating layer.

[0024] The width of the first insulating layer and the width of the second insulating layer can be substantially the same.

[0025] The first insulating film extends to the side surface of the first insulating layer, and the second insulating film is not disposed on the side surface of the second insulating layer.

[0026] The width of the first insulating layer may be smaller than the width of the second insulating layer.

[0027] The first wiring portion may further include: a third conductor layer disposed on another surface of the first insulating layer opposite to one surface of the first insulating layer; and a third insulating film disposed on a portion of the third conductor layer.

[0028] The second wiring portion may further include: a fourth conductor layer disposed on another surface of the second insulating layer opposite to the first surface of the second insulating layer; and a fourth insulating film disposed on a portion of the fourth conductor layer. Attached Figure Description

[0029] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system; Figure 2 It is a perspective view schematically illustrating an example of an electronic device; Figure 3 This is a schematic cross-sectional view illustrating an example of a printed circuit board; Figures 4 to 7 An example of the manufacturing process for printed circuit boards is shown; Figure 8 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 9 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 10 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 11 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 12 This illustrates another example of the manufacturing process for printed circuit boards; Figure 13 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 14 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 15 This is a schematic cross-sectional view illustrating another example of a printed circuit board; and Figure 16This is a schematic cross-sectional view illustrating another example of a printed circuit board. Detailed Implementation

[0030] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. However, the present disclosure may be exemplified in many different forms and should not be construed as limiting oneself to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be comprehensive and complete, and will fully convey the scope of the disclosure to those skilled in the art. Therefore, for clarity of description, the shape and size of the elements in the drawings may be exaggerated, and elements denoted by the same reference numerals in the drawings are the same elements.

[0031] Electronic devices Figure 1 This is a block diagram that schematically illustrates an example of an electronic device system.

[0032] Reference Figure 1 The electronic device 1000 may house a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the motherboard 1010. These components may be connected to other electronic components described below via various signal lines 1090.

[0033] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, encryption processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 can be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips or electronic components.

[0034] Network-related components 1030 may include components compatible with or operating according to standards or protocols such as: Wireless Fidelity (Wi-Fi) (IEEE 802.11 series, etc.), Global Microwave Access Interoperability (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolved Data Optimized (Ev-DO), High Speed ​​Packet Access+ (HSPA+), High Speed ​​Downlink Packet Access+ (HSDPA+), High Speed ​​Uplink Packet Access+ (HSUPA+), Global System for Mobile Communications (GSM), Evolution of GSM with Enhanced Data Rates (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), 3G, 4G, and 5G protocols, and any other wireless and wired protocols specified after the aforementioned protocols. However, network-related component 1030 is not limited to this and may also include components compatible with or operating according to various other wireless standards or protocols and wired standards or protocols. Furthermore, network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0035] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these, and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0036] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. Depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0037] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital camera, digital video camera, network system, computer, monitor, tablet PC, laptop PC, netbook, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these, but can be any other electronic device capable of processing data.

[0038] Figure 2 It is a perspective view schematically showing an example of an electronic device.

[0039] Reference Figure 2 The electronic device can be a smartphone 1100. A motherboard 1110 can be housed in the smartphone 1100, and various components 1120 can be physically and / or electrically connected to the motherboard 1110. Furthermore, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the motherboard 1110 or not physically and / or electrically connected to the motherboard 1110 can be housed in the smartphone 1100. A portion of component 1120 can be a chip-related component, such as a component package 1121, but its exemplary embodiments are not limited thereto. Component package 1121 can take the form of a printed circuit board on which electronic components (including active and / or passive components) are surface-mounted. Optionally, component package 1121 can take the form of a printed circuit board in which electronic components (including active and / or passive components) are embedded. The electronic device is not necessarily limited to the smartphone 1100 and can also be other electronic devices as described above.

[0040] Printed Circuit Board Figure 3 This is a schematic cross-sectional view illustrating an example of a printed circuit board. (See reference...) Figure 3The printed circuit board 100 according to this embodiment includes a first wiring portion 110, a second wiring portion 120, and an adhesive portion 130. The first wiring portion 110 and the second wiring portion 120 are connected by the adhesive portion 130, which includes an adhesive layer 131 and a conductive filler 132. Here, the first wiring portion 110 includes a first insulating layer 111 and a first conductor layer 112, and the second wiring portion 120 includes a second insulating layer 121 and a second conductor layer 122. Furthermore, a first insulating film 141 may be provided on a portion of the first conductor layer 112. Similarly, a second insulating film 142 may be provided on a portion of the second conductor layer 122, and the following description of the first insulating film 141 also applies to the second insulating film 142. As shown in this embodiment, when connecting the first wiring portion 110 and the second wiring portion 120, by forming a first insulating film 141 on a portion of the first conductor layer 112 and / or forming a second insulating film 142 on a portion of the second conductor layer 122, accidental electrical connections between the first conductor layer 112 and the second conductor layer 122 can be prevented, thereby improving the electrical reliability of the printed circuit board 100. The main components of the printed circuit board 100 will be described in more detail below.

[0041] The first wiring portion 110 includes a first insulating layer 111 and a first conductor layer 112, and the first insulating layer 111 and the first conductor layer 112 may each include multiple layers. However, the first insulating layer 111 and the first conductor layer 112 may also be implemented as a single-layer structure; for example, the first wiring portion 110 may be bonded to the second wiring portion 120 as a single-layer stack. The first insulating layer 111 may include an insulating material, such as an insulating resin (e.g., a thermosetting resin (e.g., epoxy resin) or a thermoplastic resin (e.g., polyimide)), a material that mixes these insulating resins with an inorganic filler (e.g., silica), or a material prepared by impregnating a core material (e.g., glass fiber (e.g., glass fabric, such as glass cloth)) together with an inorganic filler into a thermosetting or thermoplastic resin (e.g., Ajinomoto laminate (ABF), prepreg, etc.). If desired, the first insulating layer 111 may also include a photosensitive dielectric (PID). The first insulating layer 111 can be obtained by stacking multiple insulating layers, wherein the multiple insulating layers may include the same or different insulating materials.

[0042] The first conductor layer 112 may be disposed on at least one surface of the first insulating layer 111 and may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first conductor layer 112 may include electroless plating and electroplating layers, and may also include copper foil if desired. The first conductor layer 112 may perform various functions depending on the design of the respective layer. For example, the first conductor layer 112 may include ground patterns, power patterns, signal patterns, etc. Here, signal patterns may include various signals (such as data signals) other than ground patterns, power patterns, etc. Each of these patterns may include traces, planes, and / or pads. The first conductor layer 112 may be disposed in a multilayer structure on the surface of the first insulating layer 111 and / or inside the first insulating layer 111, and in embodiments, a layer disposed on one surface of the first insulating layer 111 is referred to as the first conductor layer 112, and a layer disposed on another surface of the first insulating layer 111 is referred to as the third conductor layer 114.

[0043] The first wiring portion 110 may further include a first via 113. The first via 113 may be configured to connect the first conductor layer 112 and the third conductor layer 114. The first via 113 may include a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first via 113 may be formed together with the first conductor layer 112 and may include an electroless plating layer and an electroplated layer. The first via 113 may be a filled via in which a through-hole of the first insulating layer 111 is filled with a metallic material, but exemplary embodiments thereof are not limited thereto, and the first via 113 may also be a conformal via in which a metallic material is disposed along the wall surface of the through-hole. In the cross-section of the printed circuit board 100 (hereinafter, unless otherwise specified, all cross-sections refer to the cross-section of the printed circuit board), the first via 113 may have a tapered shape, but is not limited thereto, such as... Figure 3 As shown, the first via 113 may also have an hourglass shape. The first via 113 may perform various functions depending on the design of the corresponding layer. For example, the first via 113 may include a grounding via, a power via, a signal via, etc. Here, a signal via may include vias other than grounding vias, power vias, etc., used for transmitting various signals (such as data signals).

[0044] Similar to the first wiring portion 110, the second wiring portion 120 includes a second insulating layer 121 and a second conductor layer 122, which may each comprise multiple layers. However, the second insulating layer 121 and the second conductor layer 122 may also be implemented as a single-layer structure; for example, the second wiring portion 120 may be bonded to the first wiring portion 110 as a single-layer stack. The second insulating layer 121 may include an insulating material, such as a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), a material that mixes these insulating resins with an inorganic filler (e.g., silica), or a material prepared by impregnating a core material (e.g., glass fiber (e.g., glass fabric, such as glass cloth)) together with an inorganic filler into a thermosetting or thermoplastic resin (e.g., Ajinomoto laminate (ABF), prepreg, etc.). If desired, the second insulating layer 121 may also include a photosensitive dielectric (PID). The second insulating layer 121 can be obtained by stacking multiple insulating layers. The multiple insulating layers may comprise the same or different insulating materials.

[0045] The second conductor layer 122 may be disposed on at least one surface of the second insulating layer 121 and may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The second conductor layer 122 may include electroless plating and electroplating layers, and may also include copper foil if desired. The second conductor layer 122 may perform various functions depending on the design of the respective layer. For example, the second conductor layer 122 may include ground patterns, power patterns, signal patterns, etc. Here, signal patterns may include various signals (such as data signals) other than ground patterns, power patterns, etc. Each of these patterns may include traces, planes, and / or pads. The second conductor layer 122 may be disposed in a multilayer structure on the surface and / or inside the second insulating layer 121, and in embodiments, a layer disposed on one surface of the second insulating layer 121 is referred to as the second conductor layer 122, and a layer disposed on another surface of the second insulating layer 121 is referred to as the fourth conductor layer 124.

[0046] The second wiring section 120 may further include a second via 123. The second via 123 may be configured to connect the second conductor layer 122 and the fourth conductor layer 124. The second via 123 may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The second via 123 may be formed together with the second conductor layer 122 and may include electroless plating and electroplating layers. The second via 123 may be a filled via in which a through-hole of the second insulating layer 121 is filled with metallic material, but exemplary embodiments thereof are not limited to this, and the second via 123 may also be a conformal via in which metallic material is disposed along the wall surface of the through-hole. In cross-section, the second via 123 may have a tapered shape, but is not limited to this, such as... Figure 3 As shown, the second via 123 may also have an hourglass shape. The second via 123 can perform various functions depending on the design of the corresponding layer. For example, the second via 123 may include grounding vias, power vias, signal vias, etc. Here, signal vias may include vias for transmitting various signals (such as data signals) other than grounding vias, power vias, etc.

[0047] An adhesive portion 130 is disposed between the first wiring portion 110 and the second wiring portion 120 to connect the first wiring portion 110 and the second wiring portion 120, and in addition to its adhesive function, the adhesive portion 130 can also serve as a path for electrical connection. For this purpose, the adhesive portion 130 may include an adhesive layer 131 and a conductive filler 132 dispersed within the adhesive layer 131. The adhesive layer 131 may include an insulating resin and may also include a thermopolymerizable compound (such as an epoxy compound) or a photopolymerizable compound (such as an acrylate compound). The conductive filler 132 may include metal particles such as nickel (Ni) particles, cobalt (Co) particles, silver (Ag) particles, copper (Cu) particles, gold (Au) particles, or palladium (Pd) particles, and copper (Cu) particles may be used herein.

[0048] The adhesive portion 130 can be configured to bond multiple separately manufactured wiring portions 110 and 120, thereby effectively realizing a multilayer substrate. As the number of substrate layers increases, the defect rate increases, and the decrease in yield is particularly pronounced in substrates requiring fine circuitry. When a portion of a wiring portion (such as the first wiring portion 110) employs a fine circuitry process, the first wiring portion 110 can be realized as a relatively fine circuit. In this case, compared to simultaneously manufacturing the first wiring portion 110 and the second wiring portion 120, the defect rate can be reduced by manufacturing the second wiring portion 120 using a process separate from the process for manufacturing the first wiring portion 110. In this case, the second wiring portion 120 with a relatively wide pitch can also be manufactured using a relatively inexpensive process.

[0049] Furthermore, in this embodiment, a first insulating film 141 is employed to reduce short-circuit defects caused by accidental electrical connections in the areas where the first wiring portion 110 and the second wiring portion 120 are connected to each other. The first insulating film 141 may be formed on a portion of the first conductor layer 112; for example, the first insulating film 141 may be formed in the remaining areas of the first conductor layer 112 except for the pad areas connected to the second conductor layer 122. The first insulating film 141 may contact the conductive filler 132 of the adhesive portion 130. The first insulating film 141 may be coated on a portion of the first conductor layer 112. Optionally, the first insulating film 141 may be a surface oxide layer of the first conductor layer 112. In this case, the surface oxide layer may include oxides of the metals included in the first conductor layer 112. When the first conductor layer 112 is protected by the first insulating film 141, the first conductor layer 112 is effectively electrically protected in the remaining areas of the wiring portions 110 and 120 except for the connection areas of the wiring portions 110 and 120, thereby improving the electrical reliability of the printed circuit board 100. Additionally, to further improve reliability, a second insulating film 142 may be provided, and the second insulating film 142 may be formed on a portion of the second conductor layer 122. For example, the second insulating film 142 may be formed in the remaining area of ​​the second conductor layer 122, excluding the pad area connected to the first conductor layer 112. The second insulating film 142 may contact the conductive filler 132 of the adhesive portion 130. Similarly, the second insulating film 142 may be coated on a portion of the second conductor layer 122. Optionally, the second insulating film 142 may be a surface oxide layer of the second conductor layer 122. In this case, the surface oxide layer may include oxides of the metals included in the second conductor layer 122.

[0050] The first insulating film 141 can be formed to have a thin thickness while maintaining high electrical insulation. In this regard, the first insulating film 141 may include at least one of Al2O3, ZnO, TiO2, and SiO2. The first insulating film 141 can be made thinner than other components; for example, the thickness of the first insulating film 141 may be 5 nm to 15 nm. As an example of a method for forming the first insulating film 141, the first insulating film 141 may be an atomic layer deposition layer obtained using an atomic layer deposition process. When the first insulating film 141 is an atomic layer deposition layer, the first insulating film 141 may be formed using Al2O3, wherein Al2O3 may have high insulation and high adhesion. However, other vapor phase deposition processes may also be used. The second insulating film 142 can be formed to have a thin thickness while maintaining high electrical insulation. In this regard, the second insulating film 142 may include at least one of Al2O3, ZnO, TiO2, and SiO2. The second insulating film 142 can be made thinner than other components; for example, the thickness of the second insulating film 142 can be from 5 nm to 15 nm. As an example of a method for forming the second insulating film 142, the second insulating film 142 can be an atomic layer deposition layer obtained using an atomic layer deposition process. However, other vapor deposition processes can also be used.

[0051] like Figure 3 In the form shown, in addition to being formed on a portion of the first conductor layer 112, the first insulating film 141 may also be formed on one surface of the first insulating layer 111 (e.g., based on...). Figure 3 The second insulating film 142 is formed on the lower surface of the first insulating layer 111, thereby further reducing the possibility of a short circuit. In addition to being formed on a portion of the second conductor layer 122, the second insulating film 142 may also be formed on one surface of the second insulating layer 121 (e.g., based on...). Figure 3 On the upper surface of the second insulating layer 121, thereby further reducing the possibility of a short circuit. Optionally, the first insulating film 141 may be limited to the minimum area required to prevent accidental electrical connection between the first conductor layer 112 and the second conductor layer 122. In this case, as Figure 8 In a variant of the printed circuit board 100 shown, the first insulating film 141 can be implemented by exposing a portion of one surface of the first insulating layer 111. Similarly, the second insulating film 142 can be implemented by exposing a portion of one surface of the second insulating layer 121. Furthermore, in Figure 3 and Figure 8 In this configuration, the first insulating film 141 can expose the entire pad area of ​​the first conductor layer 112, but is not limited thereto. The first insulating film 141 can also extend further to a portion of a surface of the pad area of ​​the first conductor layer 112 to reduce the width of the exposed area in the pad area of ​​the first conductor layer 112, that is, to reduce the area of ​​the exposed area of ​​the first conductor layer 112 (e.g., as shown in the image). Figure 10 (As shown in the embodiment). Similarly, the second insulating film 142 may further extend onto a portion of a surface of the pad region of the second conductor layer 122 to reduce the width of the exposed area in the pad region of the second conductor layer 122, i.e., reduce the area of ​​the exposed area of ​​the second conductor layer 122.

[0052] Reference Figure 3 Electrical connections between the first wiring portion 110 and the second wiring portion 120 can be performed in areas where the first insulating film 141 and the second insulating film 142 are not formed. Specifically, the first exposed area R1 in the first conductor layer 112 where the first insulating film 141 is not formed and the second exposed area R2 in the second conductor layer 122 where the second insulating film 142 is not formed can be connected to each other via conductive filler 132. In this case, although in Figure 3 Only one first exposed area R1 and one second exposed area R2 are shown, but this may only be a part of the printed circuit board 100, and multiple first exposed areas R1 and multiple second exposed areas R2 may be provided.

[0053] As an additional component, the first wiring portion 110 may further include: a third conductor layer 114 disposed on the other surface of the first insulating layer 111 opposite to one surface of the first insulating layer 111 on which the first conductor layer 112 is formed (based on...). Figure 3 The third insulating film 143 is formed on a portion of the third conductor layer 114. Furthermore, similar to the first insulating film 141, the third insulating film 143 may also be formed on the upper surface of the first insulating layer 111. Additionally, the second wiring portion 120 may further include: a fourth conductor layer 124 disposed on the other surface of the second insulating layer 121 opposite to one surface on which the second conductor layer 122 is formed (based on...). Figure 3 The third insulating film 143 is formed on the lower surface of the first insulating film 141 and the second insulating film 142; and the fourth insulating film 144 is formed on a portion of the fourth insulating layer 124. Furthermore, similar to the second insulating film 142, the fourth insulating film 144 may also be formed on the lower surface of the second insulating layer 121. The third insulating film 143 and the fourth insulating film 144 may comprise the same material as the first insulating film 141 and the second insulating film 142, and the third insulating film 143 and the fourth insulating film 144 may be formed by the same process as that used to form the first insulating film 141 and the second insulating film 142.

[0054] Reference Figures 4 to 7 An example describing the manufacturing process of a printed circuit board focuses on the bonding process of the first wiring portion 110 and the second wiring portion 120. First, after the first wiring portion 110 is fabricated, a mask M1 (such as a mask M1 covering a portion of the first conductor layer 112) can be formed. Figure 4As shown in the diagram), the area covered by mask M1 can be an area in which the first insulating film 141 is not formed and is exposed. Additionally, a mask M2 can be formed covering a portion of the third conductor layer 114. Masks M1 and M2 can comprise metals having etching properties different from those of conductor layers 112 and 114. Next, a first insulating film 141 covering the first conductor layer 112 and a third insulating film 143 covering the third conductor layer 114 are formed (as shown in the diagram). Figure 5 (As shown in the diagram). Insulating films 141 and 143 may comprise at least one of materials (such as Al2O3, ZnO, TiO2, and SiO2) that exhibit excellent insulation even at relatively small thicknesses, and may be formed by processes such as atomic layer deposition. Figure 5 In this case, insulating films 141 and 143 are not formed on the side surfaces of the first insulating layer 111. However, unlike this, insulating films 141 and 143 may also be formed on the side surfaces of the first insulating layer 111. However, in the panel cutting process described later, insulating films 141 and 143 may not be present on the side surfaces of a unit printed circuit board.

[0055] Next, masks M1 and M2 are removed to expose a portion of the first conductor layer 112 and a portion of the third conductor layer 114, and adhesive portion 130 is attached to one surface of the first wiring portion 110 (e.g., Figure 6 (As shown in the diagram). Masks M1 and M2 can be removed by a dry etching process (such as plasma etching) or a wet etching process that is available to those skilled in the art. Adhesive portion 130 can be a semi-cured adhesive layer 131 having conductive filler 132 therein or an uncured adhesive layer 131. The second wiring portion 120 can be prepared by the same process as that used to prepare the first wiring portion 110, and the first wiring portion 110 and the second wiring portion 120 can be bonded by applying pressure to the first wiring portion 110 and the second wiring portion 120, thereby obtaining a printed circuit board (e.g., with adhesive portion 130 disposed between the first wiring portion 110 and the second wiring portion 120). Figure 7 (As shown in the diagram). By using the adhesive portion 130 to bond the first wiring portion 110 and the second wiring portion 120, the method of mixing and bonding Cu layers can be replaced.

[0056] Reference Figures 9 to 16 A printed circuit board according to an example embodiment is described. First, in Figure 9In this embodiment, the region of the first conductor layer 112 where the first insulating film 141 is formed is thicker than the region of the first conductor layer 112 where the first insulating film 141 is not formed. In other words, the first exposed region R1 of the first conductor layer 112 can be relatively thin. During the above-described manufacturing process, this can be achieved by an over-etching process that removes a portion of the first conductor layer 112 together with the removal mask M1 process. In this case, the amount of etching of the first conductor layer 112 can be adjusted according to the size of the desired step structure; for example, a first conductor layer 112 of about 2 μm thickness can be removed. Similarly, in the removal mask M2 process, a portion of the third conductor layer 114 can be removed together, so the region of the third conductor layer 114 not covered by the third insulating film 143 can have a relatively thin thickness.

[0057] Because the first conductor layer 112 is partially removed, the first exposed area R1 of the first conductor layer 112 where the first insulating film 141 is not formed can have a step difference relative to the area of ​​the first conductor layer 112 where the first insulating film 141 is formed. Therefore, the adhesive portion 130 can contact the surface of the first exposed area R1 of the first conductor layer 112 where the first insulating film 141 is not formed and the side surface of the first insulating film 141, thereby improving the adhesion between the first conductor layer 112 and the adhesive portion 130. Similarly, because the third conductor layer 114 is partially removed, the area of ​​the third conductor layer 114 where the third insulating film 143 is not formed can have a step difference relative to the area of ​​the first conductor layer 112 where the third insulating film 143 is formed. As an example of such a stepped structure, such as... Figure 10 In the variant embodiment shown, the first exposed area R1 of the first conductor layer 112 where the first insulating film 141 is not formed may have a groove shape relative to the area of ​​the first conductor layer 112 where the first insulating film 141 is formed. In this case, the adhesive portion 130 may fill the groove-shaped area of ​​the first conductor layer 112. Additionally, although not in Figure 10 As shown, however, the region of the third conductor layer 114 where the third insulating film 143 is not formed may also have a groove shape relative to the region of the first conductor layer 112 where the third insulating film 143 is formed. Although in Figure 9 and Figure 10 The description is based on the first conductor layer 112, but the description of the same components can also be applied to the second conductor layer 122. Although in Figure 9 and Figure 10 The description is based on the first conductor layer 112, but the second conductor layer 122 may also adopt the same structure.

[0058] According to the variant embodiment Figure 11A more specific structure of the first wiring portion 210 and the second wiring portion 220 of the printed circuit board 200 is shown. In an embodiment, the printed circuit board 200 has a first wiring portion 210 and a second wiring portion 220 connected to each other by an adhesive portion 230, and the first wiring portion 210 and the second wiring portion 220 have different structures. The first wiring portion 210 may include a first insulating layer 211 and a first conductor layer 212, and the first insulating layer 211 and the first conductor layer 212 may each include multiple layers. The first insulating layer 211 may include an insulating material, such as a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), a material that mixes these insulating resins with an inorganic filler (such as silica), or a material prepared by impregnating a core material (such as glass fiber (such as glass fabric, for example glass cloth)) together with an inorganic filler into a thermosetting or thermoplastic resin (e.g., Ajinomoto laminate (ABF), prepreg, etc.). If desired, the first insulating layer 211 may include a photosensitive dielectric (PID). The first insulating layer 211 can be obtained by stacking multiple insulating layers, wherein the multiple insulating layers may include the same or different insulating materials.

[0059] The first conductor layer 212 may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first conductor layer 212 may include electroless plating and electroplating layers, and may also include copper foil if desired. The first conductor layer 212 may perform various functions depending on the design of the respective layer. For example, the first conductor layer 212 may include ground patterns, power patterns, signal patterns, etc. Here, signal patterns may include various signals (such as data signals) other than ground patterns, power patterns, etc. Each of these patterns may include traces, planes, and / or pads.

[0060] The first wiring section 210 may further include a first via 213. The first via 213 may be configured to connect to the first conductor layer 212. The first via 213 may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first via 213 may be formed together with the first conductor layer 212 and may include electroless plating and electroplating layers. The first via 213 may be a filled via in which a through-hole of the first insulating layer 211 is filled with metallic material, but exemplary embodiments are not limited thereto, and the first via 213 may also be a conformal via in which metallic material is disposed along the wall surface of the through-hole. In cross-section, the first via 213 may have a tapered shape. The first via 213 may perform various functions depending on the design of the corresponding layer. For example, the first via 213 may include a grounding via, a power via, a signal via, etc. Here, signal vias may include vias used to transmit various signals (such as data signals), in addition to grounding vias, power vias, etc.

[0061] A first solder resist layer 214 may be disposed on the exterior of the first wiring portion 210. The first solder resist layer 214 may have an opening that partially exposes the first conductor layer 212 disposed in the uppermost portion of the first wiring portion 210. The first solder resist layer 214 may include commonly used solder resist materials and may include photosensitive insulating materials, but exemplary embodiments thereof are not limited thereto.

[0062] The second wiring portion 220 may include a second insulating layer 221 and a second conductor layer 222, and the second insulating layer 221 and the second conductor layer 222 may each include multiple layers. The second insulating layer 221 may include a first core portion 221B and stacked portions 221A and 221C respectively disposed above and below the first core portion 221B. The first core portion 221B may include an insulating material, such as a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), a material that mixes these insulating resins with inorganic fillers (such as silica), or a material prepared by impregnating a core material (such as glass fiber (such as glass fabric, for example glass cloth)) together with an inorganic filler into a thermosetting or thermoplastic resin (e.g., copper clad laminate (CCL), etc.), but exemplary embodiments thereof are not limited thereto. If desired, a core insulating layer of different materials (such as a glass substrate, etc.) may be introduced into the first core portion 221B, or a metal core layer may also be used. The first core portion 221B may be provided with a through hole 224 to connect the second conductor layer 222 disposed above and below the through hole 224.

[0063] Stacked portions 221A and 221C may be respectively disposed on two surfaces of the first core portion 221B and may have a multilayer structure. Stacked portions 221A and 221C may include insulating materials, such as thermosetting resins (e.g., epoxy resins), thermoplastic resins (e.g., polyimide), materials that mix these insulating resins with inorganic fillers (e.g., silica), or materials prepared by impregnating a core material (e.g., glass fiber (e.g., glass fabric, such as glass cloth)) together with inorganic fillers into a thermosetting or thermoplastic resin (e.g., Ajinomoto laminate (ABF), prepreg, etc.). If desired, stacked portions 221A and 221C may include photosensitive dielectrics (PIDs). The regions forming the second insulating layer 221 of stacked portions 221A and 221C may be obtained by stacking multiple insulating layers, wherein the multiple insulating layers may include the same or different insulating materials.

[0064] The second conductor layer 222 may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The second conductor layer 222 may include electroless plating and electroplating layers, and may also include copper foil if desired. The second conductor layer 222 may perform various functions depending on the design of the respective layer. For example, the second conductor layer 222 may include ground patterns, power patterns, signal patterns, etc. Here, signal patterns may include various signals (such as data signals) other than ground patterns, power patterns, etc. Each of these patterns may include traces, planes, and / or pads.

[0065] In this embodiment, when the second conductor layer 222 has a multilayer structure, the second via 223 can be configured to connect the second conductor layer 222. The second via 223 may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The second via 223 may be formed together with the second conductor layer 222 and may include electroless plating and electroplating layers. The second via 223 may be a filled via in which a through-hole of the second insulating layer 221 is filled with metallic material, but is not limited thereto, and the second via 223 may also be a conformal via in which metallic material is disposed along the wall surface of the through-hole. In cross-section, the second via 223 may have a tapered shape. The second via 223 may perform various functions depending on the design of the corresponding layer. For example, the second via 223 may include a grounding via, a power via, a signal via, etc. Here, signal vias may include vias used to transmit various signals (such as data signals), in addition to grounding vias, power vias, etc.

[0066] In the case of the first wiring portion 210, compared to the second conductor layer 222 of the second wiring portion 220, the first conductor layer 212 disposed in the first wiring portion 210 can be implemented with a relatively narrow pitch using fine circuit technology. In this case, compared to manufacturing the first wiring portion 210 and the second wiring portion 220 simultaneously, the defect rate can be reduced by manufacturing the second wiring portion 220 using a process separate from the process for manufacturing the first wiring portion 210. In this case, the second wiring portion 220 with a relatively wide pitch can also be manufactured using a relatively inexpensive process.

[0067] The second solder resist layer 225 may be disposed on the exterior of the second wiring portion 220. The second solder resist layer 225 may have an opening that partially exposes the second conductor layer 222 disposed in the lowermost portion of the second wiring portion 220. The second solder resist layer 225 may include commonly used solder resist materials and may include photosensitive insulating materials, but exemplary embodiments thereof are not limited thereto.

[0068] Similar to the embodiments described above, the adhesive portion 230 includes an adhesive layer 231 and a conductive filler 232. A first insulating film 241 may be provided on a portion of the first conductor layer 212. Similarly, a second insulating film 242 may be provided on a portion of the second conductor layer 222. In this case, as... Figure 11 As shown, the first insulating film 241 may not be formed on the side surface of the first insulating layer 211, and the second insulating film 242 may not be formed on the side surface of the second insulating layer 221. (Refer to...) Figure 12 Describe the process used to obtain this structure. For example... Figure 12 As shown, the first wiring portion 210 and the second wiring portion 220 can be implemented in the form of panels. That is, the first panel 210P and the second panel 220P can be bonded together by adhesive panel 230P, and can be bonded together along the cutting line ( Figure 12 The first panel 210P and the second panel 220P are cut (as shown by the dashed lines) to obtain a unit printed circuit board. In this case, after cutting, there is no insulating film on the side surface of the unit printed circuit board. Furthermore, in this manufacturing method, as... Figure 11 As shown, the width of the first insulating layer 211 and the width of the second insulating layer 221 can be substantially the same.

[0069] Alternatively, as in the variant embodiment Figure 13As shown, a structure is illustrated in which the first insulating film 241 extends to the side surface of the first insulating layer 211 and the second insulating film 242 is not formed on the side surface of the second insulating layer 221. Such a structure can be obtained by forming the first insulating film 241 in the first wiring portion 210 in a unit state without using a method of bonding the first wiring portion 210 to the second wiring portion 220 and then cutting them. For example, such a structure can be obtained by using a method of bonding the first wiring portion 210 in a unit state to the second wiring portion 220 in a panel state and then cutting the second wiring portion 220. In this case, the width of the first insulating layer 211 can be smaller than the width of the second insulating layer 221. When the first insulating film 241 is also formed on the side surface of the first insulating layer 211, the overall insulation of the first wiring portion 210 can be improved.

[0070] In addition, such as Figure 13 The structure shown can be obtained not only by bonding the first wiring portion 210 to the second wiring portion 220 manufactured in the form of a panel and then cutting, but also by bonding the second wiring portion 220 to the first wiring portion 210 in a unit state (i.e., in a unit state) after cutting. Additionally, as in... Figure 14 As shown, even when the first insulating film 241 extends to the side surface of the first insulating layer 211 in the first wiring portion 210, the width of the first insulating layer 211 and the width of the second insulating layer 221 can be substantially the same. Furthermore, as in... Figure 15 In the embodiments, the width of the first insulating layer 211 and the width of the second insulating layer 221 are substantially the same, and both the first insulating film 241 and the second insulating film 242 can extend to the side surfaces of the first insulating layer 211 and the second insulating layer 221, respectively. That is, in addition to the first insulating film 241, the second insulating film 242 can also extend to the side surface of the second insulating layer 221. Furthermore, as... Figure 16 As shown, when the width of the first insulating layer 211 is smaller than the width of the second insulating layer 221, the first insulating film 241 can extend to the side surface of the first insulating layer 211, and the second insulating film 242 can extend to the side surface of the second insulating layer 221. Additionally, Figures 9 to 16 The description of other components of the printed circuit board in the diagram can be compared with... Figure 3 The descriptions of the corresponding components on the printed circuit board are the same, therefore, their repeated descriptions will be omitted.

[0071] In this disclosure, the term "section" can refer to the shape when an object is cut vertically or when the object is viewed from the side. Furthermore, the term "plane" can refer to the shape when an object is cut horizontally or when the object is viewed from the top or bottom.

[0072] In this disclosure, for convenience, the term "upper" in "upper side," "upper part," and "upper surface" refers to the upward direction relative to the cross-section of the drawing, and the term "lower side," "lower part," and "lower surface" refers to the direction opposite to the upward direction. However, the above directions are defined for ease of interpretation, and the scope of the claims is not specifically limited by the description of the directions, and the concepts of upper / lower can be changed at any time.

[0073] In this disclosure, the term "connection" includes not only the concept of direct connection but also the concept of indirect connection, such as through adhesive layers. Furthermore, the term "electrical connection" encompasses both physical and non-physical connections. Additionally, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, the first component may be referred to as the second component, or similarly, the second component may be referred to as the first component.

[0074] The term "example embodiment" as used in this disclosure does not imply the same embodiment, but is provided to explain different unique characteristics. However, the example embodiments presented above do not preclude implementation through combinations of features with other example embodiments. For example, unless there is an interpretation contrary to or contradicting that of other example embodiments, even if content described in a particular example embodiment is not described in other example embodiments, it may be understood as an interpretation related to other example embodiments.

[0075] The terminology used in this disclosure is for describing exemplary embodiments only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions unless explicitly stated otherwise in the context.

[0076] As described above, in a printed circuit board according to an embodiment of the present disclosure, reliability can be improved by bonding multiple wiring portions together.

[0077] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board comprising: a first wiring portion including a first insulating layer and a first conductor layer provided on one surface of the first insulating layer; a second wiring portion including a second insulating layer and a second conductor layer provided on one surface of the second insulating layer, the one surface of the second insulating layer facing the one surface of the first insulating layer; an adhesive portion provided between the first wiring portion and the second wiring portion to connect the first wiring portion and the second wiring portion, and including an adhesive layer and a conductive filler dispersed within the adhesive layer; and a first insulating film provided on a part of the first conductor layer. The first insulating film includes at least one of Al2O3, ZnO, TiO2, and SiO2.

2. The printed circuit board of claim 1, wherein, The first insulating film is an atomic layer deposition layer.

3. The printed circuit board of claim 1, wherein, The first insulating film has a thickness of 5 nm to 15 nm.

4. The printed circuit board of claim 1, wherein, The first insulating film is further provided on the one surface of the first insulating layer.

5. The printed circuit board of claim 1, wherein, The first insulating film exposes a part of the one surface of the first insulating layer.

6. The printed circuit board of claim 1, wherein, The first insulating film is in contact with the conductive filler.

7. The printed circuit board of claim 1, wherein, The first insulating film is coated on the part of the first conductor layer.

8. The printed circuit board of claim 1, wherein, The first insulating film is a surface oxidation layer of the first conductor layer.

9. The printed circuit board of claim 1, wherein, A region of the first conductor layer on which the first insulating film is provided is thicker than a region of the first conductor layer on which the first insulating film is not provided.

10. The printed circuit board of claim 1, wherein, The adhesive portion is in contact with a surface of the region of the first conductor layer on which the first insulating film is not provided and a side surface of the first insulating film.

11. The printed circuit board of claim 10, wherein, The region of the first conductor layer on which the first insulating film is not provided has a step difference with respect to the region of the first conductor layer on which the first insulating film is provided.

12. The printed circuit board of claim 10, wherein, The region of the first conductor layer on which the first insulating film is not provided has a groove shape with respect to the region of the first conductor layer on which the first insulating film is provided.

13. The printed circuit board of claim 10, wherein, The adhesive portion is provided in the region of the first conductor layer having the groove shape.

14. The printed circuit board of claim 13, wherein, A pitch of the first conductor layer is narrower than a pitch of the second conductor layer.

15. The printed circuit board of claim 1, wherein, The second wiring portion further includes a second insulating film provided on a part of the second conductor layer.

16. The printed circuit board of claim 1, wherein, A first exposed region of the first conductor layer exposed by the first insulating film and a second exposed region of the second conductor layer exposed by the second insulating film are connected to each other by the conductive filler.

17. The printed circuit board of claim 16, wherein, A side surface of the first insulating layer is not provided with the first insulating film, and 18. The printed circuit board of claim 16, wherein, A side surface of the second insulating layer is not provided with the second insulating film. A width of the first insulating layer and a width of the second insulating layer are the same.

19. The printed circuit board of claim 18, wherein, The first insulating film extends to a side surface of the first insulating layer, and 20. The printed circuit board of claim 16, wherein, The second insulating layer is not provided with the second insulating film on the side surface. The width of the first insulating layer is smaller than the width of the second insulating layer.

21. The printed circuit board of claim 20, wherein, The first wiring portion further includes a third conductor layer provided on another surface of the first insulating layer opposite to the one surface of the first insulating layer, and a third insulating film provided on a part of the third conductor layer.

22. The printed circuit board of claim 1, wherein, ​ 23. The printed circuit board of claim 22, wherein, The second wiring portion further includes a fourth conductor layer provided on the other surface of the second insulating layer opposite to the one surface of the second insulating layer, and a fourth insulating film provided on a portion of the fourth conductor layer.

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