Semiconductor structure, preparation method of semiconductor structure and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method of the semiconductor structure and electronic equipment. The memory unit comprises a semiconductor layer and a gate dielectric layer which are stacked; the gate dielectric layer comprises an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side, away from the semiconductor layer, of the interface voltage reduction layer. By arranging the interface voltage reduction layer in contact with the semiconductor layer and the ferroelectric layer located on the side, away from the semiconductor layer, of the interface voltage reduction layer, the interface voltage reduction layer is located between the channel layer and the ferroelectric layer, and the interface voltage reduction layer reduces the voltage at the interface by replacing a low-k-value interface; and the durability of the device is improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure, a method for fabricating the semiconductor structure, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, and an electronic device.

[0005] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a semiconductor structure, the semiconductor structure including a substrate and a multilayer memory cell layer stacked on the substrate along a first direction perpendicular to the substrate;

[0006] Each of the memory cell layers includes multiple memory cells arranged in an array; each memory cell includes a semiconductor layer and a gate dielectric layer stacked together; the gate dielectric layer includes an interface step-down layer in contact with the semiconductor layer, and a ferroelectric dielectric layer located on the side of the interface step-down layer away from the semiconductor layer.

[0007] The semiconductor structure in the above embodiments includes a memory cell comprising a stacked semiconductor layer and a gate dielectric layer. The gate dielectric layer includes an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer. This enables a 1T0C memory structure, thereby improving the storage density of the memory device. Furthermore, by providing an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer, the present invention positions the interface voltage reduction layer between the channel layer and the ferroelectric dielectric layer. This allows the interface voltage reduction layer to replace the naturally formed low-k interface between the channel layer and the ferroelectric material, thereby reducing the voltage at the interface and improving the device's durability.

[0008] In some embodiments, the semiconductor structure further includes: a bit line extending along a first direction; the bit line being connected to a first end of a semiconductor layer of a plurality of memory cells arranged along the first direction; a word line extending along a second direction parallel to the substrate; the semiconductor layers of the plurality of memory cells arranged along the second direction are spaced around the outer wall of the word line, and a gate dielectric layer is located between the semiconductor layers and the word line, and a ferroelectric dielectric layer is in contact with the word line; and a power line extending along the first direction; the power line being connected to a second end of a semiconductor layer of a plurality of memory cells arranged along the first direction; wherein the first direction and the second direction intersect.

[0009] The semiconductor structure in the above embodiments, by providing a bit line extending along a first direction connected to a first end of the semiconductor layer, and providing a word line extending along a second direction, wherein the first direction intersects the second direction, can realize a vertical bit line structure, thereby reducing the parasitic capacitance between bit lines.

[0010] In some embodiments, a plurality of memory cells are arranged in columns along a first direction and in rows along a second direction; wherein a bit line connects the semiconductor layer of a column of memory cells; or, a bit line connects the semiconductor layers of two adjacent columns of memory cells, and the two adjacent columns of memory cells are symmetrically arranged with the bit line as the center; the gate dielectric layer has an opening on the side facing the bit line.

[0011] In some embodiments, a power line of the semiconductor structure is connected to the semiconductor layer of a row of memory cells, and the power line is located on the side of the semiconductor layer away from the bit line.

[0012] In some embodiments, the semiconductor structure includes at least one of the following features: the semiconductor layer includes a polycrystalline silicon layer; the interface voltage reduction layer includes a high-k material layer; and the ferroelectric layer includes zirconium-doped hafnium oxide.

[0013] The second aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a multilayer memory cell layer on the substrate; each memory cell layer comprising a plurality of memory cells arranged in an array; each memory cell comprising a semiconductor layer and a gate dielectric layer stacked thereon; the gate dielectric layer comprising: an interface voltage reduction layer in contact with the semiconductor layer, and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer.

[0014] The semiconductor structure fabrication method in the above embodiments, by forming multiple memory cell layers on a substrate, wherein each memory cell includes a stacked semiconductor layer and a gate dielectric layer; wherein the gate dielectric layer includes an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer, can realize a 1T0C memory structure, thereby improving the storage density of the memory device. Furthermore, by setting an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer, the interface voltage reduction layer in this embodiment is located between the channel layer and the ferroelectric dielectric layer. This allows the interface voltage reduction layer to replace the naturally formed low-k interface between the channel layer and the ferroelectric material to reduce the voltage at the interface, thereby improving the device's durability.

[0015] In some embodiments, forming a multilayer memory cell layer on a substrate includes: forming a stacked structure on the substrate, the stacked structure including a first dielectric layer and a second dielectric layer alternately stacked along a first direction perpendicular to the substrate; forming a first trench in the stacked structure, the first trench penetrating the stacked structure along a first direction and extending along a second direction; the second direction intersecting the first direction; laterally etching the second dielectric layer based on the first trench to form a first lateral trench; the first lateral trench extending along the second direction; and sequentially stacking a semiconductor layer, an interface voltage reduction layer, and a ferroelectric dielectric layer of a plurality of memory cells on the inner sidewall of the first lateral trench; wherein the semiconductor layers of the plurality of memory cells are spaced apart in the second direction.

[0016] In some embodiments, before forming the first lateral trench by laterally etching the second dielectric layer based on the first trench, the method for fabricating the semiconductor structure further includes: filling the first trench with bit line material; etching the bit line material to form a plurality of bit lines spaced apart in a second direction; and extending the bit lines along a first direction; wherein, forming the first lateral trench by laterally etching the second dielectric layer based on the first trench includes: laterally etching the second dielectric layer based on the interval between adjacent bit lines to form the first lateral trench.

[0017] The semiconductor structure fabrication method in the above embodiments, by setting a first dielectric layer and a second dielectric layer alternately stacked along a first direction perpendicular to the substrate, and setting the bit lines to be spaced apart in a second direction and extending along the first direction, enables the fabricated semiconductor structure to realize a vertical bit line 3D structure, which can reduce the parasitic capacitance between bit lines.

[0018] In some embodiments, a semiconductor layer, an interface voltage reduction layer, and a ferroelectric dielectric layer for a plurality of memory cells are sequentially stacked on the inner sidewall of a first lateral trench, including: sequentially depositing a semiconductor material, an interface voltage reduction material, a ferroelectric dielectric material, and a word line material on the inner sidewall of the first lateral trench and the outer sidewall of the bit line; removing the word line material, ferroelectric dielectric material, interface voltage reduction material, and semiconductor material located in the first trench based on the interval between adjacent bit lines, such that the word line material, ferroelectric dielectric material, interface voltage reduction material, and semiconductor material retained in the first lateral trench constitute a word line, a ferroelectric dielectric layer, an interface voltage reduction layer, and a semiconductor material layer, respectively; filling the interval between adjacent bit lines with a third dielectric layer; forming a first hole extending along a first direction in the third dielectric layer; etching and separating the semiconductor material layer based on each first hole to form a semiconductor layer for a plurality of memory cells; and filling the first hole with a fourth dielectric layer.

[0019] In some embodiments, the method for fabricating a semiconductor structure further includes: forming a plurality of second trenches on the side of the first lateral trench opposite to the first trench; the second trenches extending along a first direction and exposing a semiconductor layer; and forming power lines connecting the semiconductor layer in the second trenches.

[0020] According to some embodiments, a third aspect of this disclosure provides an electronic device including the semiconductor structure of the first aspect described above; or a semiconductor structure prepared based on the method for preparing the semiconductor structure of the second aspect. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0023] Figure 2 This is a flowchart illustrating the formation of memory cells on a substrate according to one embodiment;

[0024] Figure 3 This is a three-dimensional structural diagram of the structure obtained in S202 provided in one embodiment;

[0025] Figure 4 This is a three-dimensional structural diagram of the structure obtained in S204 provided in one embodiment;

[0026] Figure 5 This is a flowchart of forming a memory cell on a substrate provided in another embodiment;

[0027] Figure 6 Schematic three-dimensional structure diagram of the structure obtained from S205 in an embodiment;

[0028] Figure 7 Schematic three-dimensional structure diagram of the structure obtained from S206 in an embodiment;

[0029] Figure 8 Schematic three-dimensional structure diagram of the structure obtained from S2082 in an embodiment;

[0030] Figures 9-11 Schematic three-dimensional structure diagram of the structure obtained from the preparation process of S210 in an embodiment;

[0031] Figure 12 Flow chart of sequentially stacking a semiconductor layer, an interface voltage reduction layer, and a ferroelectric dielectric layer to form a plurality of memory cells on the inner side wall of the first transverse groove in an embodiment;

[0032] Figure 13 Schematic three-dimensional structure diagram of the structure obtained from S2102 in an embodiment;

[0033] Figures 14-17 Schematic three-dimensional structure diagram of the structure obtained from the preparation process of S2104 in an embodiment;

[0034] Figure 18 Schematic three-dimensional structure diagram of the structure obtained from S2106 in an embodiment;

[0035] Figure 19 Schematic three-dimensional structure diagram of the structure obtained from S2108 in an embodiment;

[0036] Figure 20 Schematic three-dimensional structure diagram of the structure for forming the second hole in an embodiment;

[0037] Figure 21 Schematic three-dimensional structure diagram of the structure obtained from S2110 in an embodiment;

[0038] Figure 22 Schematic three-dimensional structure diagram showing different cross-sections in the first direction of the structure obtained from S2110 in an embodiment;

[0039] Figure 23 Schematic three-dimensional structure diagram of the structure obtained by filling the second hole in an embodiment;

[0040] Figure 24 Flow chart of the preparation method of the semiconductor structure provided in another embodiment;

[0041] Figure 25This is a three-dimensional structural diagram of the structure obtained in S212 provided in one embodiment;

[0042] Figure 26 This is a three-dimensional structural diagram of the structure obtained in S214 provided in one embodiment.

[0043] Explanation of reference numerals in the attached figures:

[0044] 100, Substrate; 200, Stacked structure; D1, First direction; D2, Second direction; D3, Third direction; 210, First dielectric layer; 220, Second dielectric layer; 310, First trench; 320, Bit line material; 330, First trench; 300, Bit line; 410, First lateral trench; 610, Semiconductor layer; 620, Interface step-down layer; 630, Ferroelectric dielectric layer; 420, Word line material; 400, Word line; 630', Partial ferroelectric dielectric layer; 620', Partial interface step-down layer; 610', Partial semiconductor material layer; 210', Partial first dielectric layer; 230, Third dielectric layer; 240, Fourth dielectric layer; 640, First via; 650, Second via; 510, Second trench; 500, Power line. Detailed Implementation

[0045] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0051] In one embodiment, see Figure 1 This disclosure provides a method for preparing a semiconductor structure, including the following steps: S10 and S20.

[0052] S10: Provide substrate 100.

[0053] For example, substrate 100 may be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For instance, the substrate may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0054] S20: A multilayer memory cell layer is formed on the substrate; each memory cell layer includes multiple memory cells arranged in an array, and each memory cell includes a semiconductor layer and a gate dielectric layer stacked together; the gate dielectric layer includes: an interface voltage reduction layer in contact with the semiconductor layer, and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer.

[0055] The semiconductor structure fabrication method in the above embodiments, by forming multiple memory cell layers on a substrate, wherein each memory cell includes a stacked semiconductor layer and a gate dielectric layer; wherein the gate dielectric layer includes an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer, can achieve a 1T0C memory structure, thereby improving the storage density of the memory device. Furthermore, by setting an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer, the interface voltage reduction layer in this embodiment is located between the channel layer and the ferroelectric dielectric layer. Therefore, the interface voltage reduction layer can replace the naturally formed low-k interface between the channel layer and the ferroelectric material to reduce the voltage at the interface, thereby improving the device's durability.

[0056] In some embodiments, please refer to Figure 2 Step S20, which forms a multilayer memory cell layer on the substrate 100, includes S202-S210.

[0057] S202: A stacked structure 200 is formed on the substrate 100. The stacked structure 200 includes a first dielectric layer 210 and a second dielectric layer 220 that are alternately stacked along a first direction D1 perpendicular to the substrate.

[0058] Please see Figure 3 , Figure 3 This is a three-dimensional structural diagram of the structure obtained in S202; wherein, the first direction D1 is the direction perpendicular to the substrate 100. Figure 3As shown, a first dielectric layer 210 and a second dielectric layer 220 can be alternately deposited on a substrate 100 using a deposition process to form a stacked structure 200. The second dielectric layer 220 serves a supporting role, ensuring the stability of the semiconductor structure throughout the entire process. The etching ratios of the first dielectric layer 210 and the second dielectric layer 220 are different. The first dielectric layer 210 can be silicon oxide, etc., and the second dielectric layer 220 can be silicon nitride, etc. The deposition process can include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD). As a further example, the first dielectric layer 210 can be prepared by plasma-enhanced chemical vapor deposition (PECVD), and the second dielectric layer 220 can be prepared by low-pressure chemical vapor deposition (LPCVD).

[0059] S204: A first trench 310 is formed in the stacked structure 200. The first trench 310 penetrates the stacked structure 200 along the first direction D1 and extends along the second direction D2; the second direction D2 intersects the first direction D1.

[0060] Please also refer to Figure 4 , Figure 4 This is a schematic diagram of the structure obtained in S204. It is understood that, for clarity, the structural diagrams shown in this disclosure represent a portion of the entire semiconductor structure. Exemplarily, a first trench 310 can be formed in the stacked structure 200 using dry etching. The first trench 310 penetrates the stacked structure 200 along a first direction D1 and extends along a second direction D2; the second direction D2 intersects the first direction D1. In some embodiments, dry etching includes at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP).

[0061] S208: The second dielectric layer 220 is etched laterally based on the first trench 310 to form a first lateral trench 410; the first lateral trench 410 extends along the second direction D2.

[0062] S210: A semiconductor layer 610, an interface voltage reduction layer 620, and a ferroelectric dielectric layer 630 of a plurality of memory cells are sequentially stacked on the inner sidewall of the first transverse trench 410; wherein the semiconductor layers of the plurality of memory cells are spaced apart on the second direction D2.

[0063] It can be understood that the first direction D1 is the vertical direction and the second direction D2 is the horizontal direction; or, the first direction D1 is the horizontal direction and the second direction D2 is the vertical direction.

[0064] In other embodiments, please refer to Figure 5 Step S20, which forms a memory cell on the substrate 100, includes S202-S210.

[0065] S202: A stacked structure 200 is formed on the substrate 100. The stacked structure 200 includes a first dielectric layer 210 and a second dielectric layer 220 that are alternately stacked along a first direction D1 perpendicular to the substrate.

[0066] S204: A first trench 310 is formed in the stacked structure 200. The first trench 310 penetrates the stacked structure 200 along the first direction D1 and extends along the second direction D2; the second direction D2 intersects the first direction D1.

[0067] S205: Fill the first groove 310 with the bit line material 320.

[0068] Please also refer to Figure 6 , Figure 6 This is a three-dimensional structural diagram of the structure obtained in S205. For example, bit line material 320 can be deposited using an atomic layer deposition (ALD) process. The bit line material 320 fills the first trench 310, and the material of the bit line material 320 can be, but is not limited to, titanium nitride (TiN).

[0069] S206: Etch bit line material 320 to form a plurality of bit lines 300 spaced apart in the second direction D2; the bit lines 300 extend along the first direction D1.

[0070] Please also refer to Figure 7 , Figure 7 This is a three-dimensional structural diagram of the structure obtained in S206. For example, the bit line material 320 can be etched along the first direction D1 using methods such as dry etching. The etching is performed on multiple bit line materials 320, and the bit line materials 320 are etched at intervals along the second direction D2, thereby forming multiple first grooves 330 extending along the first direction D1 and spaced apart along the second direction D2 in the bit line material 320. Simultaneously with the formation of the multiple first grooves 330, multiple bit lines 300 are formed at intervals distributed along the second direction D2, extending along the first direction D1.

[0071] S2082: The second dielectric layer 220 is etched laterally based on the interval between adjacent bit lines 300 to form a first lateral groove 410; the first lateral groove 410 extends along the second direction D2.

[0072] Specifically, after S206, step S2082 is performed to laterally etch the second dielectric layer 220 based on the spacing between adjacent bit lines 300, forming the first lateral trench 410. Please also refer to... Figure 8 , Figure 8 This is a three-dimensional structural diagram of the structure obtained in S2082. In order to form a plurality of first lateral grooves 410, a second dielectric layer 220 is etched laterally based on the first grooves 330. For example, wet etching can be used. The plurality of first lateral grooves 410 extend along the second direction D2 and are located on both sides of the bit line 300 in the third direction D3.

[0073] S210: A semiconductor layer 610, an interface voltage reduction layer 620, and a ferroelectric dielectric layer 630 of a plurality of memory cells are sequentially stacked on the inner sidewall of the first transverse trench 410; wherein the semiconductor layers of the plurality of memory cells are spaced apart on the second direction D2.

[0074] Please also refer to Figure 9 , Figure 9 This is a three-dimensional structural diagram of the structure obtained after forming a semiconductor layer 610 with multiple memory cells on the inner sidewall of the first lateral trench 410. The semiconductor layer 610 can be deposited by atomic layer deposition or similar processes. The material of the semiconductor layer 610 can be, but is not limited to, polysilicon. It is understood that the semiconductor layer 610 is formed in the inner sidewall of the first lateral trench 410 and also in the inner sidewall of the first trench 330. The semiconductor layer is connected to the bit line 300.

[0075] Please continue reading. Figure 10 , Figure 10 This is a three-dimensional structural diagram of the structure obtained after sequentially stacking a semiconductor layer 610 and an interface voltage reduction layer 620, which form multiple memory cells, on the inner sidewall of the first lateral trench 410. For example, the interface voltage reduction layer 620 can be deposited on the inner sidewall of the semiconductor layer 610 using atomic layer deposition (ALD) or similar processes. The material of the interface voltage reduction layer 620 can be, but is not limited to, a high-k dielectric material (such as Al2O3). It is understood that the interface voltage reduction layer 620 is formed in the inner sidewall of the semiconductor layer 610 in the first lateral trench 410 and also in the inner sidewall of the semiconductor layer 610 in the first trench 330.

[0076] Please continue reading. Figure 11 , Figure 11This is a three-dimensional structural diagram of the structure obtained after sequentially stacking a semiconductor layer 610, an interface voltage reduction layer 620, and a ferroelectric dielectric layer 630 for forming multiple memory cells on the inner wall of the first transverse trench 410; wherein the semiconductor layers of the multiple memory cells are spaced apart in the second direction D2. For example, the ferroelectric dielectric layer 630 can be deposited on the inner wall of the interface voltage reduction layer 620 using atomic layer deposition (ALD) or similar processes. The ferroelectric dielectric layer 630 may include, but is not limited to, a ferroelectric dielectric layer, and the material of the ferroelectric dielectric layer 630 may include, but is not limited to, ferroelectric materials. It is understood that the ferroelectric dielectric layer 630 is formed in the inner wall of the interface voltage reduction layer 620 of the first transverse trench 410, and also in the inner wall of the interface voltage reduction layer 620 of the first trench 330.

[0077] The semiconductor structure fabrication method in the above embodiments, by setting a first dielectric layer and a second dielectric layer alternately stacked along a first direction perpendicular to the substrate, and setting the bit lines to be spaced apart in the second direction and extending along the first direction, enables the fabricated semiconductor structure to realize a vertical bit line structure, which can reduce the parasitic capacitance between bit lines.

[0078] In some embodiments, the gate dielectric layer is a stacked structure formed by a ferroelectric dielectric layer 630 and an interface voltage reduction layer 620.

[0079] In the semiconductor structure fabrication method described above, a stacked structure formed by an interface voltage reduction layer and a ferroelectric dielectric layer is set as the gate dielectric layer. The interface voltage reduction layer is located between the channel layer and the ferroelectric dielectric layer, so that the interface voltage reduction layer reduces the voltage at the interface by replacing the interface with a low k value naturally formed between the semiconductor layer and the ferroelectric dielectric layer, thereby improving the durability of the fabricated semiconductor structure.

[0080] In some embodiments, please refer to Figure 12 Step S210 involves sequentially stacking a semiconductor layer 610, an interface voltage reduction layer 620, and a ferroelectric dielectric layer 630 for multiple memory cells on the inner sidewall of the first transverse trench, including: S2102-S2110.

[0081] S2102: Semiconductor material, interface voltage reduction material, ferroelectric material and word line material 420 are sequentially deposited on the inner sidewall of the first transverse trench 410 and the outer sidewall of the bit line 300.

[0082] Please see Figure 13 , Figure 13This is a three-dimensional structural diagram of the structure obtained in S2102. For example, titanium nitride (TiN) can be deposited on the inner wall of the ferroelectric layer 630 using atomic layer deposition (ALD) or similar processes to form the word line material 420. It can be understood that the word line material 420 is formed in the inner wall of the ferroelectric layer 630 of the first transverse groove 410, filling the remaining space of the ferroelectric layer 630; and is also formed in the inner wall of the ferroelectric layer 630 of the first groove 330, filling the remaining space of the ferroelectric layer 630. At this point, both the first transverse groove 410 and the first groove 330 are filled.

[0083] S2104: Based on the interval between adjacent bit lines 300, remove the word line material 420, ferroelectric material, interface voltage reduction material and semiconductor material located in the first trench 310, so that the word line material 420, ferroelectric material, interface voltage reduction material and semiconductor material retained in the first transverse trench 410 respectively constitute word line 400, ferroelectric layer 630, interface voltage reduction layer 620 and semiconductor material layer.

[0084] Please see Figure 14 , Figure 14 This is a three-dimensional structural diagram of the structure obtained after removing word line material 420 located in the first trench 310 based on the interval between adjacent bit lines 300. At this time, the ferroelectric dielectric layer 630 is exposed, and a portion of the word line material 420 is laterally removed within the second dielectric layer 220, exposing a portion of the ferroelectric dielectric layer 630' in the first lateral trench 410, thereby allowing the word line material 420 retained within the first lateral trench 410 to constitute the word line 400. For example, the word line material 420 can be removed by dry etching in the first trench 330, exposing a portion of the ferroelectric dielectric layer 630' in the first trench 330; and the word line material 420 can be laterally removed within the second dielectric layer 220 by wet etching, exposing a portion of the ferroelectric dielectric layer 630' in the first lateral trench 410, thereby forming the word line 400 of the semiconductor structure.

[0085] In the above preparation method, by laterally removing word line material in the second dielectric layer to expose part of the ferroelectric dielectric layer in the first lateral trench, word lines of a semiconductor structure are formed, which can prepare for the subsequent process of forming separated semiconductor layers, thereby realizing the removal of parasitic channels between multiple memory cells connected to the same word line.

[0086] Please continue reading. Figure 15 , Figure 15This is a three-dimensional structural diagram of the structure obtained after removing the word line material 420 and ferroelectric material located in the first trench 310 based on the interval between adjacent bit lines 300. At this time, the ferroelectric layer 630 is removed in the first trench 330, exposing the interface voltage reduction layer 620. Specifically, wet etching can be used to remove the exposed ferroelectric layer 630 in the first trench 330, exposing the interface voltage reduction layer 620 located in the first trench 330; and wet etching can be used to laterally remove a portion of the exposed ferroelectric layer 630' within the second dielectric layer 220, exposing a portion of the interface voltage reduction layer 620' in the first lateral trench 410.

[0087] Please see Figure 16 , Figure 16 This is a three-dimensional structural diagram of the structure obtained after removing the word line material 420, ferroelectric material, and interface voltage reduction material located in the first trench 310 based on the interval between adjacent bit lines 300. At this time, the interface voltage reduction layer 620 is removed in the first trench 330, exposing the semiconductor material layer. Simultaneously, after removing the ferroelectric material and interface voltage reduction material based on the first trench 330, an opening is formed in the gate dielectric layer near the bit line. Specifically, wet etching can be used to remove the exposed interface voltage reduction layer 620 in the first trench 330, exposing the semiconductor material layer located in the first trench 330; and wet etching can be used to laterally remove a portion of the exposed interface voltage reduction layer 620' within the second dielectric layer 220, exposing a portion of the semiconductor material layer 610' in the first lateral trench 410.

[0088] Please see Figure 17 , Figure 17 This is a three-dimensional structural diagram illustrating the structure obtained by removing the word line material 420, ferroelectric material, interface voltage reduction material, and semiconductor material located within the first trench 310 based on the interval between adjacent bit lines 300, such that the word line material 420, ferroelectric material, interface voltage reduction material, and semiconductor material retained within the first lateral trench 410 respectively constitute a word line 400, a ferroelectric layer 630, an interface voltage reduction layer 620, and a semiconductor material layer. Specifically, wet etching can be used to remove the exposed semiconductor material layer within the first trench 330, exposing the first dielectric layer 210 located within the first trench 330; and wet etching can be used to laterally remove a portion of the exposed semiconductor material layer 610' within the second dielectric layer 220, exposing a portion of the first dielectric layer 210' within the first lateral trench 410.

[0089] In the above preparation method, by sequentially removing the ferroelectric dielectric layer, the interface voltage reduction layer and the semiconductor layer in the first trench to expose the first dielectric layer, it can prepare for the subsequent process of forming the separated semiconductor layer, thereby realizing the removal of parasitic channels between multiple memory cells connected to the same word line.

[0090] S2106: A third dielectric layer is filled in the gap between adjacent bit lines.

[0091] Please see Figure 18 , Figure 18 This is a three-dimensional structural diagram of the structure obtained in S2106. For example, a third dielectric layer 230 can be formed in multiple first trenches 330 using atomic layer deposition processes, etc. The third dielectric layer 230 can be silicon oxide, etc. Figure 18 As shown, the third dielectric layer 230 extends along the first direction D1 and is located between bit lines 300 along the second direction D2.

[0092] S2108: A first hole 640 extending in the first direction is formed in the third dielectric layer 230.

[0093] Please see Figure 19 , Figure 19 This is a three-dimensional structural diagram of the structure obtained in S2108. For example, a first hole 640 can be formed in the third dielectric layer 230 using dry etching. The first hole 640 extends along a first direction D1 and can be arranged in multiple rows and columns along a second direction D2 and a third direction D3.

[0094] S2110: Based on each first hole 640, an isolation semiconductor material layer is etched to form a semiconductor layer 610 of multiple memory cells; a fourth dielectric layer 240 is filled in the first hole 640.

[0095] Please see Figures 20-22 , Figure 21 and Figure 22 This is a three-dimensional structural diagram of the structure obtained in S2110. For example, firstly, the third dielectric layer 230 is laterally etched in the first hole 640 to form the second hole 650, exposing the semiconductor material layer, forming a structure as shown in the diagram. Figure 20 The structure shown, exemplarily, employs wet etching to laterally etch the third dielectric layer 230. After exposing the semiconductor material layer, lateral etching of the semiconductor material layer continues to complete the disconnection of the semiconductor material layer, i.e., the disconnection of the polysilicon in the second direction D2. Figure 21 and Figure 22 All images show the structure after the polysilicon has been completely broken. For clarity, cross-sections at different heights along the first direction D1 are shown. (The text then abruptly shifts to a different topic:) ...from... Figure 22 As can be clearly seen, the polysilicon in the second dielectric layer 220 is spaced apart to form semiconductor layers 610 for multiple memory cells.

[0096] In some embodiments, please refer to Figure 23After etching the isolation semiconductor material layer based on each first hole 640 to form a semiconductor layer 610 with multiple memory cells, a fourth dielectric layer 240 is filled into the first hole 640. Specifically, a third dielectric layer 230 is first etched laterally in the first hole 640 to form a second hole 650, exposing the semiconductor material layer. After etching the isolation semiconductor material layer to form a semiconductor layer 610 with multiple memory cells, the fourth dielectric layer 240 is filled into the second hole 650. Figure 23 This is a three-dimensional structural diagram of the structure obtained by filling the second hole 650. For example, the second hole 650 is filled using a process such as atomic layer deposition, and the filling material can be silicon oxide or the like.

[0097] In this embodiment, the parasitic channels between multiple memory cells connected by etching the isolation semiconductor material layer based on each first hole 640 to form a semiconductor layer 610 for multiple memory cells are removed.

[0098] In some embodiments, please refer to Figure 24 , Figure 24 A flowchart of a method for fabricating a semiconductor structure according to another embodiment, wherein the method for fabricating the semiconductor structure further includes: S212-S214.

[0099] S212: A plurality of second trenches are formed on the side of the first transverse trench away from the first trench; the second trenches extend along the first direction and expose the semiconductor layer.

[0100] Please see Figure 25 , Figure 25 This is a three-dimensional structural diagram of the structure obtained in S212. For example, multiple second trenches 510 extending along the first direction D1 are formed in the stacked structure 200 by dry etching. The second trenches 510 penetrate the stacked structure 200, are arranged at intervals with multiple bit lines 300 along the third direction D3, and expose the semiconductor layer 610.

[0101] S214: A power line connecting the semiconductor layer is formed in the second trench.

[0102] Please see Figure 26 , Figure 26 This is a three-dimensional structural diagram of the structure obtained in S214. For example, titanium nitride (TiN) is filled using an atomic layer deposition process to form the power line 500. It is understood that the power line 500 also penetrates the stacked structure 200 and is spaced apart from multiple bit lines 300 along the third direction D3. The power line 500 is connected to the semiconductor layer 610.

[0103] According to various embodiments of the present disclosure, a second aspect of the present disclosure provides a semiconductor structure, the semiconductor structure including a substrate and a multilayer memory cell layer stacked on the substrate along a first direction perpendicular to the substrate; each memory cell layer includes a plurality of memory cells arranged in an array; the memory cell includes a semiconductor layer and a gate dielectric layer stacked together; the gate dielectric layer includes: an interface voltage reduction layer in contact with the semiconductor layer, and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer.

[0104] The semiconductor structure in the above embodiments includes a memory cell comprising a stacked semiconductor layer and a gate dielectric layer. The gate dielectric layer includes an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer. This enables a 1T0C memory structure, thereby improving the storage density of the memory device. Furthermore, by providing an interface voltage reduction layer in contact with the semiconductor layer and a ferroelectric dielectric layer located on the side of the interface voltage reduction layer away from the semiconductor layer, the interface voltage reduction layer in this embodiment is located between the channel layer and the ferroelectric dielectric layer. Therefore, the interface voltage reduction layer can replace the naturally formed low-k interface between the channel layer and the ferroelectric material to reduce the voltage at the interface, thus improving the device's durability.

[0105] In some embodiments, please refer to Figure 26 , Figure 26 The semiconductor structure, as described in some embodiments of this disclosure, further includes: a bit line 300 extending along a first direction D1; the bit line 300 being connected to a first end of a semiconductor layer 610 of a plurality of memory cells arranged along the first direction D1; a word line 400 extending along a second direction D2; a semiconductor layer of a plurality of memory cells arranged along the second direction D2 spaced around the outer wall of the word line 400, and a gate dielectric layer located between the semiconductor layer 610 and the word line 400, and a ferroelectric dielectric layer 630 contacting the word line 400; and a power line 500 extending along the first direction D1; the power line 500 being connected to a second end of the semiconductor layer 610 of a plurality of memory cells arranged along the first direction D1; wherein the first direction D1 intersects the second direction D2.

[0106] The semiconductor structure in the above embodiments, by providing a bit line extending along a first direction connected to a first end of the semiconductor layer, and providing a word line extending along a second direction, wherein the first direction intersects the second direction, can realize a vertical bit line structure, thereby reducing the parasitic capacitance between bit lines.

[0107] In some embodiments, a plurality of memory cells are arranged in columns along a first direction D1 and in rows along a second direction D2; wherein a word line 400 connects the ferroelectric dielectric layer 630 of a row of memory cells; wherein a bit line 300 connects the semiconductor layer 610 of a column of memory cells; or, a bit line 300 connects the semiconductor layers 610 of two adjacent columns of memory cells, and the two adjacent columns of memory cells are symmetrically arranged with the bit line 300 as the center; the gate dielectric layer has an opening on the side facing the bit line 300.

[0108] In some embodiments, a power line 500 of the semiconductor structure is connected to a semiconductor layer 610 of a row of memory cells, and the power line 500 is located on the side of the semiconductor layer 610 away from the bit line 300.

[0109] In some embodiments, the semiconductor structure includes at least one of the following features: the semiconductor layer 610 includes a polycrystalline silicon layer; the interface voltage reduction layer 620 includes a high-k material layer; and the ferroelectric layer 630 includes zirconium-doped hafnium oxide.

[0110] The materials of the ferroelectric dielectric layer 630 include, but are not limited to, hafnium zirconium oxide (HfZrO, also known as HZO, which includes hafnium, zirconium and oxygen), silicon-doped hafnium oxide (material containing hafnium, oxygen and silicon), germanium-doped hafnium oxide (material containing hafnium, oxygen and germanium), aluminum-doped hafnium oxide (material containing hafnium, oxygen and aluminum), yttrium-doped hafnium oxide (material containing hafnium, oxygen and yttrium), lead zirconate titanate (material containing hafnium, including lead, zirconium and titanium), barium zirconate titanate (material containing barium, zirconium and titanium) and combinations thereof.

[0111] According to some embodiments, this disclosure also provides an electronic device, including a semiconductor structure prepared according to the above-described semiconductor structure fabrication method embodiments or the semiconductor structure in the above embodiments. The electronic device can be a mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized by, A substrate and a plurality of memory cell layers stacked along a first direction perpendicular to the substrate are included; Each of the memory cell layers includes a plurality of memory cells arranged in an array; The memory cell includes a semiconductor layer and a gate dielectric layer stacked; the gate dielectric layer includes an interface depressor layer in contact with the semiconductor layer and a ferroelectric dielectric layer on a side of the interface depressor layer away from the semiconductor layer.

2. The semiconductor structure of claim 1, wherein, Further comprising: Bit lines extending along the first direction; The bit lines are connected to first ends of the semiconductor layers of a plurality of the memory cells arranged along the first direction; Word lines extending along a second direction parallel to the substrate; The semiconductor layers of a plurality of the memory cells arranged along the second direction are spaced around an outer wall of the word lines, and the gate dielectric layers are between the semiconductor layers and the word lines, and the ferroelectric dielectric layers are in contact with the word lines; Power supply lines extending along the first direction; the power supply lines are connected to second ends of the semiconductor layers of a plurality of the memory cells arranged along the first direction; The first direction intersects the second direction.

3. The semiconductor structure of claim 2, wherein, The plurality of memory cells are arranged in columns along the first direction and in rows along the second direction; One of the bit lines is connected to the semiconductor layers of one column of the memory cells; or, one of the bit lines is connected to the semiconductor layers of two adjacent columns of the memory cells, and the two adjacent columns of the memory cells are symmetrically arranged with the bit line as the center; The gate dielectric layer has an opening on a side facing the bit line.

4. The semiconductor structure of claim 3, wherein, One of the power supply lines is connected to the semiconductor layers of one column of the memory cells, and the power supply line is on a side of the semiconductor layers away from the bit line.

5. The semiconductor structure of any one of claims 1-4, wherein, At least one of the following features is included: The semiconductor layer includes a polysilicon layer; The interface depressor layer includes a high-k material layer; The ferroelectric dielectric layer includes zirconium-doped hafnium oxide.

6. A method of fabricating a semiconductor structure, characterized by, Providing a substrate; Forming a plurality of memory cell layers on the substrate; Each of the memory cell layers includes a plurality of memory cells arranged in an array; The memory cell includes a semiconductor layer and a gate dielectric layer stacked; the gate dielectric layer includes an interface depressor layer in contact with the semiconductor layer and a ferroelectric dielectric layer on a side of the interface depressor layer away from the semiconductor layer. The forming a plurality of memory cell layers on the substrate includes:

7. The method of claim 6, wherein, Forming a stack structure on the substrate, the stack structure including first dielectric layers and second dielectric layers alternately stacked along a first direction perpendicular to the substrate; Forming a first trench in the stack structure, the first trench penetrating the stack structure along the first direction and extending along a second direction intersecting the first direction; Based on the first trench, laterally etching the second dielectric layers to form first lateral trenches extending along the second direction; Sequentially stacking the semiconductor layers, the interface depressor layers and the ferroelectric dielectric layers of a plurality of the memory cells on inner sidewalls of the first lateral trenches; wherein the semiconductor layers of a plurality of the memory cells are spaced along the second direction. ​ 8. The method of claim 7, wherein, Before the forming the first lateral trench by laterally etching the second dielectric layer based on the first trench, the method further comprises: filling bit line material in the first trench; etching the bit line material to form a plurality of bit lines spaced apart along the second direction; the bit lines extend along the first direction; wherein the forming the first lateral trench by laterally etching the second dielectric layer based on the first trench comprises: laterally etching the second dielectric layer based on the spacing between adjacent bit lines to form the first lateral trench.

9. The method of claim 8, wherein, The sequentially stacking the semiconductor layer, the interface voltage-lowering layer and the ferroelectric dielectric layer on the inner sidewall of the first lateral trench to form a plurality of the memory cells comprises: sequentially depositing semiconductor material, interface voltage-lowering material, ferroelectric dielectric material and word line material on the inner sidewall of the first lateral trench and the outer sidewall of the bit lines; removing the word line material, the ferroelectric dielectric material, the interface voltage-lowering material and the semiconductor material located in the first trench based on the spacing between adjacent bit lines, such that the word line material, the ferroelectric dielectric material, the interface voltage-lowering material and the semiconductor material retained in the first lateral trench respectively constitute a word line, the ferroelectric dielectric layer, the interface voltage-lowering layer and the semiconductor material layer; filling a third dielectric layer in the spacing between adjacent bit lines; forming a first hole extending along the first direction in the third dielectric layer; etching the semiconductor material layer to be separated based on each of the first holes to respectively form the semiconductor layer of a plurality of the memory cells; filling a fourth dielectric layer in the first hole.

10. The method of any one of claims 7-9, wherein, The method further comprises: forming a plurality of second trenches on the side of the first lateral trench away from the first trench; the second trenches extend along the first direction and expose the semiconductor layer; forming a power line connecting the semiconductor layer in the second trench.

11. An electronic device, comprising: A semiconductor structure comprising any one of the semiconductor structures of claims 1-5, or a semiconductor structure prepared based on the preparation method of any one of claims 6-10.

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