Semiconductor structure and forming method thereof
By designing word lines at the tail and middle portions of the semiconductor structure and employing a specific combination of work function layers and metal layers, the problem of enhanced coupling between adjacent word lines is solved, thereby improving the performance and integration density of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2026-03-10
AI Technical Summary
As semiconductor structures shrink, the distance between adjacent word lines decreases, leading to enhanced coupling and impacting performance, particularly in terms of signal interference and word line bending.
The word lines in the semiconductor structure are designed to include a tail section and a middle section. The top surface of the tail section is lower than that of the middle section and they are connected by a contact structure to reduce stress and bending. A specific combination of work function layers and metal layers is used to reduce coupling.
It effectively reduces signal interference and electrical short circuits between character lines, and improves the integration and performance of the semiconductor structure.
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Figure CN121645847A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure and a method for forming the same. Background Technology
[0002] Word lines are widely used in semiconductor structures, such as in dynamic random-access memory (DRAM) devices. However, as semiconductor structures are manufactured smaller, the distance between adjacent word lines also decreases, leading to stronger coupling between them. If the distance between adjacent word lines becomes too small, excessive coupling can impair the performance of the semiconductor structure, for example, by increasing signal interference between adjacent word lines. Furthermore, the tail portions of word lines typically experience greater stress and are prone to bending. When the distance between adjacent word lines decreases, and when word lines bend due to stress, the distance between them may be less than expected, resulting in coupling problems. Therefore, it is necessary to develop a novel semiconductor structure incorporating improved word lines and a new method for forming this semiconductor structure. Summary of the Invention
[0003] This invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first word line, and a first contact structure. The first word line extends along a first direction on the substrate, wherein the first word line includes a first tail portion, a second tail portion, and a first intermediate portion. The first intermediate portion is located between the first tail portion and the second tail portion, wherein the top surface of the first tail portion and the top surface of the second tail portion are lower than the top surface of the first intermediate portion, and the length of the second tail portion is greater than the length of the first tail portion. The first contact structure is located on the first tail portion of the first word line.
[0004] In some implementations, the horizontal distance from the boundary of the first tail portion closest to the second tail portion to the first contact structure is 100 nm to 1000 nm.
[0005] In some embodiments, the first intermediate portion includes a high power function layer and a low power function layer disposed on the high power function layer, wherein the power function of the high power function layer is greater than the power function of the low power function layer, the first tail portion is a power function layer having a power function greater than the power function of the low power function layer, and the second tail portion is a power function layer having a power function greater than the power function of the low power function layer.
[0006] In some embodiments, the first intermediate portion includes a metal-containing layer and a silicon-containing conductive layer disposed on the metal-containing layer, the first tail portion includes a metal-containing layer in direct contact with the first contact structure, and the second tail portion includes a metal-containing layer.
[0007] In some embodiments, a first top surface of the substrate around a first intermediate portion is higher than a second top surface of the substrate around a first tail portion and a third top surface of the substrate around a second tail portion.
[0008] In some embodiments, the semiconductor structure further includes a second word line and a second contact structure. The second word line is adjacent to the first word line and extends along a first direction on the substrate, wherein the second word line includes a third tail portion, a fourth tail portion, and a second intermediate portion. The third tail portion is adjacent to the first tail portion of the first word line. The fourth tail portion is adjacent to the second tail portion of the first word line. The second intermediate portion is located between the third and fourth tail portions, wherein the top surfaces of the third and fourth tail portions are lower than the top surface of the second intermediate portion, and the length of the third tail portion is greater than the length of the fourth tail portion. The second contact structure is located on the fourth tail portion of the second word line.
[0009] In some implementations, the virtual line passes through a point on the first contact structure and the third tail portion in a second direction perpendicular to the first direction, and the horizontal distance from the boundary of the third tail portion closest to the fourth tail portion to this point is 200 nm to 3000 nm.
[0010] In some implementations, the first character line, the first contact structure, the second character line, and the second contact structure are grouped together, and the semiconductor structure also includes multiple groups, each identical to this group, on the substrate, and each of these groups is aligned with this group.
[0011] The present invention also provides a method for forming a semiconductor structure. The method includes the following operations: forming a first word line extending along a first direction on a substrate; forming a mask on a first intermediate portion of the first word line and exposing a first end and a second end of the first word line, wherein the length of the second end exposed by the mask is greater than the length of the first end exposed by the mask, and the first intermediate portion is between the first end and the second end; etching a portion of the first end and a portion of the second end of the first word line exposed by the mask to form a first tail portion and a second tail portion of the first word line, respectively, wherein the top surface of the first tail portion and the top surface of the second tail portion are lower than the top surface of the first intermediate portion; and forming a first contact structure on the first tail portion.
[0012] In some implementations, the length of the second tail portion is greater than the length of the first tail portion.
[0013] In some embodiments, the first end includes a high power function layer and a low power function layer disposed on the high power function layer, and the power function of the high power function layer is greater than the power function of the low power function layer; when etching the portion of the first end of the first character line exposed by the mask, this portion includes the low power function layer; and when forming the first contact structure, the first contact structure is in direct contact with the high power function layer.
[0014] In some implementations, etching a portion of the substrate surrounding the first end is also included when etching a portion of the first end of the first character line exposed by the etch mask.
[0015] In some embodiments, the method further includes the following operations: forming a second character line extending along a first direction on a substrate; forming a mask on a second intermediate portion of the second character line and exposing a third end and a fourth end of the second character line, wherein the length of the third end exposed by the mask is greater than the length of the fourth end exposed by the mask, the second intermediate portion lies between the third end and the fourth end, and the third end and the fourth end are respectively adjacent to the first end and the second end of the first character line; etching a portion of the third end and a portion of the fourth end of the second character line exposed by the mask to form a third tail portion and a fourth tail portion of the second character line, respectively.
[0016] In some embodiments, the method further includes forming a second contact structure on the fourth tail portion.
[0017] In some implementations, the mask has multiple serrated edges in the first direction. Attached Figure Description
[0018] The invention can be more fully understood by referring to the accompanying drawings when reading the detailed embodiments described below.
[0019] Figure 1 This is a top view of a semiconductor structure according to some embodiments of the present invention.
[0020] Figure 2A This is according to some embodiments of the present invention. Figure 1 The semiconductor structure in the diagram is shown in a cross-sectional view along line A-A'.
[0021] Figure 2B This is according to some embodiments of the present invention. Figure 1 The semiconductor structure in the diagram is shown in a cross-sectional view along line B-B' or line b-b'.
[0022] Figure 2C This is according to some embodiments of the present invention. Figure 1 The semiconductor structure in the diagram is shown in a cross-sectional view along line C-C' or line c-c'.
[0023] Figure 2D This is according to some embodiments of the present invention. Figure 1 The semiconductor structure in the diagram is shown in a cross-sectional view along line D-D' or line d-d'.
[0024] Figure 3 This is a flowchart of a method for forming a semiconductor structure according to some embodiments of the present invention.
[0025] Figure 4A , Figure 5A , Figure 6A , Figure 8A , Figure 9A and Figure 10A This is a structure formed during the process of forming a semiconductor structure according to some embodiments of the present invention, which, along such... Figure 1 The cross-sectional view of line A-A' shown.
[0026] Figure 4B , Figure 5B , Figure 6B , Figure 8B , Figure 9B and Figure 10B This is a structure formed during the process of forming a semiconductor structure according to some embodiments of the present invention, which, along such... Figure 1 The cross-sectional view of line B-B' or line b-b' shown.
[0027] Figure 4C , Figure 5C , Figure 6C , Figure 8C , Figure 9C and Figure 10C This is a structure formed during the process of forming a semiconductor structure according to some embodiments of the present invention, which, along such... Figure 1 The cross-sectional view of line C-C' or line c-c' shown.
[0028] Figure 4D , Figure 5D , Figure 6D , Figure 8D , Figure 9D and Figure 10D This is a structure formed during the process of forming a semiconductor structure according to some embodiments of the present invention, which, along such... Figure 1 The cross-sectional view of line D-D' or line d-d' shown.
[0029] Figure 7 This is a top view of the structure during the formation of a semiconductor structure according to some embodiments of the present invention. Detailed Implementation
[0030] To make the description of the present invention more detailed and complete, various aspects of the embodiments are described illustratively below, but this is not to limit the embodiments of the present invention to only one form. Embodiments of the present invention may be combined with or substituted for each other where advantageous, and other embodiments may be added without further explanation.
[0031] Furthermore, the present invention may use spatially relative terms, such as below and above, to describe the relationship between one element (or feature) and another element (or feature) in the figures. In addition to the directions depicted in the figures, the spatially relative terms are intended to cover different orientations of the device during use or operation. For example, the device may be oriented in other ways (e.g., rotated 90 degrees) and may be interpreted accordingly using spatially relative terms. In the present invention, unless otherwise stated, the same element symbols in different figures refer to the same or similar elements formed from the same or similar materials by the same or similar methods.
[0032] This invention provides a semiconductor structure, such as Figure 1 , Figure 2A , Figure 2B , Figure 2C and Figure 2D As shown. The semiconductor structure includes a substrate 11, a first word line 21, and a first contact structure 31. The first word line 21 extends on the substrate 11 along a first direction X, wherein the first word line 21 includes a first tail portion 211, a second tail portion 212, and a first intermediate portion 213. The first intermediate portion 213 is located between the first tail portion 211 and the second tail portion 212, wherein the top surface 211TS of the first tail portion 211 and the top surface 212TS of the second tail portion 212 are lower than the top surface 213TS of the first intermediate portion 213, and the length 212L of the second tail portion 212 is greater than the length 211L of the first tail portion 211. The first contact structure 31 is located on the first tail portion 211 of the first word line 21. The first word line 21 of the present invention reduces stress by including the first tail portion 211 and the second tail portion 212, thereby reducing the bending of the first word line 21. The semiconductor structure of the present invention will be described in more detail through the following embodiments.
[0033] In some embodiments, the semiconductor structure further includes a second character line 22 extending along a first direction X on the substrate 11 and a second contact structure 32 on the second character line 22. The second character line 22 is adjacent to the first character line 21. The design of the second character line 22 and the second contact structure 32 is substantially the same as that of the first character line 21 and the first contact structure 31, except that the second character line 22 and the second contact structure 32 are opposite to the first character line 21 and the first contact structure 31 along the first direction X on the substrate 11. Therefore, to simplify the number of figures, Figure 2B It can be Figure 1 A cross-sectional view along line B-B' or line b-b'. Figure 2C It can be Figure 1 A cross-sectional view along line C-C' or line c-c', and Figure 2D It can be Figure 1 A cross-sectional view along line D-D' or line d-d' is provided, noting the position of the line extending from the starting point to the ending point when reading the accompanying drawings. Furthermore, lines C-C', c-c', D-D', and d-d' of the present invention are along the first direction X.
[0034] The second character line 22 includes a third tail portion 221, a fourth tail portion 222, and a second intermediate portion 223 between the third tail portion 221 and the fourth tail portion 222. The third tail portion 221 is adjacent to and aligned with the first tail portion 211 of the first character line 21. The fourth tail portion 222 is adjacent to and aligned with the second tail portion 212 of the first character line 21. The top surface 221TS of the third tail portion 221 and the top surface 222TS of the fourth tail portion 222 are lower than the top surface 223TS of the second intermediate portion 223, and the length 221L of the third tail portion 221 is greater than the length 222L of the fourth tail portion 222. A second contact structure 32 is located on the fourth tail portion 222 of the second character line 22. The second character line 22 reduces stress by including the third tail portion 221 and the fourth tail portion 222, thereby reducing the bending of the second character line 22. Furthermore, since the design of the second character line 22 and the second contact structure 32 on the substrate 11 is opposite to that of the first character line 21 and the first contact structure 31 along the first direction X, when the second character line 22 is disposed around the first character line 21, the stress on the first character line 21 and the stress on the second character line 22 can be reduced, thereby preventing electrical short circuits and / or signal interference caused by the character lines becoming too close due to bending. In some embodiments, the second tail portion 212 of the first character line 21 does not have a contact structure extending vertically on and contacting the second tail portion 212 (e.g., no first contact structure 31), and the third tail portion 221 of the second character line 22 does not have a contact structure extending vertically on and contacting the third tail portion 221 (e.g., no second contact structure 32).
[0035] In some embodiments, the number of character lines and contact structures on the substrate 11 is not limited. For example, the number of first character lines 21, first contact structures 31, second character lines 22, and second contact structures 32 on the substrate 11 are each multiple, such as... Figure 1As shown, the first word line 21 and the first contact structure 31 are repeatedly and alternately arranged with the second word line 22 and the second contact structure 32 on the substrate 11. When the semiconductor structure includes a plurality of first word lines 21 and a plurality of first contact structures 31 respectively disposed on these first word lines 21, and includes a plurality of second word lines 22 and a plurality of second contact structures 32 respectively disposed on these second word lines 22, more components (e.g., transistor gates) can be integrated into the semiconductor structure to improve the performance of the semiconductor structure. In some embodiments, a first word line 21, a first contact structure 31, a second word line 22, and a second contact structure 32 can be considered as a group, and the semiconductor structure includes a plurality of groups, each identical to this group and aligned with this group on the substrate 11.
[0036] Continuing with the discussion of each first word line 21 and each second word line 22, in some embodiments, the first intermediate portion 213 of the first word line 21 and the second intermediate portion 223 of the second word line 22 are portions of the word line that include the gate of a transistor, and the word line is used to control the switching of the gate. Furthermore, the first tail portion 211 and the second tail portion 212 of the first word line 21 and the third tail portion 221 and the fourth tail portion 222 of the second word line 22 are dummy portions of the word line that do not include the gate of a transistor. However, the first tail portion 211 and the second tail portion 212 of the first word line 21 and the third tail portion 221 and the fourth tail portion 222 of the second word line 22 can be used to connect contact structures (e.g., the first tail portion 211 connects to the first contact structure 31 and the fourth tail portion 222 connects to the second contact structure 32). Since the tail portions of character lines are prone to bending, the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 are dummy portions to prevent damage caused by bending from affecting the performance of the character lines. Furthermore, when two character lines are positioned close to each other, the dummy portions prevent bent character lines from becoming too close, which could lead to electrical short circuits and / or signal interference. In some embodiments, the first tail portion 211, the first intermediate portion 213, and the second tail portion 212 are continuous along the first direction X, as are the third tail portion 221, the second intermediate portion 223, and the fourth tail portion 222 along the first direction X.
[0037] In some embodiments, the top surface 211TS of the first tail portion 211 and the top surface 212TS of the second tail portion 212 are lower than the top surface 213TS of the first intermediate portion 213, and the top surface 221TS of the third tail portion 221 and the top surface 222TS of the fourth tail portion 222 are lower than the top surface 223TS of the second intermediate portion 223 by removing multiple portions originally provided on the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 (e.g., in...). Figure 1 Within the area enclosed by the dashed line, a plurality of portions corresponding to the first intermediate portion 213 and the second intermediate portion 223 are retained (the method of forming the semiconductor structure according to the present invention is discussed below). In some embodiments, the top surface 211TS of the first tail portion 211, the top surface 212TS of the second tail portion 212, the top surface 221TS of the third tail portion 221, and the top surface 222TS of the fourth tail portion 222 are located on the same plane. In some embodiments, the top surface 213TS of the first intermediate portion 213 and the top surface 223TS of the second intermediate portion 223 are located on the same plane. In some embodiments, the height 213H of the first intermediate portion 213 is greater than the height 211H of the first tail portion 211 and the height 212H of the second tail portion 212, and the height 223H of the second intermediate portion 223 is greater than the height 221H of the third tail portion 221 and the height 222H of the fourth tail portion 222. In some embodiments, the heights 211H of the first tail portion 211, 212H of the second tail portion 212, 221H of the third tail portion 221, and 222H of the fourth tail portion 222 are the same. In some embodiments, the heights 213H of the first intermediate portion 213 and 223H of the second intermediate portion 223 are the same.
[0038] In some embodiments, the first intermediate portion 213 includes a high power function layer 2131H and a low power function layer 2132L disposed on the high power function layer 2131H, wherein the top surface 213TS of the first intermediate portion 213 is the top surface of the low power function layer 2132L, and the power function of the high power function layer 2131H is greater than the power function of the low power function layer 2132L. In some embodiments, the power function of the high power function layer 2131H is preferably 4.3 eV to 4.7 eV, for example, 4.3 eV, 4.4 eV, 4.5 eV, 4.6 eV, or 4.7 eV. In some embodiments, the power function of the low power function layer 2132L is preferably 4.0 eV to 4.4 eV, for example, 4.0 eV, 4.1 eV, 4.2 eV, 4.3 eV, or 4.4 eV. In some embodiments, the first tail portion 211 includes a work function layer 2111W, and the second tail portion 212 includes a work function layer 2121W, wherein the top surface 211TS of the first tail portion 211 is the top surface of the work function layer 2111W, and the top surface 212TS of the second tail portion 212 is the top surface of the work function layer 2121W. In some embodiments, the work function of the work function layer 2111W of the first tail portion 211 and the work function of the work function layer 2121W of the second tail portion 212 are greater than the work function of the low work function layer 2132L of the first intermediate portion 213. In some embodiments, the work function of the work function layer 2111W of the first tail portion 211 and the work function layer 2121W of the second tail portion 212 are independently and preferably 4.3eV to 4.7eV, for example 4.3eV, 4.4eV, 4.5eV, 4.6eV or 4.7eV.
[0039] In some embodiments, the second intermediate portion 223 includes a high power function layer 2231H and a low power function layer 2232L disposed on the high power function layer 2231H, wherein the top surface 223TS of the second intermediate portion 223 is the top surface of the low power function layer 2232L, and the power function of the high power function layer 2231H is greater than the power function of the low power function layer 2232L. In some embodiments, the power function of the high power function layer 2231H is preferably 4.3 eV to 4.7 eV, for example, 4.3 eV, 4.4 eV, 4.5 eV, 4.6 eV, or 4.7 eV. In some embodiments, the power function of the low power function layer 2232L is preferably 4.0 eV to 4.4 eV, for example, 4.0 eV, 4.1 eV, 4.2 eV, 4.3 eV, or 4.4 eV. In some embodiments, the third tail portion 221 includes a work function layer 2211W, and the fourth tail portion 222 includes a work function layer 2221W, wherein the top surface 221TS of the third tail portion 221 is the top surface of the work function layer 2211W, and the top surface 222TS of the fourth tail portion 222 is the top surface of the work function layer 2221W. In some embodiments, the work function of the work function layer 2211W of the third tail portion 221 and the work function of the work function layer 2221W of the fourth tail portion 222 are greater than the work function of the low work function layer 2232L of the second intermediate portion 223. In some embodiments, the work function of the work function layer 2211W of the third tail portion 221 and the work function layer 2221W of the fourth tail portion 222 are independently and preferably 4.3eV to 4.7eV, for example 4.3eV, 4.4eV, 4.5eV, 4.6eV or 4.7eV.
[0040] In some embodiments, the top surface of the high power function layer 2131H of the first intermediate portion 213, the top surface of the power function layer 2111W of the first tail portion 211, the top surface of the power function layer 2121W of the second tail portion 212, the top surface of the high power function layer 2231H of the second intermediate portion 223, the top surface of the power function layer 2211W of the third tail portion 221, and the top surface of the power function layer 2221W of the fourth tail portion 222 are located on the same plane.
[0041] In some embodiments, the work functions of the high work function layer 2131H of the first intermediate portion 213, the high work function layer 2231H of the second intermediate portion 223, the work function layer 2111W of the first tail portion 211, the work function layer 2121W of the second tail portion 212, the work function layer 2211W of the third tail portion 221, and the work function layer 2221W of the fourth tail portion 222 are the same. In some embodiments, the work functions of the low work function layer 2132L of the first intermediate portion 213 and the low work function layer 2232L of the second intermediate portion 223 are the same.
[0042] In some embodiments, the work function layer 2111W of the first tail portion 211, the high work function layer 2131H of the first intermediate portion 213, and the work function layer 2121W of the second tail portion 212 are continuous along the first direction X, and the work function layer 2211W of the third tail portion 221, the high work function layer 2231H of the second intermediate portion 223, and the work function layer 2221W of the fourth tail portion 222 are continuous along the first direction X.
[0043] In some embodiments, the low work function layer 2132L of the first intermediate portion 213 and the low work function layer 2232L of the second intermediate portion 223 serve as the gate of the transistor. In some embodiments, the work function layer 2111W of the first tail portion 211 is in direct contact with the first contact structure 31, and the work function layer 2221W of the fourth tail portion 222 is in direct contact with the second contact structure 32.
[0044] In some embodiments, the first intermediate portion 213 includes a metal-containing layer 2131M and a silicon-containing conductive layer 2132S disposed on the metal-containing layer 2131M, wherein the top surface 213TS of the first intermediate portion 213 is the top surface of the silicon-containing conductive layer 2132S. In some embodiments, the metal-containing layer 2131M of the first intermediate portion 213 includes tungsten, and the silicon-containing conductive layer 2132S of the first intermediate portion 213 includes polysilicon, such as polysilicon doped with an N-type conductive dopant. In some embodiments, the first tail portion 211 includes a metal-containing layer 2111M, and the second tail portion 212 includes a metal-containing layer 2121M, wherein the top surface 211TS of the first tail portion 211 is the top surface of the metal-containing layer 2111M of the first tail portion 211, and the top surface 212TS of the second tail portion 212 is the top surface of the metal-containing layer 2121M of the second tail portion 212. In some embodiments, the metal-containing layer 2111M of the first tail portion 211 and the metal-containing layer 2121M of the second tail portion 212 include tungsten.
[0045] In some embodiments, the second intermediate portion 223 includes a metal-containing layer 2231M and a silicon-containing conductive layer 2232S disposed on the metal-containing layer 2231M, wherein the top surface 223TS of the second intermediate portion 223 is the top surface of the silicon-containing conductive layer 2232S. In some embodiments, the metal-containing layer 2231M of the second intermediate portion 223 includes tungsten, and the silicon-containing conductive layer 2232S of the second intermediate portion 223 includes polycrystalline silicon, such as polycrystalline silicon doped with an N-type conductive dopant. In some embodiments, the third tail portion 221 includes a metal-containing layer 2211M, and the fourth tail portion 222 includes a metal-containing layer 2221M, wherein the top surface 221TS of the third tail portion 221 is the top surface of the metal-containing layer 2211M of the third tail portion 221, and the top surface 222TS of the fourth tail portion 222 is the top surface of the metal-containing layer 2221M of the fourth tail portion 222. In some embodiments, the metal layer 2211M of the third tail portion 221 and the metal layer 2221M of the fourth tail portion 222 include tungsten.
[0046] In some embodiments, the top surface of the metal-containing layer 2131M of the first intermediate portion 213, the top surface of the metal-containing layer 2111M of the first tail portion 211, the top surface of the metal-containing layer 2121M of the second tail portion 212, the top surface of the metal-containing layer 2231M of the second intermediate portion 223, the top surface of the metal-containing layer 2211M of the third tail portion 221, and the top surface of the metal-containing layer 2221M of the fourth tail portion 222 are on the same plane.
[0047] In some embodiments, the metal-containing layer 2111M of the first tail portion 211, the metal-containing layer 2131M of the first intermediate portion 213, and the metal-containing layer 2121M of the second tail portion 212 are continuous along the first direction X, and the metal-containing layer 2211M of the third tail portion 221, the metal-containing layer 2231M of the second intermediate portion 223, and the metal-containing layer 2221M of the fourth tail portion 222 are continuous along the first direction X.
[0048] In some embodiments, the silicon-containing conductive layer 2132S of the first intermediate portion 213 and the silicon-containing conductive layer 2232S of the second intermediate portion 223 serve as the gate of the transistor. In some embodiments, the metal-containing layer 2111M of the first tail portion 211 is in direct contact with the first contact structure 31, and the metal-containing layer 2221M of the fourth tail portion 222 is in direct contact with the second contact structure 32.
[0049] In the first character line 21, the length 212L of the second tail portion 212 along the first direction X is greater than the length 211L of the first tail portion 211 along the first direction X. In the second character line 22, the length 221L of the third tail portion 221 along the first direction X is greater than the length 222L of the fourth tail portion 222 along the first direction X. In the semiconductor structure of the present invention (described in detail later), in an embodiment where portions originally disposed on the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 are removed, the length 212L of the second tail portion 212 being greater than the length 211L of the first tail portion 211 and the length 221L of the third tail portion 221 being greater than the length 222L of the fourth tail portion 222 originates from the fact that the length of the portion originally disposed on the second tail portion 212 is greater than the length of the portion originally disposed on the first tail portion 211, and the length of the portion originally disposed on the third tail portion 221 is greater than the length of the portion originally disposed on the fourth tail portion 222.
[0050] In some embodiments, the horizontal distance H1 from the boundary 211B of the first tail portion 211 closest to the second tail portion 212 to the center of the first contact structure 31 along the first direction X is preferably 100 nm to 1000 nm, for example, 100 nm, 250 nm, 500 nm, 750 nm, or 1000 nm. In some embodiments, the boundary 212B of the second tail portion 212 closest to the first tail portion 211 is closer to the center of the first character line 21 than the boundary 211B of the first tail portion 211. In some embodiments, the horizontal distance H4 from the boundary 222B of the fourth tail portion 222 closest to the third tail portion 221 to the center of the second contact structure 32 along the first direction X is preferably 100 nm to 1000 nm, for example, 100 nm, 250 nm, 500 nm, 750 nm, or 1000 nm. In some embodiments, the boundary 221B of the third tail portion 221 closest to the fourth tail portion 222 is closer to the center of the second character line 22 than the boundary 222B of the fourth tail portion 222. In some embodiments, the horizontal distance H1 is equal to the horizontal distance H4.
[0051] In some embodiments, the virtual line 42 passes through the center of the second contact structure 32 and the point 212P of the second tail portion 212 along the second direction Y perpendicular to the first direction X along the substrate 11, and the horizontal distance H2 from the boundary 212B of the second tail portion 212 to the point 212P along the first direction X is preferably 200nm to 3000nm, such as 200nm, 600nm, 1000nm, 1400nm, 1800nm, 2200nm, 2600nm or 3000nm. In some embodiments, the virtual line 41 passes along the second direction Y through the center of the first contact structure 31 and the point 221P of the third tail portion 221, and the horizontal distance H3 from the boundary 221B of the third tail portion 221 to the point 221P along the first direction X is preferably 200nm to 3000nm, for example 200nm, 600nm, 1000nm, 1400nm, 1800nm, 2200nm, 2600nm, or 3000nm. In some embodiments, the horizontal distance H2 is equal to the horizontal distance H3. In some embodiments, the horizontal distances H2 and H3 are greater than the horizontal distances H1 and H4. In some embodiments, the boundary 212B of the second tail portion 212 is closer to the virtual connection line between the center of the first character line 21 and the center of the second character line 22 than the boundary 222B of the fourth tail portion 222. In some implementations, the boundary 221B of the third tail portion 221 is closer to the virtual connection line between the center of the first character line 21 and the center of the second character line 22 than the boundary 211B of the first tail portion 211.
[0052] In some embodiments, the first contact structure 31 and the second contact structure 32 are conductive and extend vertically away from the substrate 11 to connect the first character line 21 and the second character line 22 to elements disposed on any suitable layer on the first character line 21 and the second character line 22. In some embodiments, the first contact structure 31 includes a first contact plug 311 and a first wire 312 disposed on the first contact plug 311, and the second contact structure 32 includes a second contact plug 321 and a second wire 322 disposed on the second contact plug 321. In some embodiments, the first contact plug 311, the first wire 312, the second contact plug 321, and the second wire 322 comprise any suitable conductive material. In embodiments where there are multiple first contact structures 31 and second contact structures 32, these first contact structures 31 and these second contact structures 32 are arranged in a zigzag pattern on the substrate 11.
[0053] Next, substrate 11 will be discussed. Substrate 11 can be any suitable substrate. In some embodiments, substrate 11 is a semiconductor substrate and includes a semiconductor material. In some embodiments, the semiconductor material includes elemental semiconductor materials, such as carbon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, tin, sulfur, selenium, tellurium, etc.; compound semiconductor materials, such as silicon carbide, boron nitride, aluminum nitride, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, etc.; alloy semiconductor materials, such as SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, etc.; or combinations thereof. In some embodiments, the first word line 21 and the second word line 22 are embedded in substrate 11.
[0054] In some embodiments, the substrate 11 includes an isolation region 111 and a plurality of active regions 112, wherein the isolation region 111 separates the active regions 112 from each other, such as Figure 1 As shown. In some embodiments, each of the active regions 112 includes an N-type conductive dopant or a P-type conductive dopant. In some embodiments, the isolation region 111 includes an electrically insulating material, such as silicon dioxide.
[0055] In some embodiments, the active region 112 includes a long active region 1121 and a short active region 1122, wherein the length 1121L of each of the long active regions 1121 is greater than the length 1122L of each of the short active regions 1122. A first tail portion 211 and a second tail portion 212 of the first character line 21, and a third tail portion 221 and a fourth tail portion 222 of the second character line 22 are disposed on the long active region 1121, and a first intermediate portion 213 of the first character line 21 and a second intermediate portion 223 of the second character line 22 are disposed on the short active region 1122. When the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 are disposed on the long active region 1121 having a length 1121L greater than the length 1122L of the short active region 1122, the first character line 21 and the second character line 22 can be further stress-reduced. In some implementations, the long active region 1121 surrounds the short active region 1122.
[0056] In some embodiments, the top surface TS213 of the portion of substrate 11 surrounding the first intermediate portion 213 is higher than the top surface TS211 of the portion of substrate 11 surrounding the first tail portion 211 and the top surface TS212 of the portion of substrate 11 surrounding the second tail portion 212, and the top surface TS223 of the portion of substrate 11 surrounding the second intermediate portion 223 is higher than the top surface TS221 of the portion of substrate 11 surrounding the third tail portion 221 and the top surface TS222 of the portion of substrate 11 surrounding the fourth tail portion 222. In some embodiments (see...) Figure 2B In some embodiments, when forming the semiconductor structure of the present invention (described in detail later), when removing portions originally disposed on the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222, portions of the substrate 11 surrounding the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 may also be removed together, such that the top surface of the remaining portion of the substrate 11 surrounding the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 is lower than the top surface of the portion of the substrate 11 surrounding the first intermediate portion 213 and the second intermediate portion 223. Furthermore, due to the different materials of the active region 112 and the isolation region 111, after removing portions of the substrate 11 surrounding the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222, the top surface of the active region 112 may be lower than the top surface of the isolation region 111 in the remaining portions of the substrate 11 surrounding the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222. Additionally, in embodiments where there are multiple first character lines 21, first contact structures 31, second character lines 22, and second contact structures 32, the height difference of the top surface of the substrate 11 causes the substrate 11 to have serrated sidewalls 11JS (see reference) along the first direction X and between the middle portions (e.g., the first middle portions 213 and the second middle portions 223) and the tail portions (e.g., the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222). Figure 1 ).
[0057] In some embodiments, the semiconductor structure further includes a hard mask layer 51 on portions of the substrate 11 surrounding the first intermediate portion 213 and the second intermediate portion 223. The hard mask layer 51 can be used as an etching mask to form trenches in the substrate 11, and thus fill the trenches with the first word line 21 and the second word line 22 (described in detail later). In some embodiments, when forming the semiconductor structure of the present invention (described in detail later), when portions originally disposed on the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 are removed, portions of the hard mask layer 51 originally disposed on the substrate 11 surrounding the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222 are also removed. In some embodiments, the hard mask layer 51 comprises silicon nitride.
[0058] In some embodiments, the semiconductor structure further includes a dielectric layer 52 between the first word line 21 and the substrate 11 and between the second word line 22 and the substrate 11 to provide electrical isolation. In some embodiments, the dielectric layer 52 comprises any suitable dielectric material, such as silicon oxide.
[0059] In some embodiments, the semiconductor structure further includes a dielectric layer 53 on the first word line 21 and the second word line 22 to provide electrical isolation. In some embodiments, the dielectric layer 53 is in direct contact with portions of the substrate 11 surrounding the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222, and is separated from portions of the substrate 11 surrounding the first intermediate portion 213 and the second intermediate portion 223 by the dielectric layer 52. In some embodiments, the semiconductor structure further includes an interlayer dielectric layer 54 on the dielectric layer 53. In some embodiments, the first contact structure 31 and the second contact structure 32 penetrate the dielectric layer 53 and the interlayer dielectric layer 54. In some embodiments, the dielectric layer 53 and the interlayer dielectric layer 54 comprise any suitable dielectric material, such as silicon oxide.
[0060] The present invention also provides a method 60 for forming the above-described semiconductor structure. Figure 3 In this context, method 60 includes operations 61 to 64. (In reading...) Figure 3 Please refer to other relevant information. Figure 1 , Figures 2A to 2D and Figures 4A to 10DOperation 61 includes forming a first character line 21 extending along a first direction X on the substrate 11. Operation 62 includes forming a mask 72 on a first intermediate portion 213 of the first character line 21, exposing a first end 211' and a second end 212' of the first character line 21, wherein the length 212'L of the second end 212' exposed by the mask 72 is greater than the length 211'L of the first end 211' exposed by the mask 72, and the first intermediate portion 213 is between the first end 211' and the second end 212'. Operation 63 includes etching a portion of the first end 211' and a portion of the second end 212' of the first character line 21 exposed by the mask 72 to form a first tail portion 211 and a second tail portion 212 of the first character line 21, respectively, wherein the top surface 211TS of the first tail portion 211 and the top surface 212TS of the second tail portion 212 are lower than the top surface 213TS of the first intermediate portion 213. Operation 64 includes forming a first contact structure 31 on the first tail portion 211. The method of the present invention will be described in detail below by way of some embodiments.
[0061] Reference Figure 4A , Figure 4B , Figure 4C and Figure 4D Prior to performing operation 61, in some embodiments, method 60 further includes receiving a substrate 11 comprising an isolation region 111 and an active region 112, wherein the active region 112 comprises a long active region 1121 and a short active region 1122, and in some embodiments, method 60 further includes forming a hard mask layer 51 on the substrate 11 by any suitable deposition method, such as by chemical vapor deposition or physical vapor deposition. It should be noted that... Figure 4A , Figure 4B , Figure 4C and Figure 4D Some portions of the substrate 11 and some portions of the hard mask layer 51 shown may be removed in subsequent operations to form Figure 1 and Figures 2A to 2D The first character line 21 and the second character line 22 are shown.
[0062] Reference Figure 5A , Figure 5B , Figure 5C and Figure 5D Prior to performing operation 61, in some embodiments, method 60 further includes etching multiple portions of the substrate 11 and the hard mask layer 51 by any suitable etching method, such as dry etching or wet etching, to form trenches 71. In subsequent operations, trenches 71 are used to fill the first character line 21 and the second character line 22; therefore, in some embodiments, the location of trenches 71 corresponds to... Figure 1 and Figures 2A to 2DThe positions of the first character line 21 and the second character line 22 shown are, for example, the trench 71 extending along the first direction X. In some embodiments, the etching of the hard mask layer 51 is performed by using a patterned photoresist layer (not shown) on the hard mask layer 51 to transfer the pattern of the patterned photoresist layer into the hard mask layer 51, and the etching of the substrate 11 is performed by using the hard mask layer 51 having a pattern transferred from the patterned photoresist layer as an etching mask to further transfer the pattern into the substrate 11. Since the materials of the active region 112 and the isolation region 111 may be different, in embodiments where the etching rate of the isolation region 111 is greater than the etching rate of the active region 112, the etching depth of the isolation region 111 exposed by the trench 71 will be greater than the etching depth of the active region 112 exposed by the trench 71 (see reference). Figure 5A , Figure 5C and Figure 5D It should be noted that when forming the first tail portion 211 and the second tail portion 212 of the first character line 21, and the third tail portion 221 and the fourth tail portion 222 of the second character line 22, Figure 5B Parts of the substrate 11 and the hard mask layer 51 shown may be further removed in subsequent operations.
[0063] Reference Figure 6A , Figure 6B , Figure 6C and Figure 6D In operation 61, the first character line 21 and, in some embodiments, the second character line 22, can be formed in the trench 71 by any suitable deposition method, such as chemical vapor deposition or physical vapor deposition. After performing operation 61, Figure 1 and Figure 2A The first middle portion 213 of the first character line 21 shown is formed, and in some embodiments, Figure 1 and Figure 2AThe second middle portion 223 of the second character line 22 shown is formed. It should be noted that after operation 61 is performed and before subsequent operations are performed, the tail portions of the first character line 21 and the second character line 22 are the precursors of the first tail portion 211, the second tail portion 212, the third tail portion 221 and the fourth tail portion 222, namely the first end 211', the second end 212', the third end 221' and the fourth end 222'. For example, the first end 211' includes a work function layer 2111W or a metal layer 2111M, and includes a layer 2112' on the work function layer 2111W or the metal layer 2111M; the second end 212' includes a work function layer 2121W or a metal layer 2121M, and includes a layer 2122' on the work function layer 2121W or the metal layer 2121M; the third end 221' includes a work function layer 2211W or a metal layer 2211M, and includes a layer 2212' on the work function layer 2211W or the metal layer 2211M; and the fourth end 222' includes a work function layer 2221W or a metal layer 2221M, and includes a layer 2222' on the work function layer 2221W or the metal layer 2221M. The layers 2112' of the first end 211', 2122' of the second end 212', 2212' of the third end 221', and 2222' of the fourth end 222' will be removed in subsequent operations to form the first tail portion 211, the second tail portion 212, the third tail portion 221, and the fourth tail portion 222, respectively.
[0064] In some embodiments, the layers 2112' of the first end 211', 2122' of the second end 212', 2212' of the third end 221', and 2222' of the fourth end 222' are low work function layers, and their work functions are respectively less than the work functions of work function layers 2111W, 2121W, 2211W, and 2221W. In some embodiments, the work functions of layers 2112', 2122', 2212', and 2222' are independently and preferably 4.0 eV to 4.4 eV, for example 4.0 eV, 4.1 eV, 4.2 eV, 4.3 eV, or 4.4 eV. In some embodiments, the layer 2112' of the first end 211', the layer 2122' of the second end 212', the layer 2212' of the third end 221', and the layer 2222' of the fourth end 222' are silicon-containing conductive layers including polysilicon, such as polysilicon doped with N-type conductive dopant.
[0065] Continue to refer to Figure 6A , Figure 6B , Figure 6C and Figure 6DIn some embodiments, method 60 further includes forming a dielectric layer 52 on the substrate 11 by any suitable deposition method, such as chemical vapor deposition or physical vapor deposition, before performing operation 61 to form the first character line 21 and the second character line 22. It should be noted that during the formation of the first tail portion 211 and the second tail portion 212 of the first character line 21 and the third tail portion 221 and the fourth tail portion 222 of the second character line 22, Figure 6B A portion of the dielectric layer 52 shown may be removed in subsequent operations.
[0066] Reference Figure 7 , Figure 8A , Figure 8B , Figure 8C and Figure 8D In operation 62, a mask 72 is formed on the first intermediate portion 213 of the first character line 21, exposing the first end 211' and the second end 212' of the first character line 21. In some embodiments, the mask 72 is further formed on the second intermediate portion 223 of the second character line 22, exposing the third end 221' and the fourth end 222' of the second character line 22. In subsequent operations, the portion covered by the mask 72 is not removed, but the portion exposed through the opening of the mask 72 (e.g., Figure 7The area enclosed by the dashed line will be removed in subsequent operations; for example, portions of layers 2112', 2122', 2212', and 2222', as well as portions of the substrate 11, hard mask layer 51, and dielectric layer 52 surrounding layers 2112', 2122', 2212', and 2222', may be removed. In some embodiments, the mask 72 is formed by any suitable deposition method, such as chemical vapor deposition or physical vapor deposition. In some embodiments, the mask 72 has a serrated edge 72JE between the middle portions (e.g., the first middle portions 213 and the second middle portions 223) and the tail portions (e.g., the first end 211', the second end 212', the third end 221', and the fourth end 222') along the first direction X and located on the character line. The length 212'L of the second end 212' exposed by the mask 72 (corresponding to the length 212L of the second tail portion 212) is greater than the length 211'L of the first end 211' exposed by the mask 72 (corresponding to the length 211L of the first tail portion 211). The length 221'L of the third end 221' exposed by the mask 72 (corresponding to the length 221L of the third tail portion 221) is greater than the length 222'L of the fourth end 222' exposed by the mask 72 (corresponding to the length 222L of the fourth tail portion 222). In some embodiments, the mask 72 includes a photoresist and can be patterned by photolithography. In some embodiments, the mask 72 is a hard mask and can include any suitable hard mask material, such as silicon nitride. In embodiments where the mask 72 is a hard mask, the hard mask can be patterned by any suitable patterned photoresist layer disposed on the hard mask.
[0067] Continue to refer to Figure 7 , Figure 8A , Figure 8B , Figure 8C and Figure 8DIn operation 63, the layers 2112' of the first end 211' and 2122' of the second end 212' exposed by the mask 72 are etched to form the first tail portion 211 and the second tail portion 212, respectively. In some embodiments, the layers 2212' of the third end 221' and 2222' of the fourth end 222' exposed by the mask 72 are etched to form the third tail portion 221 and the fourth tail portion 222, respectively. In some embodiments, when etching portions of the first end 211', the second end 212', the third end 221', and the fourth end 222' (i.e., etching layers 2112', 2122', 2212', and 2222'), portions of the substrate 11, the hard mask layer 51, and the dielectric layer 52 surrounding these portions of the first end 211', the second end 212', the third end 221', and the fourth end 222' (i.e., layers 2112', 2122', 2212', and 2222') may also be etched. Since the materials of the active region 112 and the isolation region 111 may be different, in embodiments where the etching rate of the active region 112 is greater than that of the isolation region 111, after etching a portion of the substrate 11 surrounding the first end 211', the second end 212', the third end 221', and the fourth end 222', in the remaining portion of the substrate 11 surrounding the first tail end portion 211, the second tail end portion 212, the third tail end portion 221, and the fourth tail end portion 222, the top surface of the active region 112 will be lower than the top surface of the isolation region 111 (see reference). Figure 8B In some implementations, etching can be performed by any suitable etching method, such as dry etching or wet etching. Therefore, after operation 63, as... Figure 1 and Figures 2A to 2D The first character line 21, the second character line 22, the substrate 11, the hard mask layer 51 and the dielectric layer 52 shown are formed.
[0068] Reference Figure 9A , Figure 9B , Figure 9C and Figure 9D Following operation 63, in some embodiments, method 60 further includes forming a dielectric layer 53 on the first word line 21 and the second word line 22 by any suitable deposition method, such as chemical vapor deposition or physical vapor deposition, and forming an interlayer dielectric layer 54 on the dielectric layer 53.
[0069] Reference Figure 1 , Figures 2A to 2D , Figure 10A , Figure 10B , Figure 10C and Figure 10DIn operation 64, a first contact structure 31, including a first contact plug 311 and a first wire 312, is formed on the first tail portion 211 by any suitable deposition method, such as chemical vapor deposition or physical vapor deposition. In some embodiments, a second contact structure 32, including a second contact plug 321 and a second wire 322, is formed on the fourth tail portion 222. In some embodiments, prior to performing operation 64, openings 73 exposing the first tail portion 211 and the fourth tail portion 222 are formed in the dielectric layer 53 and the interlayer dielectric layer 54 by any suitable etching method, such as dry etching or wet etching. In operation 64, the first contact structure 31 and the second contact structure 32 are formed in the openings 73. After performing operation 64, as... Figure 1 and Figures 2A to 2D The first contact structure 31, the second contact structure 32, the dielectric layer 53 and the interlayer dielectric layer 54 shown are formed.
[0070] The semiconductor structure of the present invention, and the semiconductor structure formed by the method of the present invention, includes word lines with low stress to avoid bending. Therefore, damage to the word lines can be prevented from impairing the performance of the semiconductor structure. Furthermore, when the semiconductor structure includes multiple word lines, the distance between adjacent word lines can be smaller, and bent word lines will not cause electrical short circuits and / or signal interference between adjacent word lines. In addition, the method of the present invention is easy to implement and cost-effective.
[0071] This invention has been described in considerable detail in some embodiments, but other embodiments may also be feasible. Therefore, the description of the embodiments is not intended to limit the scope and spirit of the appended claims. Modifications and alterations can be made to this invention by those skilled in the art without departing from its scope and spirit. Such modifications and alterations are included in this invention when they fall within the scope and spirit of the appended claims.
[0072] [Symbol Explanation]
[0073] 11: Substrate
[0074] 11JS: Serrated sidewalls
[0075] 21: First character line
[0076] 22: Second character line
[0077] 31: First contact structure
[0078] 32: Second contact structure
[0079] 41: Virtual line
[0080] 42: Virtual line
[0081] 51: Hard mask layer
[0082] 52: Dielectric layer
[0083] 53: Dielectric layer
[0084] 54: Interlayer dielectric layer
[0085] 60: Method
[0086] 61: Operation
[0087] 62: Operation
[0088] 63: Operation
[0089] 64: Operation
[0090] 71: Trench
[0091] 72: Mask
[0092] 72JE: Serrated edges
[0093] 73: Opening
[0094] 111: Quarantine Zone
[0095] 112: Active Area
[0096] 211: First tail section
[0097] 211': First end
[0098] 211B: Boundary
[0099] 211H: Altitude
[0100] 211L: Length
[0101] 211'L: Length
[0102] 211TS: Top surface
[0103] 212: Second tail section
[0104] 212': Second end
[0105] 212B: Boundary
[0106] 212H: Altitude
[0107] 212L: Length
[0108] 212'L: Length
[0109] 212P: Dots
[0110] 212TS: Top surface
[0111] 213: First Middle Section
[0112] 213H: Altitude
[0113] 213TS: Top surface
[0114] 221: Third tail section
[0115] 221': Third end
[0116] 221B: Boundary
[0117] 221H: Altitude
[0118] 221L: Length
[0119] 221'L: Length
[0120] 221P: Dot
[0121] 221TS: Top surface
[0122] 222: Fourth tail section
[0123] 222': Fourth end
[0124] 222B: Boundary
[0125] 222H: Altitude
[0126] 222L: Length
[0127] 222'L: Length
[0128] 222TS: Top surface
[0129] 223: Second Middle Section
[0130] 223H: Altitude
[0131] 223TS: Top surface
[0132] 311: First contact plug
[0133] 312: First conductor
[0134] 321: Second contact plug
[0135] 322: Second conductor
[0136] 1121: Long active region
[0137] 1121L: Length
[0138] 1122: Short active region
[0139] 1122L: Length
[0140] 2111M: Contains a metal layer
[0141] 2111W: Work Function Layer
[0142] 2112': Layer
[0143] 2121M: Contains a metal layer
[0144] 2121W: Work Function Layer
[0145] 2122': Layer
[0146] 2131H: High-power function layer
[0147] 2131M: Contains a metal layer
[0148] 2132L: Low-power function layer
[0149] 2132S: Silicon-containing conductive layer
[0150] 2211M: Contains a metal layer
[0151] 2211W: Work Function Layer
[0152] 2212': Layer
[0153] 2221M: Contains a metal layer
[0154] 2221W: Work Function Layer
[0155] 2222': Layer
[0156] 2231H: High-power function layer
[0157] 2231M: Contains a metal layer
[0158] 2232L: Low-power function layer
[0159] 2232S: Silicon-containing conductive layer
[0160] A-A': line
[0161] B-B': Line
[0162] b-b': line
[0163] C-C': Line
[0164] c-c': line
[0165] D-D': Line
[0166] d-d': line
[0167] H1: Horizontal distance
[0168] H2: Horizontal distance
[0169] H3: Horizontal distance
[0170] H4: Horizontal distance
[0171] TS211: Top surface
[0172] TS212: Top surface
[0173] TS213: Top surface
[0174] TS221: Top surface
[0175] TS222: Top surface
[0176] TS223: Top surface
[0177] X: First direction
[0178] Y: Second direction.
Claims
1. A semiconductor structure, characterized by, Comprising: a substrate; a first word line extending along a first direction on the substrate, wherein the first word line comprises: a first tail end portion; a second tail end portion; and a first middle portion between the first tail end portion and the second tail end portion, wherein a top surface of the first tail end portion and a top surface of the second tail end portion are lower than a top surface of the first middle portion, and a length of the second tail end portion is greater than a length of the first tail end portion; and a first contact structure on the first tail end portion of the first word line.
2. The semiconductor structure of claim 1, wherein a horizontal distance from a boundary of the first tail end portion closest to the second tail end portion to the first contact structure is 100 nm to 1000 nm.
3. The semiconductor structure of claim 1, wherein the first middle portion comprises a high work function layer and a low work function layer disposed on the high work function layer, a work function of the high work function layer is greater than a work function of the low work function layer, the first tail end portion is a work function layer having a work function greater than the work function of the low work function layer, and the second tail end portion is a work function layer having a work function greater than the work function of the low work function layer.
4. The semiconductor structure of claim 1, wherein the first middle portion comprises a metal-containing layer and a silicon-containing conductive layer disposed on the metal-containing layer, the first tail end portion comprises a metal-containing layer in direct contact with the first contact structure, and the second tail end portion comprises a metal-containing layer.
5. The semiconductor structure of claim 1, wherein a first top surface of the substrate around the first middle portion is higher than a second top surface of the substrate around the first tail end portion and a third top surface of the substrate around the second tail end portion.
6. The semiconductor structure of claim 1, wherein, Further comprising: a second word line adjacent to the first word line and extending along the first direction on the substrate, wherein the second word line comprises: a third tail end portion adjacent to the first tail end portion of the first word line; a fourth tail end portion adjacent to the second tail end portion of the first word line; and a second middle portion between the third tail end portion and the fourth tail end portion, wherein a top surface of the third tail end portion and a top surface of the fourth tail end portion are lower than a top surface of the second middle portion, and a length of the third tail end portion is greater than a length of the fourth tail end portion; and a second contact structure on the fourth tail end portion of the second word line.
7. The semiconductor structure of claim 6, wherein a virtual line passes through a point of the first contact structure and the third tail end portion in a second direction perpendicular to the first direction, and a horizontal distance from a boundary of the third tail end portion closest to the fourth tail end portion to the point is 200 nm to 3000 nm.
8. The semiconductor structure of claim 6, wherein the first word line, the first contact structure, the second word line, and the second contact structure are of a group, the semiconductor structure further comprising a plurality of groups each identical to the group on the substrate, and each of the plurality of groups is aligned with the group.
9. A method of forming a semiconductor structure, comprising: including: forming a first word line to extend along a first direction on a substrate; forming a mask on a first middle portion of the first word line and exposing a first end and a second end of the first word line, wherein a length of the second end exposed by the mask is greater than a length of the first end exposed by the mask, and the first middle portion is between the first end and the second end; etching a portion of the first end and a portion of the second end of the first word line exposed by the mask to form a first tail end portion and a second tail end portion of the first word line, respectively, wherein a top surface of the first tail end portion and a top surface of the second tail end portion are lower than a top surface of the first middle portion; and forming a first contact structure on the first tail end portion.
10. The method of claim 9, wherein a length of the second tail end portion is greater than a length of the first tail end portion.
11. The method of claim 9, wherein: the first end includes a high work function layer and a low work function layer disposed on the high work function layer, and a work function of the high work function layer is greater than a work function of the low work function layer; when etching the portion of the first end of the first word line exposed by the mask, the portion includes the low work function layer; and when forming the first contact structure, the first contact structure is in direct contact with the high work function layer.
12. The method of claim 9, wherein when etching the portion of the first end of the first word line exposed by the mask further includes etching a portion of the substrate around the first end.
13. The method of claim 9, wherein, further including: forming a second word line to extend along the first direction on the substrate; forming the mask on a second middle portion of the second word line and exposing a third end and a fourth end of the second word line, wherein a length of the third end exposed by the mask is greater than a length of the fourth end exposed by the mask, the second middle portion is between the third end and the fourth end, and the third end and the fourth end are adjacent to the first end and the second end of the first word line, respectively; and etching a portion of the third end and a portion of the fourth end of the second word line exposed by the mask to form a third tail end portion and a fourth tail end portion of the second word line, respectively.
14. The method of claim 13, wherein, further including forming a second contact structure on the fourth tail end portion.
15. The method of claim 13, wherein the mask has a plurality of jagged edges in the first direction.