Semiconductor structure and forming method thereof
By designing different height sections of the word lines in the pickup and cell areas, the spacing and overlap requirements between the conductive contacts and adjacent wires are improved, solving the problem of insufficient manufacturing process margin caused by the reduction in wire spacing, and improving the process margin and contact resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2026-03-10
AI Technical Summary
As electronic devices shrink, the reduced spacing between conductors leads to stringent requirements on the spacing and overlap between conductive contacts and adjacent conductors, resulting in insufficient manufacturing process margins.
The design incorporates sections where the second segment of the pickup area and the first segment of the cell area have different horizontal heights. By adjusting the position and height of the conductive contacts, the spacing and overlap requirements between the conductive contacts and adjacent wires are improved.
The critical dimensions and overlap requirements of conductive contacts have been improved, increasing the manufacturing process margin and reducing the contact resistance of conductive contacts.
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Figure CN121645848A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a semiconductor structure and a method of forming the same, and more particularly to a word line for a memory device and a method of forming the same. BACKGROUND
[0002] As electronic devices continue to shrink in size and users continue to demand more performance from electronic devices, how to make electronic devices include more components while maintaining the same horizontal area, or have a small horizontal area while maintaining the same number of components, is one of the goals that those skilled in the art strive to achieve. However, the above-mentioned cases will reduce the pitch of the conductive lines (such as the pitch of the word lines), so that the pitch or space between the conductive contacts (such as word line contacts) directly contacting the conductive lines and other conductive lines adjacent to the conductive lines is also reduced, so that the conductive contacts become more demanding in terms of critical dimension (CD) and overlay, causing insufficient process margin. SUMMARY
[0003] The present disclosure provides a semiconductor structure and a method of forming the same, by designing the second section of the word line in the pickup region to include a portion having a different horizontal height from the first section of the word line in the cell region, so that the pitch or space between the conductive contacts contacting the portion and other conductive lines adjacent to the conductive lines can be improved, thereby reducing the requirements of the conductive contacts on critical dimension (CD) and overlay, to improve the process margin.
[0004] One embodiment of the present disclosure provides a semiconductor structure, which includes a substrate, a plurality of word lines, an insulating layer, and a conductive contact. The substrate includes a cell region and a pickup region adjacent to the cell region. The word lines are arranged in a first direction and each extends in a second direction different from the first direction. Each word line is embedded in the substrate and spans the cell region and the pickup region, and each word line includes a first section in the cell region and a second section in the pickup region. The insulating layer is disposed on each word line and embedded in the substrate. The conductive contact is disposed on the second section of each word line. The first section includes a first top surface in contact with the insulating layer, and the second section includes a second top surface in contact with the conductive contact and a third top surface in contact with the insulating layer, wherein a horizontal height of the second top surface is different from a horizontal height of the first top surface.
[0005] In some embodiments, the horizontal height of the second top surface is higher than the horizontal height of the first top surface.
[0006] In some embodiments, the second top surface is at a different level than the third top surface.
[0007] In some embodiments, the second top surface is at a higher level than the third top surface.
[0008] In some embodiments, a size of each word line in the first direction gradually decreases in a third direction away from the top surface of the substrate.
[0009] In some embodiments, the second top surface is at a lower level than the first top surface.
[0010] In some embodiments, the second top surface is at a same level as the third top surface.
[0011] In some embodiments, the second segment includes a first portion in contact with the insulating layer and a second portion protruding from the first portion and in contact with the conductive contact and surrounded by the insulating layer.
[0012] One embodiment of the present invention provides a method of forming a semiconductor device, comprising the following steps. A substrate is provided. The substrate includes a cell region and a pick-up region adjacent to the cell region. A plurality of word lines are formed in the substrate. The word lines are arranged in a first direction and each extends in a second direction different from the first direction. Each word line spans the cell region and the pick-up region and includes a first segment formed in the cell region and a second segment formed in the pick-up region. An insulating layer is formed on each word line and embedded in the substrate. A conductive contact is formed on the second segment of each word line. The first segment includes a first top surface in contact with the insulating layer, and the second segment includes a second top surface in contact with the conductive contact and a third top surface in contact with the insulating layer, and the second top surface is at a different level than the first top surface.
[0013] In some embodiments, the step of forming the word lines includes forming a plurality of word line trenches in the substrate, wherein the word line trenches are arranged in the first direction and each extends in the second direction, and each word line trench spans the cell region and the pick-up region; filling a word line material layer in each word line trench; forming a mask pattern on each word line material layer to cover a portion of each word line material layer, wherein the portion corresponds to a location of the conductive contact; and removing another portion of each word line material layer exposed by the mask pattern to form the plurality of word lines.
[0014] In some embodiments, the step of forming the word lines comprises: forming a plurality of word line trenches in the substrate, wherein the word line trenches are arranged in a first direction and each extends in a second direction, and each word line trench spans the cell region and the pickup region; filling a word line material layer in each word line trench; forming a mask pattern covering a portion of the plurality of word line material layers in the cell region; and removing a portion of the word line material layer exposed by the mask pattern in the pickup region to form a plurality of word lines.
[0015] In some embodiments, the second top surface has a level higher than a level of the first top surface.
[0016] In some embodiments, the second top surface has a level different from a level of the third top surface.
[0017] In some embodiments, the second top surface has a level higher than the level of the third top surface.
[0018] In some embodiments, each word line has a size in the first direction gradually decreasing in a third direction away from a top surface of the substrate.
[0019] In some embodiments, the second top surface has a level lower than a level of the first top surface.
[0020] In some embodiments, the second top surface has a level identical to a level of the third top surface.
[0021] In some embodiments, the second section comprises a first portion in contact with the insulating layer and a second portion protruding from the first portion and in contact with the conductive contact and surrounded by the insulating layer.
[0022] Based on the above, in the semiconductor structure and the method of forming the same, the second section of the word line in the pickup region is designed to comprise a portion having a different level from the first section of the word line in the cell region, so that the spacing or space between the conductive contact contacting the portion and other word lines adjacent to the word line can be improved, and the requirements of the critical dimension and the overlay of the conductive contact can be reduced, so as to improve the process margin of the conductive contact. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 is a top view of a semiconductor structure according to an embodiment of the present application;
[0024] Figure 2A and Figure 2B are respectively Figure 1 are respectively cross-sectional views taken along lines X-X' and Y-Y' in an embodiment;
[0025] Figure 3A and Figure 3B are respectivelyFigure 1 Fig. 6 is a cross-sectional view taken along line X-X' and line Y-Y' of another embodiment;
[0026] Figures 4A to 4C Fig. 7 is a cross-sectional view of forming a semiconductor structure according to an embodiment of the present application.
[0027] Figure 5 Fig. 8 is a top view of Figure 4C Fig. 9 is a cross-sectional view taken along line X-X' and line Y-Y' of
[0028] Figure 6 Figure 7 Fig. 10 is a cross-sectional view taken along line X-X' and line Y-Y' of Figures 8A to 8C Fig. 11 is a cross-sectional view of forming a semiconductor structure according to another embodiment of the present application.
[0029] Symbol explanation
[0030] 10, 20: semiconductor structure
[0031] 100: substrate
[0032] 102: isolation structure
[0033] 102t: word line trench
[0034] 110, 210: word line
[0035] 110a, 210a: first portion
[0036] 110b, 210b: second portion
[0037] 110b1: line portion
[0038] 110b2: protrusion portion
[0039] 120, 220: insulating layer
[0040] 120t, 220t: recess
[0041] 130: wiring layer
[0042] CR: cell region
[0043] CT1, CT2: conductive contact
[0044] d1, d2: distance
[0045] h1, h2: height
[0046] MK1, MK2: mask pattern
[0047] PR: pick-up region
[0048] WLM: word line material layer
[0049] X, Y, Z: direction Detailed Implementation
[0050] The invention is described more fully with reference to the accompanying drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.
[0051] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be intermediate elements present. If an element is referred to as being "directly on" or "directly connected" to another element, there are no intermediate elements present. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between two elements. As used herein, "electrical connection" may include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).
[0052] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned values and specific values within an acceptable range of deviation that can be determined by one of ordinary skill in the art, taking into account the measurement under discussion and the specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties, selecting a more acceptable range of deviations or standard deviations, rather than applying a single standard deviation to all properties.
[0053] The terminology used herein is for illustrative purposes only and is not intended to limit the invention. In this context, the singular form includes the plural form unless the context otherwise requires.
[0054] Figure 1 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 2A and Figure 2B They are Figure 1 A schematic cross-sectional view taken along line X-X' and line Y-Y' in one embodiment.
[0055] Please refer to Figure 1 as well as Figure 2A and Figure 2B The semiconductor structure 10 includes a substrate 100, multiple word lines 110, an insulating layer 120, and conductive contacts CT1 and CT2.
[0056] The substrate 100 can include a cell region CR and a pick-up region PR adjoining the cell region CR. The substrate 100 can include a semiconductor substrate or a semiconductor on insulator (SOI) substrate, a device layer formed on the semiconductor substrate or the SOI substrate. The cell region CR can be a region in which memory cells (units) are formed. For example, the cell region CR can be a cell region in which volatile dynamic random access memory (DRAM) cells are formed. The pick-up region PR can be a region in which conductive contacts are formed to pick up electrical signals of wires (e.g., word lines) formed in the substrate 100. In some embodiments, the substrate 100 can include an isolation structure 102. The isolation structure 102 can include any material suitable for an isolation structure, such as silicon oxide. In some embodiments, the isolation structure 102 can be a shallow trench isolation (STI) structure.
[0057] The semiconductor material in the semiconductor substrate or the SOI substrate can include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor can include Si or Ge. The alloy semiconductor can include SiGe, SiGeC, etc. The compound semiconductor can include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material can include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The II-VI semiconductor material can include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material can be doped with dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be P-type, and the second conductivity type can be N-type.
[0058] The element layer may include active elements such as N-type metal-oxide-semiconductor (NMOS), P-type metal-oxide-semiconductor (PMOS), or complementary metal-oxide-semiconductor (CMOS). In some embodiments, the active elements may be disposed in the cell region CR, but are not limited thereto.
[0059] Character line 110 is in the first direction (e.g.) Figure 1 Arranged in the direction X) and each in a second direction different from the first direction (e.g. Figure 1 The word line 110 extends in the direction Y shown. In some embodiments, the first direction intersects the second direction. In some embodiments, the first direction is perpendicular to the second direction. Each word line 110 is embedded in the substrate 100 and spans the cell region CR and the pickup region PR. Each word line 110 includes a first segment located in the cell region CR and a second segment located in the pickup region PR. The word line 110 may include a conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or alloys thereof. In some embodiments, the word line 110 extends in the direction Y shown. Figure 2A and Figure 2B The portion shown is the isolation structure 102 formed on the substrate 100.
[0060] An insulating layer 120 is disposed on each word line 110 and embedded in the substrate 100. In some embodiments, the insulating layer 120 is embedded in the substrate 100 of the pickup area PR and the cell area CR. Figure 2A and Figure 2B The portion shown is embedded in the isolation structure 102 of the substrate 100. The insulating layer 120 may include insulating materials such as nitrides (e.g., silicon nitride).
[0061] Conductive contacts CT1 and CT2 are disposed on the second segment of each word line 110. Conductive contacts CT1 and CT2 may comprise conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. In some embodiments, conductive contacts CT1 and CT2 may be arranged alternately offset from each other along a first direction (e.g., direction X), thereby increasing the distance between adjacent conductive contacts CT1 and CT2, and thus reducing the requirements for critical dimension (CD) and overlay of the conductive contacts, thereby improving their manufacturing process margin.
[0062] like Figure 2A and Figure 2BAs shown, the first segment of the word line 110 includes a first top surface in contact with the insulating layer 120, while the second segment of the word line 110 includes a second top surface in contact with conductive contacts CT1 and CT2, and a third top surface in contact with the insulating layer 120. The horizontal height of the second top surface of the word line 110 in the second segment, which contacts the conductive contacts CT1 and CT2, is designed to be different from the horizontal height of the first top surface of the word line 110 in the first segment, which contacts the insulating layer 120. In this way, the conductive contacts (such as...) Figure 2A The spacing between the conductive contact CT1 shown and the adjacent word line 110 (e.g.) Figure 2A The distance d1 shown can be increased, thereby reducing the requirements for critical dimensions and overlap of the conductive contact CT1, so as to improve its manufacturing process margin.
[0063] In this embodiment, as Figure 2A As shown, the horizontal height of the second top surface of the word line 110 in the second section that contacts the conductive contact CT1 is designed to be higher than the horizontal height of the first top surface of the word line 110 in the first section that contacts the insulating layer 120. This improves the spacing between the conductive contact CT1 and the adjacent word line 110 (e.g., Figure 2A The distance d1 shown reduces the requirements for critical dimensions and overlap of the conductive contact CT1, thereby improving its manufacturing margin. For example, with a linewidth of approximately 19 nm for word line 110, the aforementioned distance can be increased to 2.4 times the original value.
[0064] In this embodiment, the horizontal height of the second top surface of the word line 110 in the second section that contacts the conductive contact CT1 is different from the horizontal height of the third top surface of the word line 110 in the second section that contacts the insulating layer 120. For example... Figure 1 and Figure 2B As shown, the horizontal height of the second top surface of the word line 110 in the second section that contacts the conductive contact CT1 is higher than the horizontal height of the third top surface of the word line 110 in the second section that contacts the insulating layer 120.
[0065] In this embodiment, as Figure 1 as well as Figure 2A and Figure 2BAs shown, in the cell region CR, an insulating layer 120 may be disposed in the word line trenches in which word lines 110 are formed to cover the word lines 110. That is, the word lines 110 in the first segment of the cell region CR may be covered by the insulating layer 120 and have the same horizontal height (e.g., a horizontal height difference of height h1 from the top surface of the isolation structure 102 of the substrate 100). In the pickup region PR, the word lines 110 may include a first portion 110a and a second portion 110b. The first portion 110a of the word lines 110 may extend from the cell region CR and have the same horizontal height as the word lines 110 in the first segment of the cell region CR, and the first portion 110a of the word lines 110 is also covered by the insulating layer 120. The second portion 110b of the word line 110 may include a line portion 110b1 extending from the cell region CR and having the same horizontal height as the first segment of the word line 110 in the cell region CR, and a protruding portion 110b2 protruding from the line portion 110b1 and contacting the conductive contacts CT1, CT2 and surrounded by the insulating layer 120.
[0066] In some embodiments, such as Figure 2A and Figure 2B As shown, the semiconductor structure 10 may further include a wiring layer 130. In some embodiments, the wiring layer 130 may be a conductive layer of an interconnect layer formed, for example, by a back end of line (BEOL) fabrication process. The material of the wiring layer 130 may include a conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. In some embodiments, the interconnect layer in which the wiring layer 130 is formed may include a dielectric layer (not shown). Conductive contacts CT1, CT2, and / or the wiring layer 130 may be formed in the dielectric layer. The dielectric layer may include oxides, such as tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), oxides formed by high density plasma (HDP), undoped silicate glass (USG), phosphosilicate glass (PSG), and oxides formed by spin coating, such as spin-on glass (SOG) and spin-on dielectric (SOD), or oxides formed by a high aspect ratio process (HARP).
[0067] Figure 3A and Figure 3B They areFigure 1 A schematic cross-sectional view taken along lines X-X' and Y-Y' in another embodiment. Figure 3A and Figure 3B The semiconductor structure 20 shown is Figure 2A and Figure 2B The semiconductor structure 20 is similar to the semiconductor structure 10 shown. The main difference is that the word line 210 and the insulating layer 220 of the semiconductor structure 20 are different from the word line 110 and the insulating layer 120 of the semiconductor structure 10. Other identical or similar parts are represented by the same or similar element symbols, which will not be repeated here.
[0068] In this embodiment, as Figure 2A and Figure 3A As shown, the dimension of each word line 210 in the first direction (e.g., direction X) gradually decreases in a third direction (e.g., direction Z) away from the top surface of the substrate 100 (e.g., the top surface of the isolation structure 102). That is, the distance between adjacent word lines 210 gradually increases away from the top surface of the substrate 100. In this embodiment, as... Figure 3A and Figure 3B As shown, the word line 210 is designed to include a first portion 210a in the cell region CR and a second portion 210b in the pickup region PR. The top surface of the second portion 210b is designed to differ from the top surface of the isolation structure 102 of the substrate 100 by a height h2, wherein the height h2 is greater than the height h1. Figure 3B The height h1 shown corresponds to Figure 2A The height h1 shown can be increased to improve the distance between the second portions 210b of adjacent word lines 210 (e.g., by increasing the height h2). Figure 3A The distance d2 is shown. For example, with a linewidth of approximately 19 nm for word line 210, the aforementioned distance can be increased to 1.6 times the original value. In some embodiments, Figure 2A The character line 110 shown has a lower Figure 3A The contact resistance of word line 210 is shown.
[0069] In this embodiment, such as Figure 3B As shown, the word line 210 in the first segment of the cell region CR may include a first top surface contacting the insulating layer 220, while the word line 210 in the second segment of the pickup region PR may include a second top surface contacting the conductive contact CT2 and a third top surface contacting the insulating layer 220. The horizontal height of the second top surface of the word line 210 in the second segment that contacts the conductive contact CT2 is designed to be lower than the horizontal height of the first top surface of the word line 210 in the first segment that contacts the insulating layer 220. In this embodiment, as... Figure 3BAs shown, in the pickup region PR, the horizontal level of the second top surface of the word line 210 that is in contact with the conductive contact CT2 is the same as the horizontal level of the third top surface of the word line 210 that is in contact with the insulating layer 220.
[0070] In the following, the manufacturing method of the semiconductor structure 10 shown in Figures 4A to 4C and Figure 5 will be exemplarily described. Figure 2A and Figure 2B but is not limited thereto.
[0071] Figures 4A to 4C is a schematic cross-sectional view of a semiconductor structure forming an embodiment of the present application. Figure 5 is a schematic top view of Figure 4C .
[0072] First, a substrate 100 as shown in Figure 1 is provided. The substrate 100 can comprise a cell region CR and a pickup region PR adjoining the cell region CR. In the present embodiment, the substrate 100 can comprise an isolation structure 102.
[0073] Next, a plurality of word lines 110 is formed in the substrate 100. The word lines 110 are arranged in a first direction (e.g. direction X) and each extends in a second direction (e.g. direction Y) different from the first direction, wherein each word line 110 spans the cell region CR and the pickup region PR and comprises a first section formed in the cell region CR and a second section formed in the pickup region PR.
[0074] In some embodiments, the word lines 110 can be formed by the following.
[0075] First, as shown in Figure 4A , a plurality of word line trenches 102t is formed in the isolation structure 102 of the substrate 100. The word line trenches 102t are arranged in a first direction (e.g. direction X) and each extends in a second direction (e.g. direction Y) different from the first direction, wherein each word line trench 102t spans the cell region CR and the pickup region PR.
[0076] Next, as shown in Figure 4B , a word line material layer WLM is filled in the word line trenches 102t. The word line material layer WLM can comprise a conductive material such as a metal or a metal alloy. The metal and the metal alloy can be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or an alloy thereof.
[0077] Then, as shown in Figure 4C and Figure 5 , a mask pattern MK1 is formed on each word line material layer WLM to cover a position of each word line material layer WLM corresponding to the conductive contact CT1, CT2 (see also Figure 1 andFigure 5 Then, another portion of the word line material layer WLM exposed by the mask pattern MK1 is removed to form the groove 120t and multiple word lines 110.
[0078] In the cell region CR, the word line material layer WLM is exposed by the mask pattern MK1, so that the formed word line 110 is exposed by the groove 120t.
[0079] In the pickup area PR, the word line material layer WLM includes a portion exposed by the mask pattern MK1, such that the formed word line 110 includes a first portion 110a exposed by the groove 120t. The first portion 110a of the word line 110 may extend from the cell region CR to a horizontal height equal to that of the cell region CR. In the pickup area PR, the word line material layer WLM may include a portion covered by the mask pattern MK1, such that the formed word line 110 includes a second portion 110b. The second portion 110b of the word line 110 may include a line portion 110b1 extending from the cell region CR to a horizontal height equal to that of the cell region CR, and a protruding portion 110b2 protruding from the line portion 110b1, contacting the mask pattern MK1, and surrounded by the groove 120t.
[0080] After forming the letter line 110, the mask pattern MK1 is removed.
[0081] Then, please refer to Figure 4C and Figure 2A Insulating material is filled into the groove 120t to form an insulating layer 120 embedded in the substrate 100 on each letter 110. For example... Figure 2A As shown, the insulating layer 120 is embedded in the isolation structure 102 of the substrate 100 in the pickup area PR. Then, conductive contacts CT1 and CT2 are formed on the second segment of each word line 110 in the pickup area PR.
[0082] The following will be through Figure 6 , Figure 7 as well as Figures 8A to 8C Let's take an example. Figure 3A and Figure 3B The method of manufacturing the semiconductor structure 20 shown is illustrated, but not limited thereto.
[0083] Figure 6 , Figure 7 as well as Figures 8A to 8C This is a schematic diagram of a semiconductor structure forming another embodiment of the present invention. Figure 8A and Figure 8B They are Figure 8C A schematic cross-sectional view taken along lines X-X' and Y-Y' in another embodiment.
[0084] First, a substrate 100 as shown in Figure 1 is provided. The substrate 100 can include a cell region CR and a pickup region PR adjoining the cell region CR. The substrate 100 can include an isolation structure 102.
[0085] Next, a plurality of word lines 210 are formed in the substrate 100. The word lines 210 are arranged in a first direction (e.g., direction X) and each extends in a second direction (e.g., direction Y) different from the first direction, where each word line 210 spans the cell region CR and the pickup region PR and includes a first section formed in the cell region CR and a second section formed in the pickup region PR.
[0086] In some embodiments, the word lines 210 can be formed by the following.
[0087] First, a plurality of word line trenches 102t are formed in the isolation structure 102 of the substrate 100 as shown in Figure 6 . The word line trenches 102t are arranged in a first direction (e.g., direction X) and each extends in a second direction (e.g., direction Y) different from the first direction, where each word line trench 102t spans the cell region CR and the pickup region PR.
[0088] Next, a word line material layer WLM is filled in the word line trenches 102t as shown in Figure 7 . The word line material layer WLM can include a conductive material such as a metal or a metal alloy. The metal and the metal alloy can be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or an alloy thereof.
[0089] Then, a mask pattern MK2 is formed on each word line material layer WLM to cover the portion of the word line material layer WLM disposed in the cell region CR as shown in Figures 8A to 8C . The mask pattern MK2 is formed, for example, by a photolithography process. (See Figures 8A to 8C .) Thereafter, the portion of the word line material layer WLM exposed by the mask pattern MK2 is removed to form recesses 220t and a plurality of word lines 210.
[0090] In the cell region CR, the word line material layer WLM is covered by the mask pattern MK2, such that the formed word line 210 includes a first portion 210a in contact with the mask pattern MK2. In the pickup region PR, the word line material layer WLM is exposed by the mask pattern MK2, such that the formed word line 210 includes a second portion 210b on which the recess 220t is formed.
[0091] After the word lines 210 are formed, the mask pattern MK2 is removed.
[0092] Thereafter, please refer to Figure 3A and Figure 3B as well as Figure 8A andFigure 8B The recesses 220t are filled with insulating material to form insulating layers 220 embedded in the substrate 100 over the word lines 210. As shown, the insulating layers 220 are embedded in the isolation structures 102 of the substrate 100 in the pick-up region PR. Then, conductive contacts CT1, CT2 are formed over the second segments of the word lines 210 in the pick-up region PR. Figure 3A
[0093] In summary, in the semiconductor structure and the method of forming the same of the above embodiments, the second segment of the word line in the pick-up region is designed to include a portion having a different level height from the first segment of the word line in the cell region, so that the spacing or space between the conductive contact contacting the portion and other word lines adjacent to the word line can be improved, and the critical dimension and overlay requirements of the conductive contact can be reduced to improve the process margin.
Claims
1. A semiconductor structure, comprising: a substrate including a cell region and a pickup region adjacent to the cell region; a plurality of word lines arranged in a first direction and each extending in a second direction different from the first direction, wherein each of the word lines is embedded in the substrate and straddles the cell region and the pickup region, and each of the word lines includes a first section located in the cell region and a second section located in the pickup region; an insulating layer disposed on each of the word lines and embedded in the substrate; and a conductive contact disposed on the second section of each of the word lines, wherein the first section includes a first top surface in contact with the insulating layer, and the second section includes a second top surface in contact with the conductive contact and a third top surface in contact with the insulating layer, and a level of the second top surface is different from a level of the first top surface.
2. The semiconductor structure of claim 1, wherein the level of the second top surface is higher than the level of the first top surface.
3. The semiconductor structure of claim 2, wherein the level of the second top surface is different from a level of the third top surface.
4. The semiconductor structure of claim 3, wherein the level of the second top surface is higher than the level of the third top surface.
5. The semiconductor structure of claim 1, wherein a dimension of each of the word lines in the first direction gradually decreases in a third direction away from a top surface of the substrate.
6. The semiconductor structure of claim 5, wherein the level of the second top surface is lower than the level of the first top surface.
7. The semiconductor structure of claim 6, wherein the level of the second top surface is the same as a level of the third top surface.
8. The semiconductor structure of claim 1, wherein the second section includes a first portion in contact with the insulating layer and a second portion protruding from the first portion, in contact with the conductive contact, and surrounded by the insulating layer.
9. A method of forming a semiconductor structure, comprising: providing a substrate including a cell region and a pickup region adjacent to the cell region; forming a plurality of word lines in the substrate, the plurality of word lines arranged in a first direction and each extending in a second direction different from the first direction, wherein each of the word lines straddles the cell region and the pickup region and includes a first section formed in the cell region and a second section formed in the pickup region; forming an insulating layer embedded in the substrate on each of the word lines; and forming a conductive contact on the second section of each of the word lines, wherein the first section includes a first top surface in contact with the insulating layer, and the second section includes a second top surface in contact with the conductive contact and a third top surface in contact with the insulating layer, and a level of the second top surface is different from a level of the first top surface.
10. The method of claim 9, wherein the step of forming the word lines comprises: forming a plurality of word line trenches in the substrate, the plurality of word line trenches being arranged in the first direction and each extending in the second direction, and each of the word line trenches crossing the cell region and the pickup region; filling a word line material layer in each of the word line trenches; forming a mask pattern on each of the word line material layers to cover a portion of each of the word line material layers, the portion corresponding to a location of the conductive contact; and removing another portion of the word line material layer exposed by the mask pattern to form the plurality of word lines.
11. The method of claim 9, wherein the step of forming the word lines comprises: forming a plurality of word line trenches in the substrate, the plurality of word line trenches being arranged in the first direction and each extending in the second direction, and each of the word line trenches crossing the cell region and the pickup region; filling a word line material layer in each of the word line trenches; forming a mask pattern covering a portion of the plurality of word line material layers located in the cell region; and removing a portion of the word line material layer exposed by the mask pattern located in the pickup region to form the plurality of word lines.
12. The method of claim 9, wherein the level of the second top surface is higher than the level of the first top surface.
13. The method of claim 12, wherein the level of the second top surface is different from a level of a third top surface.
14. The method of claim 13, wherein the level of the second top surface is higher than the level of the third top surface.
15. The method of claim 9, wherein a dimension of each of the word lines in the first direction is formed to gradually decrease in a third direction away from a top surface of the substrate.
16. The method of claim 15, wherein the level of the second top surface is lower than the level of the first top surface.
17. The method of claim 16, wherein the level of the second top surface is the same as a level of a third top surface.
18. The method of claim 10, wherein the second segment includes a first portion in contact with the insulating layer and a second portion raised from the first portion and in contact with the conductive contact and surrounded by the insulating layer.