Semiconductor structure, forming method thereof and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, and relates to a semiconductor structure and a forming method thereof, and electronic equipment, and the forming method comprises the steps: providing a substrate; a first semiconductor layer and a second semiconductor layer which are sequentially and alternately distributed in the direction perpendicular to the surface of a substrate are formed on the substrate, and the second semiconductor layer comprises a first germanium-silicon layer and a second germanium-silicon layer which are distributed in a stacked mode. The concentration of germanium ions in the first germanium-silicon layer is gradually reduced from one side close to the second germanium-silicon layer to one side far away from the second germanium-silicon layer; in the plurality of second semiconductor layers, the concentration of germanium ions in the second semiconductor layer close to one side of the substrate is greater than the concentration of germanium ions in the second semiconductor layer far away from one side of the substrate. According to the forming method, the lattice mismatch degree between the first semiconductor layer and the second semiconductor layer can be reduced, the dislocation density is further reduced, dislocation defects are reduced, and the structural reliability is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and an electronic device. Background Technology

[0002] Due to their advantages such as small size, high integration, and high transmission speed, memory is widely used in mobile devices such as mobile phones and tablets. In the manufacturing process of 3D memory, in order to increase storage capacity, multiple layers of alternating semiconductor films are usually stacked. However, the more semiconductor films stacked, the more obvious the misalignment defects, and the lower the product reliability.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its formation method, as well as an electronic device, which can reduce the lattice mismatch between the first semiconductor layer and the second semiconductor layer, thereby reducing the dislocation density, reducing dislocation defects, and improving structural reliability.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: Provide substrate; A first semiconductor layer and a second semiconductor layer are formed on the substrate in a direction perpendicular to the surface of the substrate, which are alternately distributed in sequence. The second semiconductor layer includes a first germanium-silicon layer and a second germanium-silicon layer stacked together. The concentration of germanium ions in the first germanium-silicon layer gradually decreases from the side closer to the second germanium-silicon layer to the side farther away from the second germanium-silicon layer. In the plurality of second semiconductor layers, the concentration of germanium ions in the second semiconductor layer closer to the substrate is greater than the concentration of germanium ions in the second semiconductor layer farther from the substrate.

[0006] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer is equal to the maximum concentration of germanium ions in the first germanium-silicon layer.

[0007] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer is 20% to 30%, and the concentration of germanium ions in the first germanium-silicon layer gradually decreases from the same concentration as the second germanium-silicon layer to 5% to 10%.

[0008] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer gradually decreases from the side closer to the first germanium-silicon layer to the side farther away from the first germanium-silicon layer.

[0009] In one exemplary embodiment of this disclosure, the second semiconductor layer further includes a third germanium-silicon layer adjacent to the second germanium-silicon layer, the third germanium-silicon layer being located on the side of the second germanium-silicon layer away from the first germanium-silicon layer; the concentration of germanium ions in the third germanium-silicon layer gradually decreases from the side closer to the second germanium-silicon layer to the side farther away from the second germanium-silicon layer.

[0010] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer is equal to the maximum concentration of germanium ions in the third germanium-silicon layer.

[0011] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer is 20% to 30%; the concentration of germanium ions in the third germanium-silicon layer gradually decreases from the same concentration as the second germanium-silicon layer to 5% to 10%.

[0012] In one exemplary embodiment of this disclosure, among the plurality of second semiconductor layers, the thickness of the second semiconductor layer on the side closer to the substrate is less than the thickness of the second semiconductor layer on the side farther from the substrate.

[0013] In an exemplary embodiment of this disclosure, the first semiconductor layer includes a support region and an active region arranged side-by-side along a direction parallel to the surface of the substrate; the first germanium-silicon layer includes a first sub-film layer and a second sub-film layer, the second sub-film layer being located between the second germanium-silicon layer and the first sub-film layer; the formation method further includes: The second germanium-silicon layer and the second sub-film layer are etched laterally to form a first recess; the first recess exposes the active region and the first sub-film layer corresponding to the active region; The first sub-film layer exposed in the first recess is removed and the active region is thinned to form a second recess; the remaining first sub-film layer has a groove on the end face near the second recess. A spacer layer is formed, the spacer layer filling the groove and the second recess, and the portion of the spacer layer located in the groove constitutes a protrusion; Remove the remaining second semiconductor layer and the support region to expose the end of the active region; Multiple capacitor structures are formed, each coupled to an active region in a different first semiconductor layer.

[0014] In an exemplary embodiment of this disclosure, the first semiconductor layer includes a support region and an active region arranged side-by-side along a direction parallel to the surface of the substrate; the first germanium-silicon layer includes a first sub-film layer and a second sub-film layer, the second sub-film layer being located between the second germanium-silicon layer and the first sub-film layer; the third germanium-silicon layer includes a third sub-film layer and a fourth sub-film layer, the fourth sub-film layer being located between the second germanium-silicon layer and the third sub-film layer; the formation method further includes: Laterally etch the second germanium-silicon layer, the second sub-film layer, and the fourth sub-film layer to form a first recess; the first recess exposes the first sub-film layer and the third sub-film layer corresponding to the active region; The first sub-film layer and the third sub-film layer exposed in the first recess are removed, and the active region is thinned to form a second recess; the remaining first sub-film layer and the remaining third sub-film layer have grooves on their end faces near the second recess. A spacer layer is formed, the spacer layer filling the groove and the second recess, and the portion of the spacer layer located in the groove constitutes a protrusion; Remove the remaining second semiconductor layer and the support region to expose the end of the active region; Multiple capacitor structures are formed, each coupled to an active region in a different first semiconductor layer.

[0015] In an exemplary embodiment of this disclosure, the active region includes a first source / drain region, a channel region, and a second source / drain region sequentially distributed along a direction parallel to the surface of the substrate; the capacitor structure is coupled to the first source / drain region; the spacer layer includes a first insulating layer conformally covering the second recess and a second insulating layer located on the surface of the first insulating layer and filling the remaining space in the second recess; before removing the remaining second semiconductor layer, the formation method further includes: The first insulating layer is etched back to expose the surfaces of the channel region and the second source / drain region; A gate oxide layer is formed at least on the surface of the channel region; Word lines are formed on the surface of the gate oxide layer; A third insulating layer is formed on the side of the word line away from the remaining first insulating layer.

[0016] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: A substrate and a plurality of first semiconductor layers spaced apart along a direction perpendicular to the surface of the substrate, wherein the first semiconductor layers include a first source / drain region, a channel region, and a second source / drain region sequentially distributed along a direction parallel to the surface of the substrate; A spacer layer is located between adjacent first semiconductor layers and at least covers the surface of the first source / drain region. The end of the spacer layer covering the surface of the first source / drain region and away from the channel region has a protrusion that protrudes toward the side away from the channel region. Multiple capacitor structures are coupled to different first source / drain regions; the protrusion is located between the first electrode layers of adjacent capacitor structures; or, in adjacent capacitor structures, one end of the portion of the first electrode layer of the upper capacitor structure closer to the substrate contacts the top of the protrusion, and one end of the portion of the first electrode layer of the lower capacitor structure farther from the substrate contacts the bottom of the protrusion.

[0017] In one exemplary embodiment of this disclosure, the capacitor structure further includes a capacitor dielectric layer and a second electrode layer, wherein the capacitor dielectric layer conformally covers the surface of the structure jointly formed by the first electrode layer and the spacer layer, and the second electrode layer conformally covers the surface of the capacitor dielectric layer.

[0018] In an exemplary embodiment of this disclosure, a dielectric layer is provided between the first electrode layers of adjacent capacitor structures, and the thickness of the dielectric layer on the side closer to the substrate is less than the thickness of the dielectric layer on the side farther from the substrate.

[0019] According to one aspect of this disclosure, an electronic device is provided, comprising: A processing device; and a memory device electrically connected to the processing device, the memory device comprising the semiconductor structure described in any one of the preceding claims.

[0020] The semiconductor structure, its formation method, and electronic device disclosed herein, by incorporating a first germanium-silicon layer with a gradually varying concentration in the second semiconductor layer, results in a film layer with a low germanium ion concentration in contact with the first semiconductor layer. This film layer exhibits good lattice matching with the first semiconductor layer (which may be made of silicon), helping to reduce lattice mismatch between the first and second semiconductor layers, thereby reducing dislocation density, minimizing dislocation defects, and improving structural reliability. Simultaneously, because germanium ions in the low-concentration germanium-silicon layer have low diffusion capacity, they are less likely to diffuse into adjacent first semiconductor layers, effectively suppressing germanium ion diffusion and reducing the interface thickness between the first and second semiconductor layers. Furthermore, since the lower second semiconductor layer undergoes a longer heat treatment time during the manufacturing process, by ensuring that the germanium ion concentration in the second semiconductor layer closer to the substrate is greater than that in the second semiconductor layer farther from the substrate, the high concentration design can compensate for the concentration decay caused by thermal diffusion of germanium ions in the lower second semiconductor layer during heat treatment. This ensures that the germanium ion concentration in each second semiconductor layer of the structure after heat treatment remains within a preset range, further improving product reliability.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0023] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0024] Figure 2 This is a schematic diagram of a substrate, a first semiconductor layer, and a second semiconductor layer in one embodiment of the present disclosure.

[0025] Figure 3 This is a schematic diagram of a substrate, a first semiconductor layer, and a second semiconductor layer in another embodiment of the present disclosure.

[0026] Figure 4 This is a schematic diagram of the first sub-film layer and the second sub-film layer in one embodiment of the present disclosure.

[0027] Figure 5 This is a schematic diagram of the structure after step S210 is completed in one embodiment of this disclosure.

[0028] Figure 6 This is a schematic diagram of the structure after step S220 is completed in one embodiment of this disclosure.

[0029] Figure 7 This is a schematic diagram of the structure after step S230 is completed in one embodiment of this disclosure.

[0030] Figure 8 This is a schematic diagram of the structure after step S310 is completed in one embodiment of this disclosure.

[0031] Figure 9 This is a schematic diagram of the structure after step S340 is completed in one embodiment of this disclosure.

[0032] Figure 10 This is a schematic diagram of the third recess in one embodiment of the present disclosure.

[0033] Figure 11 This is a schematic diagram of the dielectric layer in one embodiment of the present disclosure.

[0034] Figure 12 This is a schematic diagram of the fourth recess in one embodiment of the present disclosure.

[0035] Figure 13 This is a schematic diagram of the structure after step S250 is completed in one embodiment of this disclosure.

[0036] Figure 14 This is a schematic diagram of the first sub-film layer, the second sub-film layer, the third sub-film layer and the fourth sub-film layer in one embodiment of the present disclosure.

[0037] Figure 15 This is a schematic diagram of the structure after step S410 is completed in one embodiment of this disclosure.

[0038] Figure 16 This is a schematic diagram of the structure after step S420 is completed in one embodiment of this disclosure.

[0039] Figure 17 This is a schematic diagram of the structure after step S430 is completed in one embodiment of this disclosure.

[0040] Figure 18 This is a schematic diagram of the structure after the gate oxide layer, word line and third insulating layer are formed in one embodiment of the present disclosure.

[0041] Figure 19 This is a schematic diagram of the structure after the third recess is formed in one embodiment of the present disclosure.

[0042] Figure 20 This is a schematic diagram of the structure after the fourth recess is formed in one embodiment of the present disclosure.

[0043] Figure 21 This is a schematic diagram of the structure after the dielectric layer is formed in one embodiment of this disclosure.

[0044] Figure 22 This is a schematic diagram of the structure after the fifth recess is formed in one embodiment of the present disclosure.

[0045] Figure 23 This is a schematic diagram of the structure after step S450 is completed in one embodiment of this disclosure.

[0046] Figure 24 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0047] Explanation of reference numerals in the attached figures: 1. Substrate; 2. First semiconductor layer; 21. Support region; 22. Active region; 221. First source / drain region; 222. Channel region; 223. Second source / drain region; 3. Second semiconductor layer; 31. First germanium-silicon layer; 311. First sub-film layer; 312. Second sub-film layer; 32. Second germanium-silicon layer; 33. Third germanium-silicon layer; 331. Third sub-film layer; 332. Fourth sub-film layer; 4. First recess; 5. Second recess; 6. Groove; 7. Spacer layer; 71. First insulating layer; 711. Protrusion; 72. Second insulating layer; 8. Third recess; 9. Dielectric layer; 10. Fourth recess; 11. Capacitor structure; 111. First electrode layer; 112. Capacitor dielectric layer; 113. Second electrode layer; 12. Gate oxide layer; 13. Word line; 14. Third insulating layer; 15. Mask layer; 16. Fifth recess; 20. Electronic device; 201. Processing device; 202. Storage device; 203. Semiconductor structure. Detailed Implementation

[0048] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0049] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0050] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” “third,” and “fourth,” etc., are used only as markers and are not a limitation on the number of objects.

[0051] This disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes steps S110 and S120, wherein: Step S110: Provide a substrate; In step S120, a first semiconductor layer and a second semiconductor layer are formed on the substrate in a direction perpendicular to the surface of the substrate, which are alternately distributed in sequence. The second semiconductor layer includes a first germanium-silicon layer and a second germanium-silicon layer stacked together. The concentration of germanium ions in the first germanium-silicon layer gradually decreases from the side closer to the second germanium-silicon layer to the side farther away from the second germanium-silicon layer. Among the multiple second semiconductor layers, the concentration of germanium ions in the second semiconductor layer closer to the substrate is greater than the concentration of germanium ions in the second semiconductor layer farther away from the substrate.

[0052] The semiconductor structure formation method disclosed herein, by incorporating a first germanium-silicon layer with a gradually varying concentration in the second semiconductor layer, results in a film layer with a low germanium ion concentration in contact with the first semiconductor layer. This film layer exhibits good lattice matching with the first semiconductor layer (which may be made of silicon), helping to reduce lattice mismatch between the first and second semiconductor layers, thereby reducing dislocation density, minimizing dislocation defects, and improving structural reliability. Simultaneously, because germanium ions in the low-concentration germanium-silicon layer have low diffusion capacity, they are less likely to diffuse into adjacent first semiconductor layers, effectively suppressing germanium ion diffusion and reducing the thickness of the interface layer between the first and second semiconductor layers. Furthermore, since the lower second semiconductor layer undergoes a longer heat treatment time during the manufacturing process, by ensuring that the germanium ion concentration in the second semiconductor layer closer to the substrate is greater than that in the second semiconductor layer farther from the substrate, the high concentration design can compensate for the concentration decay caused by thermal diffusion of germanium ions in the lower second semiconductor layer during heat treatment. This ensures that the germanium ion concentration in each second semiconductor layer of the structure after heat treatment remains within a preset range, further improving product reliability.

[0053] The steps and specific details of the semiconductor structure formation method disclosed herein are described in detail below: like Figure 1 As shown, in step S110, a substrate is provided.

[0054] like Figure 2 As shown, substrate 1 can be a flat plate structure, and its material can be a semiconductor material, such as silicon, but not limited to silicon or other semiconductor materials. It can be undoped single crystal silicon or single crystal silicon doped with elements such as phosphorus and boron. No special limitation is made on the material of substrate 1 here.

[0055] like Figure 1 As shown, in step S120, a first semiconductor layer 2 and a second semiconductor layer 3 are formed on the substrate 1 in a direction perpendicular to the surface of the substrate 1, which are alternately distributed in sequence. The second semiconductor layer 3 includes a first germanium-silicon layer 31 and a second germanium-silicon layer 32 stacked together. The concentration of germanium ions in the first germanium-silicon layer 31 gradually decreases from the side closer to the second germanium-silicon layer 32 to the side farther away from the second germanium-silicon layer 32. Among the multiple second semiconductor layers 3, the concentration of germanium ions in the second semiconductor layer 3 on the side closer to the substrate 1 is greater than the concentration of germanium ions in the second semiconductor layer 3 on the side farther away from the substrate 1.

[0056] Please continue reading Figure 2 As shown, a first semiconductor layer 2 and a second semiconductor layer 3 are alternately distributed in a direction perpendicular to the surface of the substrate 1 on the substrate 1, wherein the film layer closest to the substrate 1 is the second semiconductor layer 3, and the film layer farthest from the substrate 1 is the first semiconductor layer 2. The alternating distribution of the first semiconductor layer 2 and the second semiconductor layer 3 constitutes a multilayer stacked structure.

[0057] In an exemplary embodiment of this disclosure, the material of the first semiconductor layer 2 may be silicon, and the material of the second semiconductor layer 3 may be germanium-silicon. The thickness of the first semiconductor layer 2 may be greater than the thickness of the second semiconductor layer 3. For example, the thickness of the first semiconductor layer 2 may be 60 nm to 80 nm, such as 60 nm, 65 nm, 70 nm, 75 nm, or 80 nm. The thickness of the second semiconductor layer 3 may be 10 nm to 15 nm, such as 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm. Multiple sequentially alternating first semiconductor layers 2 and second semiconductor layers 3 can be formed on the surface of the substrate 1 using an epitaxial growth process.

[0058] In one exemplary embodiment of this disclosure, please continue to refer to Figure 2As shown, the second semiconductor layer 3 includes a first germanium-silicon layer 31 and a second germanium-silicon layer 32 stacked together. The germanium ion concentration in the second germanium-silicon layer 32 is fixed; that is, the concentration of germanium ions in different regions of the second germanium-silicon layer 32 is the same in the direction perpendicular to the surface of the substrate 1, and also the same in the direction parallel to the surface of the substrate 1. The concentration of germanium ions in the first germanium-silicon layer 31 gradually decreases from the side closer to the second germanium-silicon layer 32 to the side farther away from the second germanium-silicon layer 32. This design results in a lower concentration of germanium ions at the interface between the first semiconductor layer 2 formed on the first germanium-silicon layer 31 and the first germanium-silicon layer 31. The better lattice matching between the first germanium-silicon layer 31 and the first semiconductor layer 2 helps to reduce the lattice mismatch between the first semiconductor layer 2 and the second semiconductor layer 3, thereby reducing the dislocation density, reducing dislocation defects, and improving structural reliability. At the same time, since the germanium ions in the low-concentration germanium-silicon layer have a low diffusion capacity, they are not easy to diffuse into the adjacent first semiconductor layer 2. Therefore, the diffusion behavior of germanium ions can be effectively suppressed, thereby reducing the thickness of the interface layer between the first semiconductor layer 2 and the second semiconductor layer 3.

[0059] In one exemplary embodiment of this disclosure, please continue to refer to Figure 2 As shown, the first germanium-silicon layer 31 can be located on the side of the second germanium-silicon layer 32 away from the substrate 1. During the formation of the first germanium-silicon layer 31, the ratio of germanium ion source and silicon ion source in the reaction gas can be continuously adjusted. For example, when growing the first germanium-silicon layer 31 using an epitaxial growth process, germanane can be used as the germanium ion source and silane as the silicon ion source. By gradually increasing the flow rate of silane and decreasing the flow rate of germanane, the concentration of germanium ions in the grown first germanium-silicon layer 31 gradually decreases in the direction away from the second germanium-silicon layer 32. In one example, when growing the first germanium-silicon layer 31 using an epitaxial growth process, the flow rate of germanane decreases linearly.

[0060] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer 32 is equal to the maximum concentration of germanium ions in the first germanium-silicon layer 31. This design makes the concentration transition between the first germanium-silicon layer 31 and the second germanium-silicon layer 32 smoother, avoiding interface stress concentration caused by abrupt concentration changes. For example, the concentration of germanium ions in the second germanium-silicon layer 32 can be 20% to 30%, such as 20%, 22%, 24%, 26%, 28%, or 30%. Of course, the concentration of germanium ions in the second germanium-silicon layer 32 can also be other values, which will not be listed here. The concentration of germanium ions in the first germanium-silicon layer 31 can be gradually reduced from the same concentration as the second germanium-silicon layer 32 to 5% to 10%, for example, it can eventually be reduced to 5%, 6%, 7%, 8%, 9%, or 10%.

[0061] For example, if the germanium ion concentration in the second germanium-silicon layer 32 is 25%, the maximum concentration of germanium ions in the first germanium-silicon layer 31 is also 25%, and can be gradually reduced from 25% to 5%. In this way, there will be no concentration step between the first germanium-silicon layer 31 and the second germanium-silicon layer 32, and the lattice structure can remain continuous, which helps to reduce interface defects between the first germanium-silicon layer 31 and the second germanium-silicon layer 32. At the same time, the germanium concentration difference between the first germanium-silicon layer 31 and the first semiconductor layer 2 subsequently formed thereon is only 5%, and the lattice mismatch between the two is low, the dislocation density is low, and there are fewer dislocation defects.

[0062] In another exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer 32 gradually decreases from the side closer to the first germanium-silicon layer 31 to the side farther away from the first germanium-silicon layer 31, and the thickness of the first germanium-silicon layer 31 can be equal to the thickness of the second germanium-silicon layer 32. This design makes the germanium ion concentration of the second semiconductor layer 3 exhibit a bidirectional gradual change, that is, in the direction perpendicular to the surface of the substrate 1, the germanium ion concentration in the middle region of the second semiconductor layer 3 is the largest, and in the direction from the middle to both sides, the germanium ion concentration gradually decreases. At this time, the germanium ion concentration difference at the interface between the second semiconductor layer 3 and the first semiconductor layer 2 on its upper and lower sides (i.e., the interface between the first germanium-silicon layer 31 and the first semiconductor layer 2 and the interface between the second germanium-silicon layer 32 and the first semiconductor layer 2) is relatively small, so that during the formation of the first semiconductor layer 2 and the second semiconductor layer 3 by the epitaxial growth process, the degree of lattice mismatch between the two adjacent layers is low and the number of dislocation defects is small.

[0063] In one exemplary embodiment of this disclosure, taking the second germanium-silicon layer 32 of the second semiconductor layer 3 located on the side of the first germanium-silicon layer 31 closer to the substrate 1 as an example, during the growth of the second germanium-silicon layer 32, as the epitaxial growth time increases, the flow rate of germanane is gradually increased and the flow rate of silane is gradually decreased, so that the germanium ion concentration gradually increases from the side away from the substrate 1 to the side away from the substrate 1. Furthermore, after the formation of the second germanium-silicon layer 32, the first germanium-silicon layer 31 can be formed. At this time, the flow rate of silane can be gradually increased and the flow rate of germanium ane can be gradually decreased as time increases, ultimately forming the first germanium-silicon layer 31.

[0064] In one exemplary embodiment of this disclosure, when the concentration of germanium ions in the second germanium-silicon layer 32 gradually decreases from the side closer to the first germanium-silicon layer 31 to the side farther away from the first germanium-silicon layer 31, the maximum concentration of germanium ions in the second germanium-silicon layer 32 can be equal to the maximum concentration of germanium ions in the first germanium-silicon layer 31; the minimum concentration of germanium ions in the second germanium-silicon layer 32 can also be equal to the minimum concentration of germanium ions in the first germanium-silicon layer 31. For example, the maximum concentration of germanium ions in both the second germanium-silicon layer 32 and the first germanium-silicon layer 31 can be 20%, 22%, 24%, 26%, 28%, or 30%, and the minimum concentration of germanium ions in both the second germanium-silicon layer 32 and the first germanium-silicon layer 31 can be 5%, 6%, 7%, 8%, 9%, or 10%.

[0065] In yet another exemplary embodiment of this disclosure, such as Figure 3 As shown, the second semiconductor layer 3 further includes a third germanium-silicon layer 33 adjacent to the second germanium-silicon layer 32. The third germanium-silicon layer 33 is located on the side of the second germanium-silicon layer 32 away from the first germanium-silicon layer 31, and the thickness of the third germanium-silicon layer 33 can be equal to the thickness of the first germanium-silicon layer 31. The germanium ion concentration in the second germanium-silicon layer 32 is fixed, that is, the concentration of germanium ions in different regions of the second germanium-silicon layer 32 is the same in the direction perpendicular to the surface of the substrate 1, and the concentration of germanium ions in different regions of the second germanium-silicon layer 32 is also the same in the direction parallel to the surface of the substrate 1. The concentration of germanium ions in the third germanium-silicon layer 33 gradually decreases from the side closer to the second germanium-silicon layer 32 to the side farther away from the second germanium-silicon layer 32. This three-layer germanium-silicon design makes the concentration gradient of the second semiconductor layer 3 more gradual, which can better adapt to the stacking requirements of higher layers. At the same time, the germanium ion concentration difference at the interface between the second semiconductor layer 3 and the first semiconductor layer 2 on its upper and lower sides (i.e. the interface between the first germanium-silicon layer 31 and the first semiconductor layer 2 and the interface between the third germanium-silicon layer 33 and the first semiconductor layer 2) is relatively small. This results in a lower degree of lattice mismatch between adjacent layers and fewer dislocation defects during the formation of the first semiconductor layer 2 and the second semiconductor layer 3 by epitaxial growth process.

[0066] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the second germanium-silicon layer 32 is equal to the maximum concentration of germanium ions in the third germanium-silicon layer 33. For example, when the concentration of germanium ions in the second germanium-silicon layer 32 is 28%, the maximum concentration of germanium ions in the third germanium-silicon layer 33 is also 28%; when the concentration of germanium ions in the second germanium-silicon layer 32 is 20%, the maximum concentration of germanium ions in the third germanium-silicon layer 33 is also 20%. This design makes the concentration transition between the second germanium-silicon layer 32 and the third germanium-silicon layer 33 smoother, further reducing interface defects.

[0067] In one exemplary embodiment of this disclosure, the concentration of germanium ions in the third germanium-silicon layer 33 is gradually reduced from the same concentration as that in the second germanium-silicon layer 32 to 5% to 10%, for example, it may eventually be reduced to 5%, 6%, 7%, 8%, 9% or 10%.

[0068] In one exemplary embodiment of this disclosure, the minimum concentration of germanium ions in the third germanium-silicon layer 33 is equal to the minimum concentration of germanium ions in the first germanium-silicon layer 31. For example, when the minimum concentration of germanium ions in the first germanium-silicon layer 31 is 10%, the minimum concentration of germanium ions in the third germanium-silicon layer 33 is also 10%; when the minimum concentration of germanium ions in the first germanium-silicon layer 31 is 8%, the minimum concentration of germanium ions in the third germanium-silicon layer 33 is also 8%; when the minimum concentration of germanium ions in the first germanium-silicon layer 31 is 5%, the minimum concentration of germanium ions in the third germanium-silicon layer 33 is also 5%.

[0069] In one exemplary embodiment of this disclosure, taking the third germanium-silicon layer 33 located on the side of the second germanium-silicon layer 32 closer to the substrate 1 as an example, during the growth of the third germanium-silicon layer 33, as the growth time increases, the flow rate of germane is gradually increased and the flow rate of silane is gradually decreased, so that the germanium ion concentration gradually increases from the side closer to the substrate 1 to the side farther away from the substrate 1. Furthermore, after the formation of the third germanium-silicon layer 33, the flow rates of both germane and silane can be kept constant, thereby forming the second germanium-silicon layer 32, and finally forming the first germanium-silicon layer 31.

[0070] In one exemplary embodiment of this disclosure, among the plurality of second semiconductor layers 3, the concentration of germanium ions in the second semiconductor layer 3 closer to the substrate 1 is greater than the concentration of germanium ions in the second semiconductor layer 3 farther from the substrate 1. Since the lower second semiconductor layer 3 undergoes a longer heat treatment time during the manufacturing process, by ensuring that the concentration of germanium ions in the second semiconductor layer 3 closer to the substrate 1 is greater than the concentration of germanium ions in the second semiconductor layer 3 farther from the substrate 1, the high concentration design can compensate for the concentration decay caused by thermal diffusion of germanium ions in the lower second semiconductor layer 3 during heat treatment. This ensures that the concentration of germanium ions in each second semiconductor layer 3 in the structure after heat treatment is within a preset range, which helps to further improve product reliability.

[0071] In one exemplary embodiment of this disclosure, the concentration of the largest germanium ion in the second semiconductor layer 3 when forming the lowest layer is greater than 3% to 4% of the concentration of the largest germanium ion in the second semiconductor layer 3 when forming the highest layer. For example, when forming the lowest layer, the concentration of the largest germanium ion in the second semiconductor layer 3 is 30%, and when forming the highest layer, the concentration of the largest germanium ion in the second semiconductor layer 3 is 26%. After thermal diffusion throughout the process, as the concentration of germanium ions in the lowest layer decreases, the final concentration of germanium ions in that layer will approach the concentration of germanium ions in the highest layer.

[0072] In one exemplary embodiment of this disclosure, among the plurality of second semiconductor layers 3, the thickness of the second semiconductor layer 3 on the side closer to the substrate 1 is smaller than the thickness of the second semiconductor layer 3 on the side farther from the substrate 1. This thickness distribution design, combined with the concentration distribution design, can further optimize the uniformity of the structure and improve product reliability.

[0073] In one exemplary embodiment of this disclosure, such as Figure 4 As shown, the first semiconductor layer 2 may include a support region 21 and an active region 22 arranged side-by-side along a direction parallel to the surface of the substrate 1. The active region 22 is the core region for realizing the electrical functions of the device and is used to form transistors. Please refer to some embodiments of this disclosure. Figure 4 As shown, the first germanium-silicon layer 31 may include a first sub-film layer 311 and a second sub-film layer 312. The second sub-film layer 312 is located between the second germanium-silicon layer 32 and the first sub-film layer 311. Both the first sub-film layer 311 and the second sub-film layer 312 are films with gradually changing germanium ion concentrations. The concentration of germanium ions in the second sub-film layer 312 gradually decreases from the side closer to the second germanium-silicon layer 32 to the side farther away from the second germanium-silicon layer 32. The concentration of germanium ions in the first sub-film layer 311 gradually decreases from the side closer to the second sub-film layer 312 to the side farther away from the second sub-film layer 312. The maximum concentration of germanium ions in the first sub-film layer 311 is equal to the minimum concentration of germanium ions in the second sub-film layer 312.

[0074] The method for forming a semiconductor structure disclosed herein may further include steps S210-S250, wherein: In step S210, the second germanium-silicon layer 32 and the second sub-film layer 312 are etched laterally to form a first recess 4; the first recess 4 exposes the active region 22 and the first sub-film layer 311 corresponding to the active region 22.

[0075] The second germanium-silicon layer 32 and the second sub-film layer 312 can be selectively etched using an etching process to form a first recess 4 in the first sub-film layer 311 that exposes the active region 22 and the portion in contact with the active region 22. It should be noted that when there are multiple second semiconductor layers 3, each second germanium-silicon layer 32 and the second sub-film layer 312 in each second semiconductor layer 3 can form a first recess 4 after lateral etching; that is, there are multiple first recesses 4, which are spaced apart along a direction perpendicular to the surface of the substrate 1. It is understood that the stacked structure can be etched using a wet etching process, for example, using hydrofluoric acid as the etching solution. The wet etching process has an etching selectivity ratio of germanium-silicon to silicon of 10:1 to 20:1. Because the germanium ion concentration in the second germanium-silicon layer 32 and the second sub-film layer 312 is high, they are selectively etched away, while because the germanium ion concentration in the first sub-film layer 311 is low, it is retained in the structure. In one embodiment of this disclosure, the structure after step S210 is as follows: Figure 5 As shown.

[0076] In step S220, the first sub-film layer 311 exposed in the first recess 4 is removed and the active region 22 is thinned to form the second recess 5; the remaining first sub-film layer 311 has a groove 6 on the end face near the second recess 5.

[0077] A mask layer 15 can be formed on the topmost first semiconductor layer 2, and then the first sub-film layer 311 exposed in the first recess 4 can be removed by etching. During this process, the active region 22 exposed in the first recess 4 can be thinned simultaneously, and part of the second germanium-silicon layer 32 and the ends of the second sub-film layer 312 exposed in the first recess 4 are consumed. During etching, due to the different germanium ion concentrations of the first sub-film layer 311 and the second sub-film layer 312 in contact with it, the etching rates differ. The etching rate of the first sub-film layer 311 will be slightly higher than that of the second sub-film layer 312, thus forming a groove 6 on the remaining end face of the first sub-film layer 311 near the second recess 5. It is understood that the stacked structure can be etched using a wet etching process, for example, using tetramethylammonium hydroxide (TMAH) as the etchant. The wet etching process has an etching selectivity ratio of silicon to germanium-silicon of 10:1 to 20:1. Because the germanium ion concentration in the first sub-film layer 311 is low, it will be selectively etched away.

[0078] Meanwhile, because the germanium ion concentrations in the first sub-film layer 311 and the first semiconductor layer 2 are different, and the germanium ion concentration in the first sub-film layer 311 is asymmetrical, the thinning thicknesses on the upper and lower sides of the first semiconductor layer 2 are inconsistent, resulting in the second recess 5 formed after etching being asymmetrical in the direction perpendicular to the surface of the substrate 1. In one embodiment of this disclosure, the structure after step S220 is as follows: Figure 6 As shown.

[0079] Step S230: Forming a spacer layer 7, the spacer layer 7 fills the groove 6 and the second recess 5, and the portion of the spacer layer 7 located in the groove 6 forms a protrusion 711.

[0080] The spacer layer 7 is made of an insulating material, such as one or more of silicon nitride, silicon oxide, silicon carbide nitride, or silicon oxynitride. In an exemplary embodiment of this disclosure, the spacer layer 7 may include a first insulating layer 71 conformally covering the second recess 5 and a second insulating layer 72 located on the surface of the first insulating layer 71 and filling the remaining space in the second recess 5. The first insulating layer 71 may be made of silicon nitride, and the second insulating layer 72 may be made of silicon oxide. The first insulating layer 71 and the second insulating layer 72 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It should be noted that the first insulating layer 71 may fill the groove 6, meaning the portion of the first insulating layer 71 located within the groove 6 can be defined as a protrusion 711. Furthermore, because the second recess 5 is asymmetrical in the direction perpendicular to the surface of the substrate 1, the formed first insulating layer 71 also has an asymmetrical structure in the direction perpendicular to the surface of the substrate 1 (e.g., the side of one end of the first insulating layer 71 furthest from the substrate 1 protrudes outward relative to the side closer to the substrate 1). It should be noted that the first insulating layer 71 may surround the first semiconductor layer 2, and the first insulating layers 71 surrounding adjacent first semiconductor layers 2 in the horizontal direction are connected to each other. In one embodiment of this disclosure, the structure after completing step S230 is as follows: Figure 7 As shown.

[0081] In step S240, the remaining second semiconductor layer 3 and support region 21 are removed to expose the end of the active region 22.

[0082] In one exemplary embodiment of this disclosure, such as Figure 8 As shown, the active region 22 may include a first source / drain region 221, a channel region 222, and a second source / drain region 223 sequentially distributed along a direction parallel to the surface of the substrate 1. Before removing the remaining second semiconductor layer 3, the formation method of this disclosure may further include steps S310-S340, wherein: Step S310: The first insulating layer 71 is etched back to expose the surface of the channel region 222 and the second source / drain region 223.

[0083] Laterally etching can be performed on the first insulating layer 71 to expose the channel region 222 and the second source / drain region 223 of each first semiconductor layer 2, thereby providing space for the subsequent formation of word lines 13. In one embodiment of this disclosure, the structure after completing step S310 is as follows: Figure 8 As shown.

[0084] Step S320: At least a gate oxide layer 12 is formed on the surface of the channel region 222.

[0085] The gate oxide layer 12 can be made of an insulating material, for example, silicon oxide. Figure 9 As shown, the gate oxide layer 12 can be formed on the channel region 222 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or in-situ water vapor oxidation. It should be noted that, in some embodiments of this disclosure, for process convenience, the gate oxide layer 12 can be formed simultaneously on the surface of the second source / drain region 223, that is, the gate oxide layer 12 can simultaneously cover the surfaces of the channel region 222 and the second source / drain region 223.

[0086] Step S330: Word lines 13 are formed on the surface of the gate oxide layer 12.

[0087] Conductive material can be deposited on the gate oxide layer 12 to fill the space formed after etching back the first insulating layer 71. Subsequently, the conductive material can be etched back to remove the conductive material in the region corresponding to the second source / drain region 223, leaving only the conductive material corresponding to the channel region 222. The remaining conductive material can be used as word line 13. Word line 13 extends in a direction parallel to the surface of substrate 1.

[0088] In step S340, a third insulating layer 14 is formed on the side of the word line 13 away from the remaining first insulating layer 71.

[0089] The material of the third insulating layer 14 can be the same as that of the first insulating layer 71. For example, the material of the third insulating layer 14 can be silicon nitride. The third insulating layer 14 can insulate the ends of the word line 13 away from the first insulating layer 71, thereby reducing the risk of short circuits or coupling between the bit line (not shown) subsequently formed at the end of the second source / drain region 223 and the word line 13, which helps improve product yield. In one embodiment of this disclosure, the structure after step S340 is as follows... Figure 9 As shown.

[0090] like Figure 10 As shown, after forming the third insulating layer 14, the second germanium-silicon layer 32 and the second sub-film layer 312 in the remaining second semiconductor layer 3 can be removed first, thereby forming the third recess 8; as Figure 11 As shown, a dielectric material can be filled into the third recess 8 to form a dielectric layer 9. The dielectric material can be an insulating material, for example, silicon oxide.

[0091] like Figure 12 As shown, after forming the dielectric layer 9, the remaining first sub-film layers 311 and the support regions 21 in each first semiconductor layer 2 can be etched to form a plurality of fourth recesses 10. The plurality of fourth recesses 10 can be distributed at intervals along a direction perpendicular to the surface of the substrate 1, and adjacent fourth recesses 10 can be isolated by the dielectric layer 9. The bottom of the fourth recesses 10 can expose the end face of the first source / drain region 221 in the active region 22.

[0092] It should be noted that during the etching of the remaining first sub-film layers 311 and the first semiconductor layers 2, due to the different concentrations of germanium ions in the first sub-film layers 311 and the first semiconductor layers 2, the first semiconductor layer 2 is etched relatively faster than the first sub-film layer 311. Therefore, after the first sub-film layer 311 is etched, the first semiconductor layer 2 is etched slightly more. Furthermore, it has been determined that the end face of the remaining first source / drain region 221 after etching, which is far from the channel region 222, is a slope. The fourth recess 10 formed after etching can expose at least part of the sidewall of the protrusion 711.

[0093] In step S250, multiple capacitor structures 11 are formed that are respectively coupled to active regions 22 in different first semiconductor layers 2.

[0094] A capacitor structure 11 can be formed within the fourth recess 10. The capacitor structure 11 may include a first electrode layer 111, a capacitor dielectric layer 112, and a second electrode layer 113. The first electrode layer 111 conformally covers the sidewall of the fourth recess 10 and contacts the top of the protrusion 711 exposed in the fourth recess 10. Simultaneously, since the end face of the first source / drain region 221 in contact with the first electrode layer 111 is inclined, the contact area between the first electrode layer 111 and the first source / drain region 221 is large, resulting in low contact resistance. The capacitor dielectric layer 112 conformally covers the surface of the first electrode layer 111, and the second electrode layer 113 is located on the surface of the capacitor dielectric layer 112 and can fill the fourth recess 10. In this embodiment, the accommodating space of the first electrode layer 111 in the fourth recess 10 is widened, and short circuits between the first electrode layers 111 are avoided by the dielectric layer 9, thus improving the process window for fabricating the capacitor structure 11. In one embodiment of this disclosure, the structure after step S250 is as follows... Figure 13 As shown. In some instances, the dimension of the capacitor structure 11 in the direction perpendicular to the surface of the substrate 1 is greater than the maximum thickness of the first source / drain region 221 in the direction perpendicular to the surface of the substrate 1.

[0095] In one exemplary embodiment of this disclosure, such as Figure 14As shown, while the first germanium-silicon layer 31 includes a first sub-film layer 311 and a second sub-film layer 312, the third germanium-silicon layer 33 includes a third sub-film layer 331 and a fourth sub-film layer 332, with the fourth sub-film layer 332 located between the second germanium-silicon layer 32 and the third sub-film layer 331. Both the third sub-film layer 331 and the fourth sub-film layer 332 are films with gradually changing germanium ion concentrations. The concentration of germanium ions in the fourth sub-film layer 332 gradually decreases from the side closer to the second germanium-silicon layer 32 to the side farther away from the second germanium-silicon layer 32. Similarly, the concentration of germanium ions in the third sub-film layer 331 gradually decreases from the side closer to the fourth sub-film layer 332 to the side farther away from the fourth sub-film layer 332. Furthermore, the maximum concentration of germanium ions in the third sub-film layer 331 is equal to the minimum concentration of germanium ions in the fourth sub-film layer 332.

[0096] In one exemplary embodiment of this disclosure, the method for forming this disclosure may further include steps S410-S450, wherein: In step S410, the second germanium-silicon layer 32, the second sub-film layer 312, and the fourth sub-film layer 332 are etched laterally to form a first recess 4; the first recess 4 exposes the first sub-film layer 311 and the third sub-film layer 331 corresponding to the active region 22.

[0097] The second germanium-silicon layer 32, the second sub-film layer 312, and the fourth sub-film layer 332 can be selectively etched using an etching process to form a first recess 4. This first recess 4 exposes the portion of the first sub-film layer 311 corresponding to the active region 22 and the portion of the third sub-film layer 331 corresponding to the active region 22. It should be noted that when there are multiple second semiconductor layers 3, each second semiconductor layer 3 can form a first recess 4 after lateral etching of the second germanium-silicon layer 32, the second sub-film layer 312, and the fourth sub-film layer 332. That is, there are multiple first recesses 4, and the multiple first recesses 4 are distributed at intervals along a direction perpendicular to the surface of the substrate 1. It is understood that the stacked structure can be etched using a wet etching process, for example, using hydrofluoric acid as the etchant. The wet etching process has an etching selectivity ratio of germanium-silicon to silicon of 10:1 to 20:1. Because the germanium ion concentration in the second germanium-silicon layer 32, the second sub-film layer 312, and the fourth sub-film layer 332 is relatively high, they will be selectively etched away. However, because the germanium ion concentration in the first sub-film layer 311 and the third sub-film layer 331 is relatively low, they will remain in the structure. In one embodiment of this disclosure, the structure after step S410 is as follows: Figure 15 As shown.

[0098] In step S420, the first sub-film layer 311 and the third sub-film layer 331 exposed in the first recess 4 are removed, and the active region 22 exposed after removing part of the first sub-film layer 311 and part of the third sub-film layer 331 is thinned to form the second recess 5; the remaining first sub-film layer 311 and the remaining third sub-film layer 331 have grooves 6 on the end faces near the second recess 5.

[0099] For example, a mask layer 15 can be formed on the topmost first semiconductor layer 2. Then, the first sub-film layer 311 and the third sub-film layer 331 exposed in the first recess 4 can be removed by etching. In this process, the active region 22 exposed after removing the first sub-film layer 311 and the third sub-film layer 331 exposed in the first recess 4 can be thinned at the same time, and part of the ends of the second germanium silicon layer 32, the second sub-film layer 312 and the fourth sub-film layer 332 exposed in the first recess 4 can be consumed. During the etching process, due to the different germanium ion concentrations of the first sub-film layer 311 and the second sub-film layer 312 in contact with it, the etching rates differ. During etching, the etching rate of the first sub-film layer 311 is slightly higher than that of the second sub-film layer 312. Therefore, a groove 6 is formed on the remaining end face of the first sub-film layer 311 near the second recess 5. Simultaneously, due to the different germanium ion concentrations of the third sub-film layer 331 and the fourth sub-film layer 332 in contact with it, the etching rates differ. During etching, the etching rate of the third sub-film layer 331 is slightly higher than that of the fourth sub-film layer 332. Therefore, a groove 6 is formed on the remaining end face of the third sub-film layer 331 near the second recess 5. It is understood that the stacked structure can be etched using a wet etching process, for example, using tetramethylammonium hydroxide (TMAH) as the etching solution. The wet etching process has an etching selectivity ratio of silicon to germanium silicon of 10:1 to 20:1. In one embodiment of this disclosure, the structure after step S420 is as follows... Figure 16 As shown.

[0100] Step S430: Forming a spacer layer 7, which fills the groove 6 and the second recess 5, with the portion of the spacer layer 7 located in the groove 6 forming a protrusion 711.

[0101] The process of forming the spacer layer 7 in step S430 is similar to that in step S230; please refer to step S230 for details, which will not be repeated here. In one embodiment of this disclosure, the structure after completing step S430 is as follows: Figure 17 As shown.

[0102] In step S440, the remaining second semiconductor layer 3 and support region 21 are removed to expose the end of the active region 22.

[0103] In some embodiments of this disclosure, before performing step S440, the formation method may further include forming a gate oxide layer 12, a word line 13, and a third insulating layer 14. The specific formation process of the gate oxide layer 12, word line 13, and third insulating layer 14 is detailed in steps S310-S340, and will not be repeated here. In one embodiment of this disclosure, the structure after forming the gate oxide layer 12, word line 13, and third insulating layer 14 is as follows... Figure 18 As shown.

[0104] like Figure 19 As shown, after forming the third insulating layer 14, the second germanium-silicon layer 32, the second sub-film layer 312, and the fourth sub-film layer 332 in the remaining second semiconductor layer 3 can be removed first to form the third recess 8; as Figure 20 As shown, the remaining first sub-film layer 311 and third sub-film layer 331 can be removed, and the support region 21 exposed after the removal of the first sub-film layer 311 and third sub-film layer 331 can be thinned, thereby forming a fourth recess 10. The fourth recess 10 can expose the end of the spacer layer 7 near the support region 21, that is, the protrusion 711 is exposed in the fourth recess 10. Figure 21 As shown, a dielectric material can be filled into the fourth recess 10 to form a dielectric layer 9. The dielectric material can be an insulating material, for example, silicon oxide.

[0105] like Figure 22 As shown, after forming the dielectric layer 9, the support regions 21 in each of the first semiconductor layers 2 can be etched to form a plurality of fifth recesses 16. The plurality of fifth recesses 16 can be spaced apart along a direction perpendicular to the surface of the substrate 1, and adjacent fifth recesses 16 can be isolated by the dielectric layer 9. The bottom of the fifth recesses 16 can expose the end face of the first source / drain region 221 in the active region 22. The cross-section of the first source / drain region 221 is fan-shaped, and the first source / drain region 221 has a gradually increasing thickness in the direction away from the channel region 222.

[0106] In step S450, multiple capacitor structures 11 are formed that are respectively coupled to active regions 22 in different first semiconductor layers 2.

[0107] For example, a first electrode layer 111 can be formed in each of the fifth recesses 16. The first electrode layer 111 can conformally cover the inner wall of the fifth recess 16, and after forming the first electrode layer 111, the dielectric layer 9 can be removed. Subsequently, a capacitor dielectric layer 112 is formed on the surface of the structure formed by the first electrode layer 111 and the spacer layer 7. Then, a second electrode layer 113 can be formed on the capacitor dielectric layer 112, and the second electrode layer 113 can fill the remaining space in each of the fifth recesses 16. In this embodiment, the capacitor structure 11 is a double-sided capacitor, which further improves the capacitance. In one embodiment of this disclosure, the structure after completing step S450 is as follows: Figure 23 As shown.

[0108] In one exemplary embodiment of this disclosure, the formation method may further include: forming a bit line on the side of the second source / drain region 223 away from the channel region 222, the bit line being coupled to each of the second source / drain regions 223 distributed along the vertical direction. The vertical direction refers to the direction perpendicular to the surface of the substrate 1.

[0109] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0110] This disclosure also provides a semiconductor structure formed by the semiconductor structure formation method in any of the above embodiments. Please continue to refer to... Figure 13 and Figure 23 As shown, the semiconductor structure includes a substrate 1, multiple first semiconductor layers 2, a spacer layer 7, and multiple capacitor structures 11, wherein: Multiple first semiconductor layers 2 are spaced apart along a direction perpendicular to the surface of the substrate 1. Each first semiconductor layer 2 includes a first source / drain region 221, a channel region 222, and a second source / drain region 223 that are sequentially distributed along a direction parallel to the surface of the substrate 1. The spacer layer 7 is located between adjacent first semiconductor layers 2 and at least covers the surface of the first source / drain region 221. The end of the spacer layer 7 that covers the surface of the first source / drain region 221 and is away from the channel region 222 has a protrusion 711 that protrudes toward the side away from the channel region 222. Multiple capacitor structures 11 are coupled to different first source / drain regions 221 respectively; protrusions 711 are located between the first electrode layers 111 of adjacent capacitor structures 11; or, in adjacent capacitor structures 11, one end of the portion of the first electrode layer 111 of the upper capacitor structure 11 that is closer to the substrate 1 is in contact with the top of the protrusion 711, and one end of the portion of the first electrode layer 111 of the lower capacitor structure 11 that is farther from the substrate 1 is in contact with the bottom of the protrusion 711.

[0111] In the semiconductor structure formed by the above-described semiconductor structure formation method, there are fewer stacking fault defects in the different first semiconductor layers 2, resulting in smaller performance differences in transistors formed from different layers of the semiconductor structure and higher structural reliability. Simultaneously, when the bump 711 is located between the first electrode layers 111 of adjacent capacitor structures 11, the bump 711 can insulate and isolate the adjacent first electrode layers 111, helping to reduce the risk of leakage or short circuit between adjacent first electrode layers 111, thus improving product yield and reliability. When, in adjacent capacitor structures 11, one end of the portion of the first electrode layer 111 of the upper capacitor structure 11 closer to the substrate 1 contacts the top of the bump 711, and one end of the portion of the first electrode layer 111 of the lower capacitor structure 11 farther from the substrate 1 contacts the bottom of the bump 711, the design of the bump 711 allows for a staggered distribution of the adjacent regions of the first electrode layers 111 in the adjacent capacitor structures 11, reducing the risk of leakage or short circuit between adjacent first electrode layers 111.

[0112] The following provides a detailed description of the various parts of the semiconductor structure disclosed herein, along with their specific details: The substrate 1 may be a planar structure and its material may be a semiconductor material, such as silicon, but not limited to silicon or other semiconductor materials. It may be undoped single crystal silicon or single crystal silicon doped with elements such as phosphorus and boron. No special limitation is made on the material of the substrate 1 here.

[0113] The material of the first semiconductor layer 2 may be single crystal silicon. There may be multiple first semiconductor layers 2. Multiple first semiconductor layers 2 may be distributed at intervals along a direction perpendicular to the surface of the substrate 1. The first semiconductor layer 2 may be strip-shaped. The first semiconductor layer 2 may include a first source / drain region 221, a channel region 222 and a second source / drain region 223 distributed sequentially along a direction parallel to the surface of the substrate 1 (i.e., its length direction).

[0114] The spacer layer 7 is located between adjacent first semiconductor layers 2 and at least covers the surface of the first source / drain region 221. The end of the spacer layer 7 that covers the surface of the first source / drain region 221 and is away from the channel region 222 has a protrusion 711 that protrudes toward the side away from the channel region 222.

[0115] In one exemplary embodiment of this disclosure, the spacer layer 7 may be a composite film structure. For example, the spacer layer 7 may include a first insulating layer 71 and a second insulating layer 72. The first insulating layer 71 may have a U-shaped cross-section in a direction perpendicular to the surface of the substrate 1, and the first insulating layer 71 may cover the first source / drain regions 221 of two adjacent first semiconductor layers 2. The end of the first insulating layer 71 away from the channel region 222 may have a protrusion 711.

[0116] In one exemplary embodiment of this disclosure, the semiconductor structure may further include a gate oxide layer 12 and a word line 13. The gate oxide layer 12 may be made of silicon oxide and may at least cover the perimeter of the surface of the channel region 222. The word line 13 may be made of a conductive material and is located on the gate oxide layer 12, and may cover the outer perimeter of the gate oxide layer 12. The surface of the word line 13 away from the gate oxide layer 12 is flush with the surface of the first insulating layer 71 away from the first source / drain region 221.

[0117] In one exemplary embodiment of this disclosure, the semiconductor structure may further include a third insulating layer 14, which may be located on the second source / drain region 223. The material of the third insulating layer 14 is the same as that of the first insulating layer 71. For example, both the first insulating layer 71 and the third insulating layer 14 may be made of silicon nitride. The second insulating layer 72 may be located on the surface of the structure formed by the first insulating layer 71, the word line 13, and the third insulating layer 14, and may fill the remaining gaps between adjacent first semiconductor layers 2. The material of the second insulating layer 72 may be different from that of the first insulating layer 71. For example, the material of the second insulating layer 72 may be silicon oxide.

[0118] Multiple capacitor structures 11 are respectively coupled to the end faces of different first source / drain regions 221 that are far from the channel region 222. In an exemplary embodiment of this disclosure, the capacitor structure 11 includes a first electrode layer 111, a capacitor dielectric layer 112, and a second electrode layer 113. The first electrode layer 111 may be strip-shaped, and the material of the first electrode layer 111 may be a material with good conductivity, for example, the material of the first electrode layer 111 may be titanium nitride. The capacitor dielectric layer 112 conformally covers the surface of the first electrode layer 111, and its material may be an insulating material with a high dielectric constant, for example, its material may be alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof, and of course, other materials may also be used, which will not be listed here. The second electrode layer 113 is located on the surface of the capacitor dielectric layer 112, and its material may also be a material with good conductivity, for example, the material of the second electrode layer 113 may be titanium nitride.

[0119] In one exemplary embodiment of this disclosure, please continue to refer to Figure 13 As shown, in adjacent capacitor structures 11, one end of the portion of the first electrode layer 111 of the upper capacitor structure 11 near the substrate 1 is in contact with the top of the protrusion 711, and one end of the portion of the first electrode layer 111 of the lower capacitor structure 11 away from the substrate 1 is in contact with the bottom of the protrusion 711. In this case, the design of the protrusion 711 allows for a staggered distribution of the regions in the first electrode layers 111 of adjacent capacitor structures 11, thereby reducing the risk of leakage or short circuit between adjacent first electrode layers 111.

[0120] In one exemplary embodiment of this disclosure, please continue to refer to Figure 13 As shown, the end face of the first source / drain region 221 that is far from the channel region 222 can be a slope, and the first electrode layer 111 covers the slope. At this time, the contact area between the first electrode layer 111 and the first source / drain region 221 is relatively large, and the contact resistance is small.

[0121] In one exemplary embodiment of this disclosure, please continue to refer to Figure 13 As shown, the capacitor dielectric layer 112 can cover the inner surface of the first electrode layer 111 in a conformal manner, and the second electrode layer 113 is located on the surface of the capacitor dielectric layer 112. At this time, the first electrode layer 111, the capacitor dielectric layer 112 and the second electrode layer 113 can form a cylindrical single-sided capacitor.

[0122] In one exemplary embodiment of this disclosure, please continue to refer to Figure 13 As shown, a dielectric layer 9 is provided between the first electrode layers 111 of adjacent capacitor structures 11. The dielectric layer 9 can be made of an insulating material, for example, silicon oxide. Among the plurality of dielectric layers 9, the thickness of the dielectric layer 9 on the side closer to the substrate 1 is less than the thickness of the dielectric layer 9 on the side farther from the substrate 1.

[0123] In one exemplary embodiment of this disclosure, please continue to refer to Figure 23 As shown, the protrusion 711 is located between the first electrode layers 111 of adjacent capacitor structures 11. In this case, the protrusion 711 can be used to insulate and isolate the adjacent first electrode layers 111, which helps to reduce the risk of leakage or short circuit between adjacent first electrode layers 111, and helps to improve product yield and reliability.

[0124] In one exemplary embodiment of this disclosure, please continue to refer to Figure 23 As shown, the capacitor dielectric layer 112 can conformally cover the surface of the structure jointly formed by the first electrode layer 111 and the spacer layer 7, and the second electrode layer 113 can conformally cover the surface of the capacitor dielectric layer 112. At this time, the first electrode layer 111, the capacitor dielectric layer 112 and the second electrode layer 113 can form a double-sided capacitor.

[0125] This disclosure also provides an electronic device with storage functionality, such as... Figure 24As shown, the electronic device 20 includes a processing device 201 and a storage device 202 electrically connected to the processing device 201. The storage device 202 includes the semiconductor structure 203 in any of the above embodiments. The electronic device 20 can be a terminal device, such as a personal computer, mobile phone, tablet computer, consumer electronics product, such as smart home appliances, autonomous driving, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality devices, augmented reality devices, and can also be a server, data center, etc. The storage function in the electronic device 20 can be implemented through these storage devices 202.

[0126] In some embodiments, the processing device 201 and the memory device 202 can be two independent chips forming a separate memory. In other embodiments, the memory device 202 and the processing device 201 can also be integrated into the same chip to form an embedded memory. This electronic device 20 can solve the same technical problem and achieve the same expected effect as the semiconductor structure 203 in any of the above embodiments.

[0127] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate; forming first semiconductor layers and second semiconductor layers on the substrate, the second semiconductor layers comprising first germanium-silicon layers and second germanium-silicon layers, the concentration of germanium ions in the first germanium-silicon layers gradually decreasing from the side close to the second germanium-silicon layers to the side away from the second germanium-silicon layers; in the plurality of second semiconductor layers, the concentration of germanium ions in the second semiconductor layers close to the substrate is greater than the concentration of germanium ions in the second semiconductor layers away from the substrate.

2. The method of forming of claim 1, wherein, the concentration of germanium ions in the second germanium-silicon layers is equal to the maximum concentration of germanium ions in the first germanium-silicon layers.

3. The method of forming of claim 2, wherein, the concentration of germanium ions in the second germanium-silicon layers is 20%-30%, and the concentration of germanium ions in the first germanium-silicon layers gradually decreases from the concentration equal to that of the second germanium-silicon layers to 5%-10%.

4. The method of forming of claim 1, wherein, the concentration of germanium ions in the second germanium-silicon layers gradually decreases from the side close to the first germanium-silicon layers to the side away from the first germanium-silicon layers.

5. The method of forming of claim 2, wherein, the second semiconductor layers further comprise third germanium-silicon layers adjacent to the second germanium-silicon layers, the third germanium-silicon layers being located on the side of the second germanium-silicon layers away from the first germanium-silicon layers; the concentration of germanium ions in the third germanium-silicon layers gradually decreases from the side close to the second germanium-silicon layers to the side away from the second germanium-silicon layers.

6. The method of forming of claim 5, wherein, the concentration of germanium ions in the second germanium-silicon layers is equal to the maximum concentration of germanium ions in the third germanium-silicon layers.

7. The method of forming of claim 5, wherein, the concentration of germanium ions in the second germanium-silicon layers is 20%-30%, and the concentration of germanium ions in the third germanium-silicon layers gradually decreases from the concentration equal to that of the second germanium-silicon layers to 5%-10%.

8. The forming method of any of claims 1-7, wherein, in the plurality of second semiconductor layers, the thickness of the second semiconductor layers close to the substrate is less than the thickness of the second semiconductor layers away from the substrate.

9. The method of forming of claim 1, wherein, the first semiconductor layers comprise support regions and active regions distributed side by side along the direction parallel to the surface of the substrate, and the first germanium-silicon layers comprise first sub-film layers and second sub-film layers, the second sub-film layers being located between the second germanium-silicon layers and the first sub-film layers, and the forming method further comprises: laterally etching the second germanium-silicon layers and the second sub-film layers to form first recesses; the first recesses expose the active regions and the first sub-film layers corresponding to the active regions; removing the first sub-film layers exposed in the first recesses and thinning the active regions to form second recesses; in the remaining first sub-film layers, the end surface close to the second recesses has a groove; forming a spacing layer, the spacing layer filling the grooves and the second recesses, and the part of the spacing layer located in the grooves forming protrusions; removing the remaining second semiconductor layers and the support regions to expose the end of the active regions; forming a plurality of capacitive structures respectively coupled to the active regions in different first semiconductor layers.

10. The method of forming of claim 5, wherein, The first semiconductor layer includes support regions and active regions distributed side by side in a direction parallel to the surface of the substrate, the first germanium-silicon layer includes a first sub-film layer and a second sub-film layer, the second sub-film layer is located between the second germanium-silicon layer and the first sub-film layer; the third germanium-silicon layer includes a third sub-film layer and a fourth sub-film layer, the fourth sub-film layer is located between the second germanium-silicon layer and the third sub-film layer, and the forming method further includes: Transversely etching the second germanium-silicon layer, the second sub-film layer and the fourth sub-film layer to form a first recess; the first recess exposes the first sub-film layer and the third sub-film layer corresponding to the active regions; Removing the first sub-film layer and the third sub-film layer exposed in the first recess and thinning the active regions to form a second recess; the remaining first sub-film layer and the remaining third sub-film layer have grooves near the end faces of the second recess; Forming a spacing layer, the spacing layer fills the grooves and the second recess, and the part of the spacing layer located in the grooves constitutes a protrusion; Removing the remaining second semiconductor layer and the support regions to expose the end of the active region; Forming a plurality of capacitive structures respectively coupled with the active regions in different first semiconductor layers.

11. The forming method of claim 9 or 10, wherein, The active region includes a first source-drain region, a channel region and a second source-drain region distributed in sequence in a direction parallel to the surface of the substrate, the capacitive structure is coupled with the first source-drain region, and the spacing layer includes a first insulating layer conformally covering the second recess and a second insulating layer located on the surface of the first insulating layer and filling the remaining space in the second recess; Before removing the remaining second semiconductor layer, the forming method further includes: Re-etching the first insulating layer to expose the surfaces of the channel region and the second source-drain region; Forming a gate oxide layer at least on the surface of the channel region; Forming a word line on the surface of the gate oxide layer; Forming a third insulating layer on the side of the word line away from the remaining first insulating layer.

12. A semiconductor structure, characterized by Comprise: a substrate and a plurality of first semiconductor layers spaced apart in a direction perpendicular to the surface of the substrate, the first semiconductor layer includes a first source-drain region, a channel region and a second source-drain region distributed in sequence in a direction parallel to the surface of the substrate; a spacing layer located between adjacent first semiconductor layers and covering at least the surface of the first source-drain region, the spacing layer having a protrusion protruding away from the side of the channel region on the surface of the first source-drain region and away from the channel region; a plurality of capacitive structures respectively coupled with different first source-drain regions; the protrusion is located between the first electrode layers of adjacent capacitive structures; or, in adjacent capacitive structures, one end of the part of the first electrode layer of the capacitive structure in the upper layer close to the substrate is in contact with the top of the protrusion, and one end of the part of the first electrode layer of the capacitive structure in the lower layer away from the substrate is in contact with the bottom of the protrusion.

13. The semiconductor structure of claim 12, wherein, The capacitor structure further comprises a capacitor dielectric layer and a second electrode layer, the capacitor dielectric layer conformally covers the surface of the structure composed of the first electrode layer and the spacer layer, and the second electrode layer conformally covers the surface of the capacitor dielectric layer.

14. The semiconductor structure of claim 12, wherein, The first electrode layer of the capacitor structure is provided with a dielectric layer between adjacent first electrode layers, and the thickness of the dielectric layer on the side close to the substrate is smaller than the thickness of the dielectric layer on the side away from the substrate.

15. An electronic device, comprising: Comprising: A processing device; and a memory device electrically connected to the processing device, the memory device comprising the semiconductor structure of any one of claims 12-14.

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